10ee52b15SSoren Brinkmann /* 20ee52b15SSoren Brinkmann * Zynq clock controller 30ee52b15SSoren Brinkmann * 40ee52b15SSoren Brinkmann * Copyright (C) 2012 - 2013 Xilinx 50ee52b15SSoren Brinkmann * 60ee52b15SSoren Brinkmann * Sören Brinkmann <soren.brinkmann@xilinx.com> 70ee52b15SSoren Brinkmann * 80ee52b15SSoren Brinkmann * This program is free software: you can redistribute it and/or modify 90ee52b15SSoren Brinkmann * it under the terms of the GNU General Public License v2 as published by 100ee52b15SSoren Brinkmann * the Free Software Foundation. 110ee52b15SSoren Brinkmann * 120ee52b15SSoren Brinkmann * This program is distributed in the hope that it will be useful, 130ee52b15SSoren Brinkmann * but WITHOUT ANY WARRANTY; without even the implied warranty of 140ee52b15SSoren Brinkmann * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 150ee52b15SSoren Brinkmann * GNU General Public License for more details. 160ee52b15SSoren Brinkmann * 170ee52b15SSoren Brinkmann * You should have received a copy of the GNU General Public License 180ee52b15SSoren Brinkmann * along with this program. If not, see <http://www.gnu.org/licenses/>. 190ee52b15SSoren Brinkmann */ 200ee52b15SSoren Brinkmann 210ee52b15SSoren Brinkmann #include <linux/clk/zynq.h> 220ee52b15SSoren Brinkmann #include <linux/clk-provider.h> 230ee52b15SSoren Brinkmann #include <linux/of.h> 24b0504e39SMichal Simek #include <linux/of_address.h> 250ee52b15SSoren Brinkmann #include <linux/slab.h> 260ee52b15SSoren Brinkmann #include <linux/string.h> 270ee52b15SSoren Brinkmann #include <linux/io.h> 280ee52b15SSoren Brinkmann 29b0504e39SMichal Simek static void __iomem *zynq_clkc_base; 300ee52b15SSoren Brinkmann 31b0504e39SMichal Simek #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) 32b0504e39SMichal Simek #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) 33b0504e39SMichal Simek #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) 34b0504e39SMichal Simek #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) 35b0504e39SMichal Simek #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) 36b0504e39SMichal Simek #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) 37b0504e39SMichal Simek #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) 38b0504e39SMichal Simek #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) 39b0504e39SMichal Simek #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) 40b0504e39SMichal Simek #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) 41b0504e39SMichal Simek #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) 42b0504e39SMichal Simek #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) 43b0504e39SMichal Simek #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) 44b0504e39SMichal Simek #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) 45b0504e39SMichal Simek #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) 46b0504e39SMichal Simek #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) 47b0504e39SMichal Simek #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) 48b0504e39SMichal Simek #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) 49b0504e39SMichal Simek #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) 50b0504e39SMichal Simek #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) 51b0504e39SMichal Simek #define SLCR_621_TRUE (zynq_clkc_base + 0xc4) 52b0504e39SMichal Simek #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) 530ee52b15SSoren Brinkmann 540ee52b15SSoren Brinkmann #define NUM_MIO_PINS 54 550ee52b15SSoren Brinkmann 569268beb5SSoren Brinkmann #define DBG_CLK_CTRL_CLKACT_TRC BIT(0) 579268beb5SSoren Brinkmann #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) 589268beb5SSoren Brinkmann 590ee52b15SSoren Brinkmann enum zynq_clk { 600ee52b15SSoren Brinkmann armpll, ddrpll, iopll, 610ee52b15SSoren Brinkmann cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 620ee52b15SSoren Brinkmann ddr2x, ddr3x, dci, 630ee52b15SSoren Brinkmann lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, 640ee52b15SSoren Brinkmann sdio0, sdio1, uart0, uart1, spi0, spi1, dma, 650ee52b15SSoren Brinkmann usb0_aper, usb1_aper, gem0_aper, gem1_aper, 660ee52b15SSoren Brinkmann sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, 670ee52b15SSoren Brinkmann i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, 680ee52b15SSoren Brinkmann smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; 690ee52b15SSoren Brinkmann 700ee52b15SSoren Brinkmann static struct clk *ps_clk; 710ee52b15SSoren Brinkmann static struct clk *clks[clk_max]; 720ee52b15SSoren Brinkmann static struct clk_onecell_data clk_data; 730ee52b15SSoren Brinkmann 740ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(armpll_lock); 750ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(ddrpll_lock); 760ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(iopll_lock); 770ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(armclk_lock); 78252957ccSSoren Brinkmann static DEFINE_SPINLOCK(swdtclk_lock); 790ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(ddrclk_lock); 800ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(dciclk_lock); 810ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(gem0clk_lock); 820ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(gem1clk_lock); 830ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(canclk_lock); 840ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(canmioclk_lock); 850ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(dbgclk_lock); 860ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(aperclk_lock); 870ee52b15SSoren Brinkmann 888eaf5034SSoren Brinkmann static const char *armpll_parents[] __initconst = {"armpll_int", "ps_clk"}; 898eaf5034SSoren Brinkmann static const char *ddrpll_parents[] __initconst = {"ddrpll_int", "ps_clk"}; 908eaf5034SSoren Brinkmann static const char *iopll_parents[] __initconst = {"iopll_int", "ps_clk"}; 918eaf5034SSoren Brinkmann static const char *gem0_mux_parents[] __initconst = {"gem0_div1", "dummy_name"}; 928eaf5034SSoren Brinkmann static const char *gem1_mux_parents[] __initconst = {"gem1_div1", "dummy_name"}; 938eaf5034SSoren Brinkmann static const char *can0_mio_mux2_parents[] __initconst = {"can0_gate", 940ee52b15SSoren Brinkmann "can0_mio_mux"}; 958eaf5034SSoren Brinkmann static const char *can1_mio_mux2_parents[] __initconst = {"can1_gate", 960ee52b15SSoren Brinkmann "can1_mio_mux"}; 978eaf5034SSoren Brinkmann static const char *dbg_emio_mux_parents[] __initconst = {"dbg_div", 988eaf5034SSoren Brinkmann "dummy_name"}; 990ee52b15SSoren Brinkmann 1008eaf5034SSoren Brinkmann static const char *dbgtrc_emio_input_names[] __initconst = {"trace_emio_clk"}; 1018eaf5034SSoren Brinkmann static const char *gem0_emio_input_names[] __initconst = {"gem0_emio_clk"}; 1028eaf5034SSoren Brinkmann static const char *gem1_emio_input_names[] __initconst = {"gem1_emio_clk"}; 1038eaf5034SSoren Brinkmann static const char *swdt_ext_clk_input_names[] __initconst = {"swdt_ext_clk"}; 1040ee52b15SSoren Brinkmann 1050ee52b15SSoren Brinkmann static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 1060ee52b15SSoren Brinkmann const char *clk_name, void __iomem *fclk_ctrl_reg, 107ba52f8a9SSoren Brinkmann const char **parents, int enable) 1080ee52b15SSoren Brinkmann { 1090ee52b15SSoren Brinkmann struct clk *clk; 110ba52f8a9SSoren Brinkmann u32 enable_reg; 1110ee52b15SSoren Brinkmann char *mux_name; 1120ee52b15SSoren Brinkmann char *div0_name; 1130ee52b15SSoren Brinkmann char *div1_name; 1140ee52b15SSoren Brinkmann spinlock_t *fclk_lock; 1150ee52b15SSoren Brinkmann spinlock_t *fclk_gate_lock; 1160ee52b15SSoren Brinkmann void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; 1170ee52b15SSoren Brinkmann 1180ee52b15SSoren Brinkmann fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); 1190ee52b15SSoren Brinkmann if (!fclk_lock) 1200ee52b15SSoren Brinkmann goto err; 1210ee52b15SSoren Brinkmann fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); 1220ee52b15SSoren Brinkmann if (!fclk_gate_lock) 123f8fe36f6SFelipe Pena goto err_fclk_gate_lock; 1240ee52b15SSoren Brinkmann spin_lock_init(fclk_lock); 1250ee52b15SSoren Brinkmann spin_lock_init(fclk_gate_lock); 1260ee52b15SSoren Brinkmann 1270ee52b15SSoren Brinkmann mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); 128f8fe36f6SFelipe Pena if (!mux_name) 129f8fe36f6SFelipe Pena goto err_mux_name; 1300ee52b15SSoren Brinkmann div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 131f8fe36f6SFelipe Pena if (!div0_name) 132f8fe36f6SFelipe Pena goto err_div0_name; 1330ee52b15SSoren Brinkmann div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 134f8fe36f6SFelipe Pena if (!div1_name) 135f8fe36f6SFelipe Pena goto err_div1_name; 1360ee52b15SSoren Brinkmann 137819c1de3SJames Hogan clk = clk_register_mux(NULL, mux_name, parents, 4, 138819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, 139819c1de3SJames Hogan fclk_lock); 1400ee52b15SSoren Brinkmann 1410ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, div0_name, mux_name, 1420ee52b15SSoren Brinkmann 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 1430ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, fclk_lock); 1440ee52b15SSoren Brinkmann 1450ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, div1_name, div0_name, 1460ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, 1470ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 1480ee52b15SSoren Brinkmann fclk_lock); 1490ee52b15SSoren Brinkmann 1500ee52b15SSoren Brinkmann clks[fclk] = clk_register_gate(NULL, clk_name, 1510ee52b15SSoren Brinkmann div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 1520ee52b15SSoren Brinkmann 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 1532c97ec58SMichal Simek enable_reg = clk_readl(fclk_gate_reg) & 1; 154ba52f8a9SSoren Brinkmann if (enable && !enable_reg) { 155ba52f8a9SSoren Brinkmann if (clk_prepare_enable(clks[fclk])) 156ba52f8a9SSoren Brinkmann pr_warn("%s: FCLK%u enable failed\n", __func__, 157ba52f8a9SSoren Brinkmann fclk - fclk0); 158ba52f8a9SSoren Brinkmann } 1590ee52b15SSoren Brinkmann kfree(mux_name); 1600ee52b15SSoren Brinkmann kfree(div0_name); 1610ee52b15SSoren Brinkmann kfree(div1_name); 1620ee52b15SSoren Brinkmann 1630ee52b15SSoren Brinkmann return; 1640ee52b15SSoren Brinkmann 165f8fe36f6SFelipe Pena err_div1_name: 166f8fe36f6SFelipe Pena kfree(div0_name); 167f8fe36f6SFelipe Pena err_div0_name: 168f8fe36f6SFelipe Pena kfree(mux_name); 169f8fe36f6SFelipe Pena err_mux_name: 170f8fe36f6SFelipe Pena kfree(fclk_gate_lock); 171f8fe36f6SFelipe Pena err_fclk_gate_lock: 172f8fe36f6SFelipe Pena kfree(fclk_lock); 1730ee52b15SSoren Brinkmann err: 1740ee52b15SSoren Brinkmann clks[fclk] = ERR_PTR(-ENOMEM); 1750ee52b15SSoren Brinkmann } 1760ee52b15SSoren Brinkmann 1770ee52b15SSoren Brinkmann static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, 1780ee52b15SSoren Brinkmann enum zynq_clk clk1, const char *clk_name0, 1790ee52b15SSoren Brinkmann const char *clk_name1, void __iomem *clk_ctrl, 1800ee52b15SSoren Brinkmann const char **parents, unsigned int two_gates) 1810ee52b15SSoren Brinkmann { 1820ee52b15SSoren Brinkmann struct clk *clk; 1830ee52b15SSoren Brinkmann char *mux_name; 1840ee52b15SSoren Brinkmann char *div_name; 1850ee52b15SSoren Brinkmann spinlock_t *lock; 1860ee52b15SSoren Brinkmann 1870ee52b15SSoren Brinkmann lock = kmalloc(sizeof(*lock), GFP_KERNEL); 1880ee52b15SSoren Brinkmann if (!lock) 1890ee52b15SSoren Brinkmann goto err; 1900ee52b15SSoren Brinkmann spin_lock_init(lock); 1910ee52b15SSoren Brinkmann 1920ee52b15SSoren Brinkmann mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 1930ee52b15SSoren Brinkmann div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 1940ee52b15SSoren Brinkmann 195819c1de3SJames Hogan clk = clk_register_mux(NULL, mux_name, parents, 4, 196819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); 1970ee52b15SSoren Brinkmann 1980ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 1990ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 2000ee52b15SSoren Brinkmann 2010ee52b15SSoren Brinkmann clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, 2020ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); 2030ee52b15SSoren Brinkmann if (two_gates) 2040ee52b15SSoren Brinkmann clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, 2050ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); 2060ee52b15SSoren Brinkmann 2070ee52b15SSoren Brinkmann kfree(mux_name); 2080ee52b15SSoren Brinkmann kfree(div_name); 2090ee52b15SSoren Brinkmann 2100ee52b15SSoren Brinkmann return; 2110ee52b15SSoren Brinkmann 2120ee52b15SSoren Brinkmann err: 2130ee52b15SSoren Brinkmann clks[clk0] = ERR_PTR(-ENOMEM); 2140ee52b15SSoren Brinkmann if (two_gates) 2150ee52b15SSoren Brinkmann clks[clk1] = ERR_PTR(-ENOMEM); 2160ee52b15SSoren Brinkmann } 2170ee52b15SSoren Brinkmann 2180ee52b15SSoren Brinkmann static void __init zynq_clk_setup(struct device_node *np) 2190ee52b15SSoren Brinkmann { 2200ee52b15SSoren Brinkmann int i; 2210ee52b15SSoren Brinkmann u32 tmp; 2220ee52b15SSoren Brinkmann int ret; 2230ee52b15SSoren Brinkmann struct clk *clk; 2240ee52b15SSoren Brinkmann char *clk_name; 225ba52f8a9SSoren Brinkmann unsigned int fclk_enable = 0; 2260ee52b15SSoren Brinkmann const char *clk_output_name[clk_max]; 2270ee52b15SSoren Brinkmann const char *cpu_parents[4]; 2280ee52b15SSoren Brinkmann const char *periph_parents[4]; 2290ee52b15SSoren Brinkmann const char *swdt_ext_clk_mux_parents[2]; 2300ee52b15SSoren Brinkmann const char *can_mio_mux_parents[NUM_MIO_PINS]; 2318eaf5034SSoren Brinkmann const char *dummy_nm = "dummy_name"; 2320ee52b15SSoren Brinkmann 2330ee52b15SSoren Brinkmann pr_info("Zynq clock init\n"); 2340ee52b15SSoren Brinkmann 2350ee52b15SSoren Brinkmann /* get clock output names from DT */ 2360ee52b15SSoren Brinkmann for (i = 0; i < clk_max; i++) { 2370ee52b15SSoren Brinkmann if (of_property_read_string_index(np, "clock-output-names", 2380ee52b15SSoren Brinkmann i, &clk_output_name[i])) { 2390ee52b15SSoren Brinkmann pr_err("%s: clock output name not in DT\n", __func__); 2400ee52b15SSoren Brinkmann BUG(); 2410ee52b15SSoren Brinkmann } 2420ee52b15SSoren Brinkmann } 2430ee52b15SSoren Brinkmann cpu_parents[0] = clk_output_name[armpll]; 2440ee52b15SSoren Brinkmann cpu_parents[1] = clk_output_name[armpll]; 2450ee52b15SSoren Brinkmann cpu_parents[2] = clk_output_name[ddrpll]; 2460ee52b15SSoren Brinkmann cpu_parents[3] = clk_output_name[iopll]; 2470ee52b15SSoren Brinkmann periph_parents[0] = clk_output_name[iopll]; 2480ee52b15SSoren Brinkmann periph_parents[1] = clk_output_name[iopll]; 2490ee52b15SSoren Brinkmann periph_parents[2] = clk_output_name[armpll]; 2500ee52b15SSoren Brinkmann periph_parents[3] = clk_output_name[ddrpll]; 2510ee52b15SSoren Brinkmann 252ba52f8a9SSoren Brinkmann of_property_read_u32(np, "fclk-enable", &fclk_enable); 253ba52f8a9SSoren Brinkmann 2540ee52b15SSoren Brinkmann /* ps_clk */ 2550ee52b15SSoren Brinkmann ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 2560ee52b15SSoren Brinkmann if (ret) { 2570ee52b15SSoren Brinkmann pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); 2580ee52b15SSoren Brinkmann tmp = 33333333; 2590ee52b15SSoren Brinkmann } 2600ee52b15SSoren Brinkmann ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, 2610ee52b15SSoren Brinkmann tmp); 2620ee52b15SSoren Brinkmann 2630ee52b15SSoren Brinkmann /* PLLs */ 2640ee52b15SSoren Brinkmann clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 2650ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 0, &armpll_lock); 2660ee52b15SSoren Brinkmann clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 267819c1de3SJames Hogan armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 268819c1de3SJames Hogan SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); 2690ee52b15SSoren Brinkmann 2700ee52b15SSoren Brinkmann clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 2710ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 1, &ddrpll_lock); 2720ee52b15SSoren Brinkmann clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 273819c1de3SJames Hogan ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 274819c1de3SJames Hogan SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); 2750ee52b15SSoren Brinkmann 2760ee52b15SSoren Brinkmann clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 2770ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 2, &iopll_lock); 2780ee52b15SSoren Brinkmann clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 279819c1de3SJames Hogan iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, 280819c1de3SJames Hogan SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); 2810ee52b15SSoren Brinkmann 2820ee52b15SSoren Brinkmann /* CPU clocks */ 2832c97ec58SMichal Simek tmp = clk_readl(SLCR_621_TRUE) & 1; 284819c1de3SJames Hogan clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 285819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, 286819c1de3SJames Hogan &armclk_lock); 2870ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 2880ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 2890ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 2900ee52b15SSoren Brinkmann 2910ee52b15SSoren Brinkmann clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], 2920ee52b15SSoren Brinkmann "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2930ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); 2940ee52b15SSoren Brinkmann 2950ee52b15SSoren Brinkmann clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 2960ee52b15SSoren Brinkmann 1, 2); 2970ee52b15SSoren Brinkmann clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], 2980ee52b15SSoren Brinkmann "cpu_3or2x_div", CLK_IGNORE_UNUSED, 2990ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); 3000ee52b15SSoren Brinkmann 3010ee52b15SSoren Brinkmann clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 3020ee52b15SSoren Brinkmann 2 + tmp); 3030ee52b15SSoren Brinkmann clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 3040ee52b15SSoren Brinkmann "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 3050ee52b15SSoren Brinkmann 26, 0, &armclk_lock); 3060ee52b15SSoren Brinkmann 3070ee52b15SSoren Brinkmann clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 3080ee52b15SSoren Brinkmann 4 + 2 * tmp); 3090ee52b15SSoren Brinkmann clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], 3100ee52b15SSoren Brinkmann "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 3110ee52b15SSoren Brinkmann 0, &armclk_lock); 3120ee52b15SSoren Brinkmann 3130ee52b15SSoren Brinkmann /* Timers */ 3140ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; 3150ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { 3160ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 3170ee52b15SSoren Brinkmann swdt_ext_clk_input_names[i]); 3180ee52b15SSoren Brinkmann if (idx >= 0) 3190ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[i + 1] = 3200ee52b15SSoren Brinkmann of_clk_get_parent_name(np, idx); 3210ee52b15SSoren Brinkmann else 3220ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 3230ee52b15SSoren Brinkmann } 3240ee52b15SSoren Brinkmann clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 325819c1de3SJames Hogan swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | 326819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, 327bef4a0abSLinus Torvalds &swdtclk_lock); 3280ee52b15SSoren Brinkmann 3290ee52b15SSoren Brinkmann /* DDR clocks */ 3300ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 3310ee52b15SSoren Brinkmann SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | 3320ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 3330ee52b15SSoren Brinkmann clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], 3340ee52b15SSoren Brinkmann "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); 3350ee52b15SSoren Brinkmann clk_prepare_enable(clks[ddr2x]); 3360ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, 3370ee52b15SSoren Brinkmann SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | 3380ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 3390ee52b15SSoren Brinkmann clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], 3400ee52b15SSoren Brinkmann "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); 3410ee52b15SSoren Brinkmann clk_prepare_enable(clks[ddr3x]); 3420ee52b15SSoren Brinkmann 3430ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, 3440ee52b15SSoren Brinkmann SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 3450ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); 3460ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "dci_div1", "dci_div0", 3470ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, 3480ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 3490ee52b15SSoren Brinkmann &dciclk_lock); 3500ee52b15SSoren Brinkmann clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", 3510ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, 3520ee52b15SSoren Brinkmann &dciclk_lock); 3530ee52b15SSoren Brinkmann clk_prepare_enable(clks[dci]); 3540ee52b15SSoren Brinkmann 3550ee52b15SSoren Brinkmann /* Peripheral clocks */ 356ba52f8a9SSoren Brinkmann for (i = fclk0; i <= fclk3; i++) { 357ba52f8a9SSoren Brinkmann int enable = !!(fclk_enable & BIT(i - fclk0)); 3580ee52b15SSoren Brinkmann zynq_clk_register_fclk(i, clk_output_name[i], 3590ee52b15SSoren Brinkmann SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 360ba52f8a9SSoren Brinkmann periph_parents, enable); 361ba52f8a9SSoren Brinkmann } 3620ee52b15SSoren Brinkmann 3630ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, 3640ee52b15SSoren Brinkmann SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 3650ee52b15SSoren Brinkmann 3660ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, 3670ee52b15SSoren Brinkmann SLCR_SMC_CLK_CTRL, periph_parents, 0); 3680ee52b15SSoren Brinkmann 3690ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, 3700ee52b15SSoren Brinkmann SLCR_PCAP_CLK_CTRL, periph_parents, 0); 3710ee52b15SSoren Brinkmann 3720ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], 3730ee52b15SSoren Brinkmann clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, 3740ee52b15SSoren Brinkmann periph_parents, 1); 3750ee52b15SSoren Brinkmann 3760ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], 3770ee52b15SSoren Brinkmann clk_output_name[uart1], SLCR_UART_CLK_CTRL, 3780ee52b15SSoren Brinkmann periph_parents, 1); 3790ee52b15SSoren Brinkmann 3800ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], 3810ee52b15SSoren Brinkmann clk_output_name[spi1], SLCR_SPI_CLK_CTRL, 3820ee52b15SSoren Brinkmann periph_parents, 1); 3830ee52b15SSoren Brinkmann 3840ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { 3850ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 3860ee52b15SSoren Brinkmann gem0_emio_input_names[i]); 3870ee52b15SSoren Brinkmann if (idx >= 0) 3880ee52b15SSoren Brinkmann gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 3890ee52b15SSoren Brinkmann idx); 3900ee52b15SSoren Brinkmann } 391819c1de3SJames Hogan clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 392819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, 393819c1de3SJames Hogan &gem0clk_lock); 3940ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 3950ee52b15SSoren Brinkmann SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 3960ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 3970ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", 3980ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 3990ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4000ee52b15SSoren Brinkmann &gem0clk_lock); 401765b7d4cSSoren Brinkmann clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 402bef4a0abSLinus Torvalds CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 403bef4a0abSLinus Torvalds SLCR_GEM0_CLK_CTRL, 6, 1, 0, 404765b7d4cSSoren Brinkmann &gem0clk_lock); 4050ee52b15SSoren Brinkmann clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 4060ee52b15SSoren Brinkmann "gem0_emio_mux", CLK_SET_RATE_PARENT, 4070ee52b15SSoren Brinkmann SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 4080ee52b15SSoren Brinkmann 4090ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { 4100ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 4110ee52b15SSoren Brinkmann gem1_emio_input_names[i]); 4120ee52b15SSoren Brinkmann if (idx >= 0) 4130ee52b15SSoren Brinkmann gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 4140ee52b15SSoren Brinkmann idx); 4150ee52b15SSoren Brinkmann } 416819c1de3SJames Hogan clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 417819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, 418819c1de3SJames Hogan &gem1clk_lock); 4190ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 4200ee52b15SSoren Brinkmann SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4210ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 4220ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", 4230ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 4240ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4250ee52b15SSoren Brinkmann &gem1clk_lock); 426765b7d4cSSoren Brinkmann clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 427bef4a0abSLinus Torvalds CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 428bef4a0abSLinus Torvalds SLCR_GEM1_CLK_CTRL, 6, 1, 0, 429765b7d4cSSoren Brinkmann &gem1clk_lock); 4300ee52b15SSoren Brinkmann clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 4310ee52b15SSoren Brinkmann "gem1_emio_mux", CLK_SET_RATE_PARENT, 4320ee52b15SSoren Brinkmann SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 4330ee52b15SSoren Brinkmann 4340ee52b15SSoren Brinkmann tmp = strlen("mio_clk_00x"); 4350ee52b15SSoren Brinkmann clk_name = kmalloc(tmp, GFP_KERNEL); 4360ee52b15SSoren Brinkmann for (i = 0; i < NUM_MIO_PINS; i++) { 4370ee52b15SSoren Brinkmann int idx; 4380ee52b15SSoren Brinkmann 4390ee52b15SSoren Brinkmann snprintf(clk_name, tmp, "mio_clk_%2.2d", i); 4400ee52b15SSoren Brinkmann idx = of_property_match_string(np, "clock-names", clk_name); 4410ee52b15SSoren Brinkmann if (idx >= 0) 4420ee52b15SSoren Brinkmann can_mio_mux_parents[i] = of_clk_get_parent_name(np, 4430ee52b15SSoren Brinkmann idx); 4440ee52b15SSoren Brinkmann else 4450ee52b15SSoren Brinkmann can_mio_mux_parents[i] = dummy_nm; 4460ee52b15SSoren Brinkmann } 4470ee52b15SSoren Brinkmann kfree(clk_name); 448819c1de3SJames Hogan clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 449819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, 450819c1de3SJames Hogan &canclk_lock); 4510ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 4520ee52b15SSoren Brinkmann SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4530ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 4540ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "can_div1", "can_div0", 4550ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, 4560ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4570ee52b15SSoren Brinkmann &canclk_lock); 4580ee52b15SSoren Brinkmann clk = clk_register_gate(NULL, "can0_gate", "can_div1", 4590ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, 4600ee52b15SSoren Brinkmann &canclk_lock); 4610ee52b15SSoren Brinkmann clk = clk_register_gate(NULL, "can1_gate", "can_div1", 4620ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 4630ee52b15SSoren Brinkmann &canclk_lock); 4640ee52b15SSoren Brinkmann clk = clk_register_mux(NULL, "can0_mio_mux", 465819c1de3SJames Hogan can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 466819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, 467819c1de3SJames Hogan &canmioclk_lock); 4680ee52b15SSoren Brinkmann clk = clk_register_mux(NULL, "can1_mio_mux", 469819c1de3SJames Hogan can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 470819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, 471819c1de3SJames Hogan 0, &canmioclk_lock); 4720ee52b15SSoren Brinkmann clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 473819c1de3SJames Hogan can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 474819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, 475819c1de3SJames Hogan &canmioclk_lock); 4760ee52b15SSoren Brinkmann clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 477819c1de3SJames Hogan can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 478819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, 479819c1de3SJames Hogan 0, &canmioclk_lock); 4800ee52b15SSoren Brinkmann 4810ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 4820ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 4830ee52b15SSoren Brinkmann dbgtrc_emio_input_names[i]); 4840ee52b15SSoren Brinkmann if (idx >= 0) 4850ee52b15SSoren Brinkmann dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 4860ee52b15SSoren Brinkmann idx); 4870ee52b15SSoren Brinkmann } 488819c1de3SJames Hogan clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 489819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, 490819c1de3SJames Hogan &dbgclk_lock); 4910ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 4920ee52b15SSoren Brinkmann SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4930ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 494819c1de3SJames Hogan clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 495819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, 496819c1de3SJames Hogan &dbgclk_lock); 4970ee52b15SSoren Brinkmann clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 4980ee52b15SSoren Brinkmann "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 4990ee52b15SSoren Brinkmann 0, 0, &dbgclk_lock); 5000ee52b15SSoren Brinkmann clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], 5010ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 5020ee52b15SSoren Brinkmann &dbgclk_lock); 5030ee52b15SSoren Brinkmann 5049268beb5SSoren Brinkmann /* leave debug clocks in the state the bootloader set them up to */ 5059268beb5SSoren Brinkmann tmp = clk_readl(SLCR_DBG_CLK_CTRL); 5069268beb5SSoren Brinkmann if (tmp & DBG_CLK_CTRL_CLKACT_TRC) 5079268beb5SSoren Brinkmann if (clk_prepare_enable(clks[dbg_trc])) 5089268beb5SSoren Brinkmann pr_warn("%s: trace clk enable failed\n", __func__); 5099268beb5SSoren Brinkmann if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) 5109268beb5SSoren Brinkmann if (clk_prepare_enable(clks[dbg_apb])) 5119268beb5SSoren Brinkmann pr_warn("%s: debug APB clk enable failed\n", __func__); 5129268beb5SSoren Brinkmann 5130ee52b15SSoren Brinkmann /* One gated clock for all APER clocks. */ 5140ee52b15SSoren Brinkmann clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 5150ee52b15SSoren Brinkmann clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 5160ee52b15SSoren Brinkmann &aperclk_lock); 5170ee52b15SSoren Brinkmann clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], 5180ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, 5190ee52b15SSoren Brinkmann &aperclk_lock); 5200ee52b15SSoren Brinkmann clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], 5210ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, 5220ee52b15SSoren Brinkmann &aperclk_lock); 5230ee52b15SSoren Brinkmann clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], 5240ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, 5250ee52b15SSoren Brinkmann &aperclk_lock); 5260ee52b15SSoren Brinkmann clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], 5270ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, 5280ee52b15SSoren Brinkmann &aperclk_lock); 5290ee52b15SSoren Brinkmann clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], 5300ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, 5310ee52b15SSoren Brinkmann &aperclk_lock); 5320ee52b15SSoren Brinkmann clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], 5330ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, 5340ee52b15SSoren Brinkmann &aperclk_lock); 5350ee52b15SSoren Brinkmann clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], 5360ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, 5370ee52b15SSoren Brinkmann &aperclk_lock); 5380ee52b15SSoren Brinkmann clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], 5390ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, 5400ee52b15SSoren Brinkmann &aperclk_lock); 5410ee52b15SSoren Brinkmann clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], 5420ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, 5430ee52b15SSoren Brinkmann &aperclk_lock); 5440ee52b15SSoren Brinkmann clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], 5450ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, 5460ee52b15SSoren Brinkmann &aperclk_lock); 5470ee52b15SSoren Brinkmann clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], 5480ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, 5490ee52b15SSoren Brinkmann &aperclk_lock); 5500ee52b15SSoren Brinkmann clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], 5510ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, 5520ee52b15SSoren Brinkmann &aperclk_lock); 5530ee52b15SSoren Brinkmann clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], 5540ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, 5550ee52b15SSoren Brinkmann &aperclk_lock); 5560ee52b15SSoren Brinkmann clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], 5570ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, 5580ee52b15SSoren Brinkmann &aperclk_lock); 5590ee52b15SSoren Brinkmann clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], 5600ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, 5610ee52b15SSoren Brinkmann &aperclk_lock); 5620ee52b15SSoren Brinkmann clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], 5630ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, 5640ee52b15SSoren Brinkmann &aperclk_lock); 5650ee52b15SSoren Brinkmann clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], 5660ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, 5670ee52b15SSoren Brinkmann &aperclk_lock); 5680ee52b15SSoren Brinkmann 5690ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(clks); i++) { 5700ee52b15SSoren Brinkmann if (IS_ERR(clks[i])) { 5710ee52b15SSoren Brinkmann pr_err("Zynq clk %d: register failed with %ld\n", 5720ee52b15SSoren Brinkmann i, PTR_ERR(clks[i])); 5730ee52b15SSoren Brinkmann BUG(); 5740ee52b15SSoren Brinkmann } 5750ee52b15SSoren Brinkmann } 5760ee52b15SSoren Brinkmann 5770ee52b15SSoren Brinkmann clk_data.clks = clks; 5780ee52b15SSoren Brinkmann clk_data.clk_num = ARRAY_SIZE(clks); 5790ee52b15SSoren Brinkmann of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 5800ee52b15SSoren Brinkmann } 5810ee52b15SSoren Brinkmann 5820ee52b15SSoren Brinkmann CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); 5830ee52b15SSoren Brinkmann 584b0504e39SMichal Simek void __init zynq_clock_init(void) 5850ee52b15SSoren Brinkmann { 586b0504e39SMichal Simek struct device_node *np; 587b0504e39SMichal Simek struct device_node *slcr; 588b0504e39SMichal Simek struct resource res; 589b0504e39SMichal Simek 590b0504e39SMichal Simek np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); 591b0504e39SMichal Simek if (!np) { 592b0504e39SMichal Simek pr_err("%s: clkc node not found\n", __func__); 593b0504e39SMichal Simek goto np_err; 594b0504e39SMichal Simek } 595b0504e39SMichal Simek 596b0504e39SMichal Simek if (of_address_to_resource(np, 0, &res)) { 597b0504e39SMichal Simek pr_err("%s: failed to get resource\n", np->name); 598b0504e39SMichal Simek goto np_err; 599b0504e39SMichal Simek } 600b0504e39SMichal Simek 601b0504e39SMichal Simek slcr = of_get_parent(np); 602b0504e39SMichal Simek 603b0504e39SMichal Simek if (slcr->data) { 604b0504e39SMichal Simek zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; 605b0504e39SMichal Simek } else { 606b0504e39SMichal Simek pr_err("%s: Unable to get I/O memory\n", np->name); 607b0504e39SMichal Simek of_node_put(slcr); 608b0504e39SMichal Simek goto np_err; 609b0504e39SMichal Simek } 610b0504e39SMichal Simek 611b0504e39SMichal Simek pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); 612b0504e39SMichal Simek 613b0504e39SMichal Simek of_node_put(slcr); 614b0504e39SMichal Simek of_node_put(np); 615b0504e39SMichal Simek 616b0504e39SMichal Simek return; 617b0504e39SMichal Simek 618b0504e39SMichal Simek np_err: 619b0504e39SMichal Simek of_node_put(np); 620b0504e39SMichal Simek BUG(); 6210ee52b15SSoren Brinkmann } 622