10ee52b15SSoren Brinkmann /* 20ee52b15SSoren Brinkmann * Zynq clock controller 30ee52b15SSoren Brinkmann * 40ee52b15SSoren Brinkmann * Copyright (C) 2012 - 2013 Xilinx 50ee52b15SSoren Brinkmann * 60ee52b15SSoren Brinkmann * Sören Brinkmann <soren.brinkmann@xilinx.com> 70ee52b15SSoren Brinkmann * 80ee52b15SSoren Brinkmann * This program is free software: you can redistribute it and/or modify 90ee52b15SSoren Brinkmann * it under the terms of the GNU General Public License v2 as published by 100ee52b15SSoren Brinkmann * the Free Software Foundation. 110ee52b15SSoren Brinkmann * 120ee52b15SSoren Brinkmann * This program is distributed in the hope that it will be useful, 130ee52b15SSoren Brinkmann * but WITHOUT ANY WARRANTY; without even the implied warranty of 140ee52b15SSoren Brinkmann * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 150ee52b15SSoren Brinkmann * GNU General Public License for more details. 160ee52b15SSoren Brinkmann * 170ee52b15SSoren Brinkmann * You should have received a copy of the GNU General Public License 180ee52b15SSoren Brinkmann * along with this program. If not, see <http://www.gnu.org/licenses/>. 190ee52b15SSoren Brinkmann */ 200ee52b15SSoren Brinkmann 210ee52b15SSoren Brinkmann #include <linux/clk/zynq.h> 220ee52b15SSoren Brinkmann #include <linux/clk-provider.h> 230ee52b15SSoren Brinkmann #include <linux/of.h> 240ee52b15SSoren Brinkmann #include <linux/slab.h> 250ee52b15SSoren Brinkmann #include <linux/string.h> 260ee52b15SSoren Brinkmann #include <linux/io.h> 270ee52b15SSoren Brinkmann 280ee52b15SSoren Brinkmann static void __iomem *zynq_slcr_base_priv; 290ee52b15SSoren Brinkmann 300ee52b15SSoren Brinkmann #define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) 310ee52b15SSoren Brinkmann #define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) 320ee52b15SSoren Brinkmann #define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) 330ee52b15SSoren Brinkmann #define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) 340ee52b15SSoren Brinkmann #define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) 350ee52b15SSoren Brinkmann #define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) 360ee52b15SSoren Brinkmann #define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) 370ee52b15SSoren Brinkmann #define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) 380ee52b15SSoren Brinkmann #define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) 390ee52b15SSoren Brinkmann #define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) 400ee52b15SSoren Brinkmann #define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) 410ee52b15SSoren Brinkmann #define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) 420ee52b15SSoren Brinkmann #define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) 430ee52b15SSoren Brinkmann #define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) 440ee52b15SSoren Brinkmann #define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) 450ee52b15SSoren Brinkmann #define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) 460ee52b15SSoren Brinkmann #define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) 470ee52b15SSoren Brinkmann #define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) 480ee52b15SSoren Brinkmann #define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) 490ee52b15SSoren Brinkmann #define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) 500ee52b15SSoren Brinkmann #define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) 510ee52b15SSoren Brinkmann #define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) 520ee52b15SSoren Brinkmann 530ee52b15SSoren Brinkmann #define NUM_MIO_PINS 54 540ee52b15SSoren Brinkmann 550ee52b15SSoren Brinkmann enum zynq_clk { 560ee52b15SSoren Brinkmann armpll, ddrpll, iopll, 570ee52b15SSoren Brinkmann cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 580ee52b15SSoren Brinkmann ddr2x, ddr3x, dci, 590ee52b15SSoren Brinkmann lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, 600ee52b15SSoren Brinkmann sdio0, sdio1, uart0, uart1, spi0, spi1, dma, 610ee52b15SSoren Brinkmann usb0_aper, usb1_aper, gem0_aper, gem1_aper, 620ee52b15SSoren Brinkmann sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, 630ee52b15SSoren Brinkmann i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, 640ee52b15SSoren Brinkmann smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; 650ee52b15SSoren Brinkmann 660ee52b15SSoren Brinkmann static struct clk *ps_clk; 670ee52b15SSoren Brinkmann static struct clk *clks[clk_max]; 680ee52b15SSoren Brinkmann static struct clk_onecell_data clk_data; 690ee52b15SSoren Brinkmann 700ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(armpll_lock); 710ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(ddrpll_lock); 720ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(iopll_lock); 730ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(armclk_lock); 74252957ccSSoren Brinkmann static DEFINE_SPINLOCK(swdtclk_lock); 750ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(ddrclk_lock); 760ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(dciclk_lock); 770ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(gem0clk_lock); 780ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(gem1clk_lock); 790ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(canclk_lock); 800ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(canmioclk_lock); 810ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(dbgclk_lock); 820ee52b15SSoren Brinkmann static DEFINE_SPINLOCK(aperclk_lock); 830ee52b15SSoren Brinkmann 840ee52b15SSoren Brinkmann static const char dummy_nm[] __initconst = "dummy_name"; 850ee52b15SSoren Brinkmann 860ee52b15SSoren Brinkmann static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; 870ee52b15SSoren Brinkmann static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; 880ee52b15SSoren Brinkmann static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; 890ee52b15SSoren Brinkmann static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm}; 900ee52b15SSoren Brinkmann static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm}; 910ee52b15SSoren Brinkmann static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", 920ee52b15SSoren Brinkmann "can0_mio_mux"}; 930ee52b15SSoren Brinkmann static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", 940ee52b15SSoren Brinkmann "can1_mio_mux"}; 950ee52b15SSoren Brinkmann static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", 960ee52b15SSoren Brinkmann dummy_nm}; 970ee52b15SSoren Brinkmann 980ee52b15SSoren Brinkmann static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; 990ee52b15SSoren Brinkmann static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; 1000ee52b15SSoren Brinkmann static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; 1010ee52b15SSoren Brinkmann static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; 1020ee52b15SSoren Brinkmann 1030ee52b15SSoren Brinkmann static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 1040ee52b15SSoren Brinkmann const char *clk_name, void __iomem *fclk_ctrl_reg, 105ba52f8a9SSoren Brinkmann const char **parents, int enable) 1060ee52b15SSoren Brinkmann { 1070ee52b15SSoren Brinkmann struct clk *clk; 108ba52f8a9SSoren Brinkmann u32 enable_reg; 1090ee52b15SSoren Brinkmann char *mux_name; 1100ee52b15SSoren Brinkmann char *div0_name; 1110ee52b15SSoren Brinkmann char *div1_name; 1120ee52b15SSoren Brinkmann spinlock_t *fclk_lock; 1130ee52b15SSoren Brinkmann spinlock_t *fclk_gate_lock; 1140ee52b15SSoren Brinkmann void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; 1150ee52b15SSoren Brinkmann 1160ee52b15SSoren Brinkmann fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); 1170ee52b15SSoren Brinkmann if (!fclk_lock) 1180ee52b15SSoren Brinkmann goto err; 1190ee52b15SSoren Brinkmann fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); 1200ee52b15SSoren Brinkmann if (!fclk_gate_lock) 121f8fe36f6SFelipe Pena goto err_fclk_gate_lock; 1220ee52b15SSoren Brinkmann spin_lock_init(fclk_lock); 1230ee52b15SSoren Brinkmann spin_lock_init(fclk_gate_lock); 1240ee52b15SSoren Brinkmann 1250ee52b15SSoren Brinkmann mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); 126f8fe36f6SFelipe Pena if (!mux_name) 127f8fe36f6SFelipe Pena goto err_mux_name; 1280ee52b15SSoren Brinkmann div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 129f8fe36f6SFelipe Pena if (!div0_name) 130f8fe36f6SFelipe Pena goto err_div0_name; 1310ee52b15SSoren Brinkmann div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 132f8fe36f6SFelipe Pena if (!div1_name) 133f8fe36f6SFelipe Pena goto err_div1_name; 1340ee52b15SSoren Brinkmann 135819c1de3SJames Hogan clk = clk_register_mux(NULL, mux_name, parents, 4, 136819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, 137819c1de3SJames Hogan fclk_lock); 1380ee52b15SSoren Brinkmann 1390ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, div0_name, mux_name, 1400ee52b15SSoren Brinkmann 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 1410ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, fclk_lock); 1420ee52b15SSoren Brinkmann 1430ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, div1_name, div0_name, 1440ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, 1450ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 1460ee52b15SSoren Brinkmann fclk_lock); 1470ee52b15SSoren Brinkmann 1480ee52b15SSoren Brinkmann clks[fclk] = clk_register_gate(NULL, clk_name, 1490ee52b15SSoren Brinkmann div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 1500ee52b15SSoren Brinkmann 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 1512c97ec58SMichal Simek enable_reg = clk_readl(fclk_gate_reg) & 1; 152ba52f8a9SSoren Brinkmann if (enable && !enable_reg) { 153ba52f8a9SSoren Brinkmann if (clk_prepare_enable(clks[fclk])) 154ba52f8a9SSoren Brinkmann pr_warn("%s: FCLK%u enable failed\n", __func__, 155ba52f8a9SSoren Brinkmann fclk - fclk0); 156ba52f8a9SSoren Brinkmann } 1570ee52b15SSoren Brinkmann kfree(mux_name); 1580ee52b15SSoren Brinkmann kfree(div0_name); 1590ee52b15SSoren Brinkmann kfree(div1_name); 1600ee52b15SSoren Brinkmann 1610ee52b15SSoren Brinkmann return; 1620ee52b15SSoren Brinkmann 163f8fe36f6SFelipe Pena err_div1_name: 164f8fe36f6SFelipe Pena kfree(div0_name); 165f8fe36f6SFelipe Pena err_div0_name: 166f8fe36f6SFelipe Pena kfree(mux_name); 167f8fe36f6SFelipe Pena err_mux_name: 168f8fe36f6SFelipe Pena kfree(fclk_gate_lock); 169f8fe36f6SFelipe Pena err_fclk_gate_lock: 170f8fe36f6SFelipe Pena kfree(fclk_lock); 1710ee52b15SSoren Brinkmann err: 1720ee52b15SSoren Brinkmann clks[fclk] = ERR_PTR(-ENOMEM); 1730ee52b15SSoren Brinkmann } 1740ee52b15SSoren Brinkmann 1750ee52b15SSoren Brinkmann static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, 1760ee52b15SSoren Brinkmann enum zynq_clk clk1, const char *clk_name0, 1770ee52b15SSoren Brinkmann const char *clk_name1, void __iomem *clk_ctrl, 1780ee52b15SSoren Brinkmann const char **parents, unsigned int two_gates) 1790ee52b15SSoren Brinkmann { 1800ee52b15SSoren Brinkmann struct clk *clk; 1810ee52b15SSoren Brinkmann char *mux_name; 1820ee52b15SSoren Brinkmann char *div_name; 1830ee52b15SSoren Brinkmann spinlock_t *lock; 1840ee52b15SSoren Brinkmann 1850ee52b15SSoren Brinkmann lock = kmalloc(sizeof(*lock), GFP_KERNEL); 1860ee52b15SSoren Brinkmann if (!lock) 1870ee52b15SSoren Brinkmann goto err; 1880ee52b15SSoren Brinkmann spin_lock_init(lock); 1890ee52b15SSoren Brinkmann 1900ee52b15SSoren Brinkmann mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 1910ee52b15SSoren Brinkmann div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 1920ee52b15SSoren Brinkmann 193819c1de3SJames Hogan clk = clk_register_mux(NULL, mux_name, parents, 4, 194819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); 1950ee52b15SSoren Brinkmann 1960ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 1970ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 1980ee52b15SSoren Brinkmann 1990ee52b15SSoren Brinkmann clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, 2000ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); 2010ee52b15SSoren Brinkmann if (two_gates) 2020ee52b15SSoren Brinkmann clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, 2030ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); 2040ee52b15SSoren Brinkmann 2050ee52b15SSoren Brinkmann kfree(mux_name); 2060ee52b15SSoren Brinkmann kfree(div_name); 2070ee52b15SSoren Brinkmann 2080ee52b15SSoren Brinkmann return; 2090ee52b15SSoren Brinkmann 2100ee52b15SSoren Brinkmann err: 2110ee52b15SSoren Brinkmann clks[clk0] = ERR_PTR(-ENOMEM); 2120ee52b15SSoren Brinkmann if (two_gates) 2130ee52b15SSoren Brinkmann clks[clk1] = ERR_PTR(-ENOMEM); 2140ee52b15SSoren Brinkmann } 2150ee52b15SSoren Brinkmann 2160ee52b15SSoren Brinkmann static void __init zynq_clk_setup(struct device_node *np) 2170ee52b15SSoren Brinkmann { 2180ee52b15SSoren Brinkmann int i; 2190ee52b15SSoren Brinkmann u32 tmp; 2200ee52b15SSoren Brinkmann int ret; 2210ee52b15SSoren Brinkmann struct clk *clk; 2220ee52b15SSoren Brinkmann char *clk_name; 223ba52f8a9SSoren Brinkmann unsigned int fclk_enable = 0; 2240ee52b15SSoren Brinkmann const char *clk_output_name[clk_max]; 2250ee52b15SSoren Brinkmann const char *cpu_parents[4]; 2260ee52b15SSoren Brinkmann const char *periph_parents[4]; 2270ee52b15SSoren Brinkmann const char *swdt_ext_clk_mux_parents[2]; 2280ee52b15SSoren Brinkmann const char *can_mio_mux_parents[NUM_MIO_PINS]; 2290ee52b15SSoren Brinkmann 2300ee52b15SSoren Brinkmann pr_info("Zynq clock init\n"); 2310ee52b15SSoren Brinkmann 2320ee52b15SSoren Brinkmann /* get clock output names from DT */ 2330ee52b15SSoren Brinkmann for (i = 0; i < clk_max; i++) { 2340ee52b15SSoren Brinkmann if (of_property_read_string_index(np, "clock-output-names", 2350ee52b15SSoren Brinkmann i, &clk_output_name[i])) { 2360ee52b15SSoren Brinkmann pr_err("%s: clock output name not in DT\n", __func__); 2370ee52b15SSoren Brinkmann BUG(); 2380ee52b15SSoren Brinkmann } 2390ee52b15SSoren Brinkmann } 2400ee52b15SSoren Brinkmann cpu_parents[0] = clk_output_name[armpll]; 2410ee52b15SSoren Brinkmann cpu_parents[1] = clk_output_name[armpll]; 2420ee52b15SSoren Brinkmann cpu_parents[2] = clk_output_name[ddrpll]; 2430ee52b15SSoren Brinkmann cpu_parents[3] = clk_output_name[iopll]; 2440ee52b15SSoren Brinkmann periph_parents[0] = clk_output_name[iopll]; 2450ee52b15SSoren Brinkmann periph_parents[1] = clk_output_name[iopll]; 2460ee52b15SSoren Brinkmann periph_parents[2] = clk_output_name[armpll]; 2470ee52b15SSoren Brinkmann periph_parents[3] = clk_output_name[ddrpll]; 2480ee52b15SSoren Brinkmann 249ba52f8a9SSoren Brinkmann of_property_read_u32(np, "fclk-enable", &fclk_enable); 250ba52f8a9SSoren Brinkmann 2510ee52b15SSoren Brinkmann /* ps_clk */ 2520ee52b15SSoren Brinkmann ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 2530ee52b15SSoren Brinkmann if (ret) { 2540ee52b15SSoren Brinkmann pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); 2550ee52b15SSoren Brinkmann tmp = 33333333; 2560ee52b15SSoren Brinkmann } 2570ee52b15SSoren Brinkmann ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, 2580ee52b15SSoren Brinkmann tmp); 2590ee52b15SSoren Brinkmann 2600ee52b15SSoren Brinkmann /* PLLs */ 2610ee52b15SSoren Brinkmann clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 2620ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 0, &armpll_lock); 2630ee52b15SSoren Brinkmann clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 264819c1de3SJames Hogan armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 265819c1de3SJames Hogan SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); 2660ee52b15SSoren Brinkmann 2670ee52b15SSoren Brinkmann clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 2680ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 1, &ddrpll_lock); 2690ee52b15SSoren Brinkmann clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 270819c1de3SJames Hogan ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 271819c1de3SJames Hogan SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); 2720ee52b15SSoren Brinkmann 2730ee52b15SSoren Brinkmann clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 2740ee52b15SSoren Brinkmann SLCR_PLL_STATUS, 2, &iopll_lock); 2750ee52b15SSoren Brinkmann clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 276819c1de3SJames Hogan iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, 277819c1de3SJames Hogan SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); 2780ee52b15SSoren Brinkmann 2790ee52b15SSoren Brinkmann /* CPU clocks */ 2802c97ec58SMichal Simek tmp = clk_readl(SLCR_621_TRUE) & 1; 281819c1de3SJames Hogan clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 282819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, 283819c1de3SJames Hogan &armclk_lock); 2840ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 2850ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 2860ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 2870ee52b15SSoren Brinkmann 2880ee52b15SSoren Brinkmann clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], 2890ee52b15SSoren Brinkmann "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2900ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); 2910ee52b15SSoren Brinkmann 2920ee52b15SSoren Brinkmann clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 2930ee52b15SSoren Brinkmann 1, 2); 2940ee52b15SSoren Brinkmann clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], 2950ee52b15SSoren Brinkmann "cpu_3or2x_div", CLK_IGNORE_UNUSED, 2960ee52b15SSoren Brinkmann SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); 2970ee52b15SSoren Brinkmann 2980ee52b15SSoren Brinkmann clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 2990ee52b15SSoren Brinkmann 2 + tmp); 3000ee52b15SSoren Brinkmann clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 3010ee52b15SSoren Brinkmann "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 3020ee52b15SSoren Brinkmann 26, 0, &armclk_lock); 3030ee52b15SSoren Brinkmann 3040ee52b15SSoren Brinkmann clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 3050ee52b15SSoren Brinkmann 4 + 2 * tmp); 3060ee52b15SSoren Brinkmann clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], 3070ee52b15SSoren Brinkmann "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 3080ee52b15SSoren Brinkmann 0, &armclk_lock); 3090ee52b15SSoren Brinkmann 3100ee52b15SSoren Brinkmann /* Timers */ 3110ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; 3120ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { 3130ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 3140ee52b15SSoren Brinkmann swdt_ext_clk_input_names[i]); 3150ee52b15SSoren Brinkmann if (idx >= 0) 3160ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[i + 1] = 3170ee52b15SSoren Brinkmann of_clk_get_parent_name(np, idx); 3180ee52b15SSoren Brinkmann else 3190ee52b15SSoren Brinkmann swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 3200ee52b15SSoren Brinkmann } 3210ee52b15SSoren Brinkmann clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 322819c1de3SJames Hogan swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | 323819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, 324bef4a0abSLinus Torvalds &swdtclk_lock); 3250ee52b15SSoren Brinkmann 3260ee52b15SSoren Brinkmann /* DDR clocks */ 3270ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 3280ee52b15SSoren Brinkmann SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | 3290ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 3300ee52b15SSoren Brinkmann clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], 3310ee52b15SSoren Brinkmann "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); 3320ee52b15SSoren Brinkmann clk_prepare_enable(clks[ddr2x]); 3330ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, 3340ee52b15SSoren Brinkmann SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | 3350ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 3360ee52b15SSoren Brinkmann clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], 3370ee52b15SSoren Brinkmann "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); 3380ee52b15SSoren Brinkmann clk_prepare_enable(clks[ddr3x]); 3390ee52b15SSoren Brinkmann 3400ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, 3410ee52b15SSoren Brinkmann SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 3420ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); 3430ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "dci_div1", "dci_div0", 3440ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, 3450ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 3460ee52b15SSoren Brinkmann &dciclk_lock); 3470ee52b15SSoren Brinkmann clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", 3480ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, 3490ee52b15SSoren Brinkmann &dciclk_lock); 3500ee52b15SSoren Brinkmann clk_prepare_enable(clks[dci]); 3510ee52b15SSoren Brinkmann 3520ee52b15SSoren Brinkmann /* Peripheral clocks */ 353ba52f8a9SSoren Brinkmann for (i = fclk0; i <= fclk3; i++) { 354ba52f8a9SSoren Brinkmann int enable = !!(fclk_enable & BIT(i - fclk0)); 3550ee52b15SSoren Brinkmann zynq_clk_register_fclk(i, clk_output_name[i], 3560ee52b15SSoren Brinkmann SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 357ba52f8a9SSoren Brinkmann periph_parents, enable); 358ba52f8a9SSoren Brinkmann } 3590ee52b15SSoren Brinkmann 3600ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, 3610ee52b15SSoren Brinkmann SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 3620ee52b15SSoren Brinkmann 3630ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, 3640ee52b15SSoren Brinkmann SLCR_SMC_CLK_CTRL, periph_parents, 0); 3650ee52b15SSoren Brinkmann 3660ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, 3670ee52b15SSoren Brinkmann SLCR_PCAP_CLK_CTRL, periph_parents, 0); 3680ee52b15SSoren Brinkmann 3690ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], 3700ee52b15SSoren Brinkmann clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, 3710ee52b15SSoren Brinkmann periph_parents, 1); 3720ee52b15SSoren Brinkmann 3730ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], 3740ee52b15SSoren Brinkmann clk_output_name[uart1], SLCR_UART_CLK_CTRL, 3750ee52b15SSoren Brinkmann periph_parents, 1); 3760ee52b15SSoren Brinkmann 3770ee52b15SSoren Brinkmann zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], 3780ee52b15SSoren Brinkmann clk_output_name[spi1], SLCR_SPI_CLK_CTRL, 3790ee52b15SSoren Brinkmann periph_parents, 1); 3800ee52b15SSoren Brinkmann 3810ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { 3820ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 3830ee52b15SSoren Brinkmann gem0_emio_input_names[i]); 3840ee52b15SSoren Brinkmann if (idx >= 0) 3850ee52b15SSoren Brinkmann gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 3860ee52b15SSoren Brinkmann idx); 3870ee52b15SSoren Brinkmann } 388819c1de3SJames Hogan clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 389819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, 390819c1de3SJames Hogan &gem0clk_lock); 3910ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 3920ee52b15SSoren Brinkmann SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 3930ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 3940ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", 3950ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 3960ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 3970ee52b15SSoren Brinkmann &gem0clk_lock); 398765b7d4cSSoren Brinkmann clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 399bef4a0abSLinus Torvalds CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 400bef4a0abSLinus Torvalds SLCR_GEM0_CLK_CTRL, 6, 1, 0, 401765b7d4cSSoren Brinkmann &gem0clk_lock); 4020ee52b15SSoren Brinkmann clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 4030ee52b15SSoren Brinkmann "gem0_emio_mux", CLK_SET_RATE_PARENT, 4040ee52b15SSoren Brinkmann SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 4050ee52b15SSoren Brinkmann 4060ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { 4070ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 4080ee52b15SSoren Brinkmann gem1_emio_input_names[i]); 4090ee52b15SSoren Brinkmann if (idx >= 0) 4100ee52b15SSoren Brinkmann gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 4110ee52b15SSoren Brinkmann idx); 4120ee52b15SSoren Brinkmann } 413819c1de3SJames Hogan clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 414819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, 415819c1de3SJames Hogan &gem1clk_lock); 4160ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 4170ee52b15SSoren Brinkmann SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4180ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 4190ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", 4200ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 4210ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4220ee52b15SSoren Brinkmann &gem1clk_lock); 423765b7d4cSSoren Brinkmann clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 424bef4a0abSLinus Torvalds CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 425bef4a0abSLinus Torvalds SLCR_GEM1_CLK_CTRL, 6, 1, 0, 426765b7d4cSSoren Brinkmann &gem1clk_lock); 4270ee52b15SSoren Brinkmann clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 4280ee52b15SSoren Brinkmann "gem1_emio_mux", CLK_SET_RATE_PARENT, 4290ee52b15SSoren Brinkmann SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 4300ee52b15SSoren Brinkmann 4310ee52b15SSoren Brinkmann tmp = strlen("mio_clk_00x"); 4320ee52b15SSoren Brinkmann clk_name = kmalloc(tmp, GFP_KERNEL); 4330ee52b15SSoren Brinkmann for (i = 0; i < NUM_MIO_PINS; i++) { 4340ee52b15SSoren Brinkmann int idx; 4350ee52b15SSoren Brinkmann 4360ee52b15SSoren Brinkmann snprintf(clk_name, tmp, "mio_clk_%2.2d", i); 4370ee52b15SSoren Brinkmann idx = of_property_match_string(np, "clock-names", clk_name); 4380ee52b15SSoren Brinkmann if (idx >= 0) 4390ee52b15SSoren Brinkmann can_mio_mux_parents[i] = of_clk_get_parent_name(np, 4400ee52b15SSoren Brinkmann idx); 4410ee52b15SSoren Brinkmann else 4420ee52b15SSoren Brinkmann can_mio_mux_parents[i] = dummy_nm; 4430ee52b15SSoren Brinkmann } 4440ee52b15SSoren Brinkmann kfree(clk_name); 445819c1de3SJames Hogan clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 446819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, 447819c1de3SJames Hogan &canclk_lock); 4480ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 4490ee52b15SSoren Brinkmann SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4500ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 4510ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "can_div1", "can_div0", 4520ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, 4530ee52b15SSoren Brinkmann CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 4540ee52b15SSoren Brinkmann &canclk_lock); 4550ee52b15SSoren Brinkmann clk = clk_register_gate(NULL, "can0_gate", "can_div1", 4560ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, 4570ee52b15SSoren Brinkmann &canclk_lock); 4580ee52b15SSoren Brinkmann clk = clk_register_gate(NULL, "can1_gate", "can_div1", 4590ee52b15SSoren Brinkmann CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 4600ee52b15SSoren Brinkmann &canclk_lock); 4610ee52b15SSoren Brinkmann clk = clk_register_mux(NULL, "can0_mio_mux", 462819c1de3SJames Hogan can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 463819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, 464819c1de3SJames Hogan &canmioclk_lock); 4650ee52b15SSoren Brinkmann clk = clk_register_mux(NULL, "can1_mio_mux", 466819c1de3SJames Hogan can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 467819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, 468819c1de3SJames Hogan 0, &canmioclk_lock); 4690ee52b15SSoren Brinkmann clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 470819c1de3SJames Hogan can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 471819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, 472819c1de3SJames Hogan &canmioclk_lock); 4730ee52b15SSoren Brinkmann clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 474819c1de3SJames Hogan can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 475819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, 476819c1de3SJames Hogan 0, &canmioclk_lock); 4770ee52b15SSoren Brinkmann 4780ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 4790ee52b15SSoren Brinkmann int idx = of_property_match_string(np, "clock-names", 4800ee52b15SSoren Brinkmann dbgtrc_emio_input_names[i]); 4810ee52b15SSoren Brinkmann if (idx >= 0) 4820ee52b15SSoren Brinkmann dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 4830ee52b15SSoren Brinkmann idx); 4840ee52b15SSoren Brinkmann } 485819c1de3SJames Hogan clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 486819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, 487819c1de3SJames Hogan &dbgclk_lock); 4880ee52b15SSoren Brinkmann clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 4890ee52b15SSoren Brinkmann SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 4900ee52b15SSoren Brinkmann CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 491819c1de3SJames Hogan clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 492819c1de3SJames Hogan CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, 493819c1de3SJames Hogan &dbgclk_lock); 4940ee52b15SSoren Brinkmann clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 4950ee52b15SSoren Brinkmann "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 4960ee52b15SSoren Brinkmann 0, 0, &dbgclk_lock); 4970ee52b15SSoren Brinkmann clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], 4980ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 4990ee52b15SSoren Brinkmann &dbgclk_lock); 5000ee52b15SSoren Brinkmann 5010ee52b15SSoren Brinkmann /* One gated clock for all APER clocks. */ 5020ee52b15SSoren Brinkmann clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 5030ee52b15SSoren Brinkmann clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 5040ee52b15SSoren Brinkmann &aperclk_lock); 5050ee52b15SSoren Brinkmann clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], 5060ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, 5070ee52b15SSoren Brinkmann &aperclk_lock); 5080ee52b15SSoren Brinkmann clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], 5090ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, 5100ee52b15SSoren Brinkmann &aperclk_lock); 5110ee52b15SSoren Brinkmann clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], 5120ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, 5130ee52b15SSoren Brinkmann &aperclk_lock); 5140ee52b15SSoren Brinkmann clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], 5150ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, 5160ee52b15SSoren Brinkmann &aperclk_lock); 5170ee52b15SSoren Brinkmann clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], 5180ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, 5190ee52b15SSoren Brinkmann &aperclk_lock); 5200ee52b15SSoren Brinkmann clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], 5210ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, 5220ee52b15SSoren Brinkmann &aperclk_lock); 5230ee52b15SSoren Brinkmann clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], 5240ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, 5250ee52b15SSoren Brinkmann &aperclk_lock); 5260ee52b15SSoren Brinkmann clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], 5270ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, 5280ee52b15SSoren Brinkmann &aperclk_lock); 5290ee52b15SSoren Brinkmann clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], 5300ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, 5310ee52b15SSoren Brinkmann &aperclk_lock); 5320ee52b15SSoren Brinkmann clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], 5330ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, 5340ee52b15SSoren Brinkmann &aperclk_lock); 5350ee52b15SSoren Brinkmann clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], 5360ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, 5370ee52b15SSoren Brinkmann &aperclk_lock); 5380ee52b15SSoren Brinkmann clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], 5390ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, 5400ee52b15SSoren Brinkmann &aperclk_lock); 5410ee52b15SSoren Brinkmann clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], 5420ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, 5430ee52b15SSoren Brinkmann &aperclk_lock); 5440ee52b15SSoren Brinkmann clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], 5450ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, 5460ee52b15SSoren Brinkmann &aperclk_lock); 5470ee52b15SSoren Brinkmann clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], 5480ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, 5490ee52b15SSoren Brinkmann &aperclk_lock); 5500ee52b15SSoren Brinkmann clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], 5510ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, 5520ee52b15SSoren Brinkmann &aperclk_lock); 5530ee52b15SSoren Brinkmann clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], 5540ee52b15SSoren Brinkmann clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, 5550ee52b15SSoren Brinkmann &aperclk_lock); 5560ee52b15SSoren Brinkmann 5570ee52b15SSoren Brinkmann for (i = 0; i < ARRAY_SIZE(clks); i++) { 5580ee52b15SSoren Brinkmann if (IS_ERR(clks[i])) { 5590ee52b15SSoren Brinkmann pr_err("Zynq clk %d: register failed with %ld\n", 5600ee52b15SSoren Brinkmann i, PTR_ERR(clks[i])); 5610ee52b15SSoren Brinkmann BUG(); 5620ee52b15SSoren Brinkmann } 5630ee52b15SSoren Brinkmann } 5640ee52b15SSoren Brinkmann 5650ee52b15SSoren Brinkmann clk_data.clks = clks; 5660ee52b15SSoren Brinkmann clk_data.clk_num = ARRAY_SIZE(clks); 5670ee52b15SSoren Brinkmann of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 5680ee52b15SSoren Brinkmann } 5690ee52b15SSoren Brinkmann 5700ee52b15SSoren Brinkmann CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); 5710ee52b15SSoren Brinkmann 5720ee52b15SSoren Brinkmann void __init zynq_clock_init(void __iomem *slcr_base) 5730ee52b15SSoren Brinkmann { 5740ee52b15SSoren Brinkmann zynq_slcr_base_priv = slcr_base; 5750ee52b15SSoren Brinkmann of_clk_init(NULL); 5760ee52b15SSoren Brinkmann } 577