1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx 'Clocking Wizard' driver 4 * 5 * Copyright (C) 2013 - 2021 Xilinx 6 * 7 * Sören Brinkmann <soren.brinkmann@xilinx.com> 8 * 9 */ 10 11 #include <linux/platform_device.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/slab.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/module.h> 18 #include <linux/err.h> 19 #include <linux/iopoll.h> 20 21 #define WZRD_NUM_OUTPUTS 7 22 #define WZRD_ACLK_MAX_FREQ 250000000UL 23 24 #define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n)) 25 26 #define WZRD_CLKOUT0_FRAC_EN BIT(18) 27 #define WZRD_CLKFBOUT_FRAC_EN BIT(26) 28 29 #define WZRD_CLKFBOUT_MULT_SHIFT 8 30 #define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT) 31 #define WZRD_CLKFBOUT_FRAC_SHIFT 16 32 #define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT) 33 #define WZRD_DIVCLK_DIVIDE_SHIFT 0 34 #define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) 35 #define WZRD_CLKOUT_DIVIDE_SHIFT 0 36 #define WZRD_CLKOUT_DIVIDE_WIDTH 8 37 #define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) 38 #define WZRD_CLKOUT_FRAC_SHIFT 8 39 #define WZRD_CLKOUT_FRAC_MASK 0x3ff 40 41 #define WZRD_DR_MAX_INT_DIV_VALUE 255 42 #define WZRD_DR_STATUS_REG_OFFSET 0x04 43 #define WZRD_DR_LOCK_BIT_MASK 0x00000001 44 #define WZRD_DR_INIT_REG_OFFSET 0x25C 45 #define WZRD_DR_DIV_TO_PHASE_OFFSET 4 46 #define WZRD_DR_BEGIN_DYNA_RECONF 0x03 47 #define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07 48 #define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02 49 50 #define WZRD_USEC_POLL 10 51 #define WZRD_TIMEOUT_POLL 1000 52 /* Get the mask from width */ 53 #define div_mask(width) ((1 << (width)) - 1) 54 55 /* Extract divider instance from clock hardware instance */ 56 #define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw) 57 58 enum clk_wzrd_int_clks { 59 wzrd_clk_mul, 60 wzrd_clk_mul_div, 61 wzrd_clk_mul_frac, 62 wzrd_clk_int_max 63 }; 64 65 /** 66 * struct clk_wzrd - Clock wizard private data structure 67 * 68 * @clk_data: Clock data 69 * @nb: Notifier block 70 * @base: Memory base 71 * @clk_in1: Handle to input clock 'clk_in1' 72 * @axi_clk: Handle to input clock 's_axi_aclk' 73 * @clks_internal: Internal clocks 74 * @clkout: Output clocks 75 * @speed_grade: Speed grade of the device 76 * @suspended: Flag indicating power state of the device 77 */ 78 struct clk_wzrd { 79 struct clk_onecell_data clk_data; 80 struct notifier_block nb; 81 void __iomem *base; 82 struct clk *clk_in1; 83 struct clk *axi_clk; 84 struct clk *clks_internal[wzrd_clk_int_max]; 85 struct clk *clkout[WZRD_NUM_OUTPUTS]; 86 unsigned int speed_grade; 87 bool suspended; 88 }; 89 90 /** 91 * struct clk_wzrd_divider - clock divider specific to clk_wzrd 92 * 93 * @hw: handle between common and hardware-specific interfaces 94 * @base: base address of register containing the divider 95 * @offset: offset address of register containing the divider 96 * @shift: shift to the divider bit field 97 * @width: width of the divider bit field 98 * @flags: clk_wzrd divider flags 99 * @table: array of value/divider pairs, last entry should have div = 0 100 * @lock: register lock 101 */ 102 struct clk_wzrd_divider { 103 struct clk_hw hw; 104 void __iomem *base; 105 u16 offset; 106 u8 shift; 107 u8 width; 108 u8 flags; 109 const struct clk_div_table *table; 110 spinlock_t *lock; /* divider lock */ 111 }; 112 113 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) 114 115 /* maximum frequencies for input/output clocks per speed grade */ 116 static const unsigned long clk_wzrd_max_freq[] = { 117 800000000UL, 118 933000000UL, 119 1066000000UL 120 }; 121 122 /* spin lock variable for clk_wzrd */ 123 static DEFINE_SPINLOCK(clkwzrd_lock); 124 125 static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw, 126 unsigned long parent_rate) 127 { 128 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 129 void __iomem *div_addr = divider->base + divider->offset; 130 unsigned int val; 131 132 val = readl(div_addr) >> divider->shift; 133 val &= div_mask(divider->width); 134 135 return divider_recalc_rate(hw, parent_rate, val, divider->table, 136 divider->flags, divider->width); 137 } 138 139 static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, 140 unsigned long parent_rate) 141 { 142 int err; 143 u32 value; 144 unsigned long flags = 0; 145 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 146 void __iomem *div_addr = divider->base + divider->offset; 147 148 if (divider->lock) 149 spin_lock_irqsave(divider->lock, flags); 150 else 151 __acquire(divider->lock); 152 153 value = DIV_ROUND_CLOSEST(parent_rate, rate); 154 155 /* Cap the value to max */ 156 min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); 157 158 /* Set divisor and clear phase offset */ 159 writel(value, div_addr); 160 writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); 161 162 /* Check status register */ 163 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, 164 value, value & WZRD_DR_LOCK_BIT_MASK, 165 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 166 if (err) 167 goto err_reconfig; 168 169 /* Initiate reconfiguration */ 170 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, 171 divider->base + WZRD_DR_INIT_REG_OFFSET); 172 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, 173 divider->base + WZRD_DR_INIT_REG_OFFSET); 174 175 /* Check status register */ 176 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, 177 value, value & WZRD_DR_LOCK_BIT_MASK, 178 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 179 err_reconfig: 180 if (divider->lock) 181 spin_unlock_irqrestore(divider->lock, flags); 182 else 183 __release(divider->lock); 184 return err; 185 } 186 187 static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate, 188 unsigned long *prate) 189 { 190 u8 div; 191 192 /* 193 * since we don't change parent rate we just round rate to closest 194 * achievable 195 */ 196 div = DIV_ROUND_CLOSEST(*prate, rate); 197 198 return *prate / div; 199 } 200 201 static const struct clk_ops clk_wzrd_clk_divider_ops = { 202 .round_rate = clk_wzrd_round_rate, 203 .set_rate = clk_wzrd_dynamic_reconfig, 204 .recalc_rate = clk_wzrd_recalc_rate, 205 }; 206 207 static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw, 208 unsigned long parent_rate) 209 { 210 unsigned int val; 211 u32 div, frac; 212 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 213 void __iomem *div_addr = divider->base + divider->offset; 214 215 val = readl(div_addr); 216 div = val & div_mask(divider->width); 217 frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK; 218 219 return mult_frac(parent_rate, 1000, (div * 1000) + frac); 220 } 221 222 static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, 223 unsigned long parent_rate) 224 { 225 int err; 226 u32 value, pre; 227 unsigned long rate_div, f, clockout0_div; 228 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 229 void __iomem *div_addr = divider->base + divider->offset; 230 231 rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate); 232 clockout0_div = rate_div / 1000; 233 234 pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); 235 f = (u32)(pre - (clockout0_div * 1000)); 236 f = f & WZRD_CLKOUT_FRAC_MASK; 237 f = f << WZRD_CLKOUT_DIVIDE_WIDTH; 238 239 value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK)); 240 241 /* Set divisor and clear phase offset */ 242 writel(value, div_addr); 243 writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); 244 245 /* Check status register */ 246 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, 247 value & WZRD_DR_LOCK_BIT_MASK, 248 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 249 if (err) 250 return err; 251 252 /* Initiate reconfiguration */ 253 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, 254 divider->base + WZRD_DR_INIT_REG_OFFSET); 255 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, 256 divider->base + WZRD_DR_INIT_REG_OFFSET); 257 258 /* Check status register */ 259 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, 260 value & WZRD_DR_LOCK_BIT_MASK, 261 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 262 } 263 264 static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate, 265 unsigned long *prate) 266 { 267 return rate; 268 } 269 270 static const struct clk_ops clk_wzrd_clk_divider_ops_f = { 271 .round_rate = clk_wzrd_round_rate_f, 272 .set_rate = clk_wzrd_dynamic_reconfig_f, 273 .recalc_rate = clk_wzrd_recalc_ratef, 274 }; 275 276 static struct clk *clk_wzrd_register_divf(struct device *dev, 277 const char *name, 278 const char *parent_name, 279 unsigned long flags, 280 void __iomem *base, u16 offset, 281 u8 shift, u8 width, 282 u8 clk_divider_flags, 283 const struct clk_div_table *table, 284 spinlock_t *lock) 285 { 286 struct clk_wzrd_divider *div; 287 struct clk_hw *hw; 288 struct clk_init_data init; 289 int ret; 290 291 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 292 if (!div) 293 return ERR_PTR(-ENOMEM); 294 295 init.name = name; 296 297 init.ops = &clk_wzrd_clk_divider_ops_f; 298 299 init.flags = flags; 300 init.parent_names = &parent_name; 301 init.num_parents = 1; 302 303 div->base = base; 304 div->offset = offset; 305 div->shift = shift; 306 div->width = width; 307 div->flags = clk_divider_flags; 308 div->lock = lock; 309 div->hw.init = &init; 310 div->table = table; 311 312 hw = &div->hw; 313 ret = devm_clk_hw_register(dev, hw); 314 if (ret) 315 return ERR_PTR(ret); 316 317 return hw->clk; 318 } 319 320 static struct clk *clk_wzrd_register_divider(struct device *dev, 321 const char *name, 322 const char *parent_name, 323 unsigned long flags, 324 void __iomem *base, u16 offset, 325 u8 shift, u8 width, 326 u8 clk_divider_flags, 327 const struct clk_div_table *table, 328 spinlock_t *lock) 329 { 330 struct clk_wzrd_divider *div; 331 struct clk_hw *hw; 332 struct clk_init_data init; 333 int ret; 334 335 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 336 if (!div) 337 return ERR_PTR(-ENOMEM); 338 339 init.name = name; 340 init.ops = &clk_wzrd_clk_divider_ops; 341 init.flags = flags; 342 init.parent_names = &parent_name; 343 init.num_parents = 1; 344 345 div->base = base; 346 div->offset = offset; 347 div->shift = shift; 348 div->width = width; 349 div->flags = clk_divider_flags; 350 div->lock = lock; 351 div->hw.init = &init; 352 div->table = table; 353 354 hw = &div->hw; 355 ret = devm_clk_hw_register(dev, hw); 356 if (ret) 357 hw = ERR_PTR(ret); 358 359 return hw->clk; 360 } 361 362 static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, 363 void *data) 364 { 365 unsigned long max; 366 struct clk_notifier_data *ndata = data; 367 struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb); 368 369 if (clk_wzrd->suspended) 370 return NOTIFY_OK; 371 372 if (ndata->clk == clk_wzrd->clk_in1) 373 max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; 374 else if (ndata->clk == clk_wzrd->axi_clk) 375 max = WZRD_ACLK_MAX_FREQ; 376 else 377 return NOTIFY_DONE; /* should never happen */ 378 379 switch (event) { 380 case PRE_RATE_CHANGE: 381 if (ndata->new_rate > max) 382 return NOTIFY_BAD; 383 return NOTIFY_OK; 384 case POST_RATE_CHANGE: 385 case ABORT_RATE_CHANGE: 386 default: 387 return NOTIFY_DONE; 388 } 389 } 390 391 static int __maybe_unused clk_wzrd_suspend(struct device *dev) 392 { 393 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); 394 395 clk_disable_unprepare(clk_wzrd->axi_clk); 396 clk_wzrd->suspended = true; 397 398 return 0; 399 } 400 401 static int __maybe_unused clk_wzrd_resume(struct device *dev) 402 { 403 int ret; 404 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); 405 406 ret = clk_prepare_enable(clk_wzrd->axi_clk); 407 if (ret) { 408 dev_err(dev, "unable to enable s_axi_aclk\n"); 409 return ret; 410 } 411 412 clk_wzrd->suspended = false; 413 414 return 0; 415 } 416 417 static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, 418 clk_wzrd_resume); 419 420 static int clk_wzrd_probe(struct platform_device *pdev) 421 { 422 int i, ret; 423 u32 reg, reg_f, mult; 424 unsigned long rate; 425 const char *clk_name; 426 void __iomem *ctrl_reg; 427 struct clk_wzrd *clk_wzrd; 428 struct device_node *np = pdev->dev.of_node; 429 int nr_outputs; 430 unsigned long flags = 0; 431 432 clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); 433 if (!clk_wzrd) 434 return -ENOMEM; 435 platform_set_drvdata(pdev, clk_wzrd); 436 437 clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0); 438 if (IS_ERR(clk_wzrd->base)) 439 return PTR_ERR(clk_wzrd->base); 440 441 ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); 442 if (!ret) { 443 if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { 444 dev_warn(&pdev->dev, "invalid speed grade '%d'\n", 445 clk_wzrd->speed_grade); 446 clk_wzrd->speed_grade = 0; 447 } 448 } 449 450 clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); 451 if (IS_ERR(clk_wzrd->clk_in1)) 452 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), 453 "clk_in1 not found\n"); 454 455 clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 456 if (IS_ERR(clk_wzrd->axi_clk)) 457 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), 458 "s_axi_aclk not found\n"); 459 ret = clk_prepare_enable(clk_wzrd->axi_clk); 460 if (ret) { 461 dev_err(&pdev->dev, "enabling s_axi_aclk failed\n"); 462 return ret; 463 } 464 rate = clk_get_rate(clk_wzrd->axi_clk); 465 if (rate > WZRD_ACLK_MAX_FREQ) { 466 dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", 467 rate); 468 ret = -EINVAL; 469 goto err_disable_clk; 470 } 471 472 reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)); 473 reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK; 474 reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT; 475 476 reg = reg & WZRD_CLKFBOUT_MULT_MASK; 477 reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT; 478 mult = (reg * 1000) + reg_f; 479 clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); 480 if (!clk_name) { 481 ret = -ENOMEM; 482 goto err_disable_clk; 483 } 484 485 ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); 486 if (ret || nr_outputs > WZRD_NUM_OUTPUTS) { 487 ret = -EINVAL; 488 goto err_disable_clk; 489 } 490 if (nr_outputs == 1) 491 flags = CLK_SET_RATE_PARENT; 492 493 clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor 494 (&pdev->dev, clk_name, 495 __clk_get_name(clk_wzrd->clk_in1), 496 0, mult, 1000); 497 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) { 498 dev_err(&pdev->dev, "unable to register fixed-factor clock\n"); 499 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]); 500 goto err_disable_clk; 501 } 502 503 clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); 504 if (!clk_name) { 505 ret = -ENOMEM; 506 goto err_rm_int_clk; 507 } 508 509 ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0); 510 /* register div */ 511 clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider 512 (&pdev->dev, clk_name, 513 __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), 514 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | 515 CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock); 516 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { 517 dev_err(&pdev->dev, "unable to register divider clock\n"); 518 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); 519 goto err_rm_int_clk; 520 } 521 522 /* register div per output */ 523 for (i = nr_outputs - 1; i >= 0 ; i--) { 524 const char *clkout_name; 525 526 clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i); 527 if (!clkout_name) { 528 ret = -ENOMEM; 529 goto err_rm_int_clk; 530 } 531 532 if (!i) 533 clk_wzrd->clkout[i] = clk_wzrd_register_divf 534 (&pdev->dev, clkout_name, 535 clk_name, flags, 536 clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), 537 WZRD_CLKOUT_DIVIDE_SHIFT, 538 WZRD_CLKOUT_DIVIDE_WIDTH, 539 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 540 NULL, &clkwzrd_lock); 541 else 542 clk_wzrd->clkout[i] = clk_wzrd_register_divider 543 (&pdev->dev, clkout_name, 544 clk_name, 0, 545 clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), 546 WZRD_CLKOUT_DIVIDE_SHIFT, 547 WZRD_CLKOUT_DIVIDE_WIDTH, 548 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 549 NULL, &clkwzrd_lock); 550 if (IS_ERR(clk_wzrd->clkout[i])) { 551 int j; 552 553 for (j = i + 1; j < nr_outputs; j++) 554 clk_unregister(clk_wzrd->clkout[j]); 555 dev_err(&pdev->dev, 556 "unable to register divider clock\n"); 557 ret = PTR_ERR(clk_wzrd->clkout[i]); 558 goto err_rm_int_clks; 559 } 560 } 561 562 kfree(clk_name); 563 564 clk_wzrd->clk_data.clks = clk_wzrd->clkout; 565 clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout); 566 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data); 567 568 if (clk_wzrd->speed_grade) { 569 clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; 570 571 ret = clk_notifier_register(clk_wzrd->clk_in1, 572 &clk_wzrd->nb); 573 if (ret) 574 dev_warn(&pdev->dev, 575 "unable to register clock notifier\n"); 576 577 ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb); 578 if (ret) 579 dev_warn(&pdev->dev, 580 "unable to register clock notifier\n"); 581 } 582 583 return 0; 584 585 err_rm_int_clks: 586 clk_unregister(clk_wzrd->clks_internal[1]); 587 err_rm_int_clk: 588 kfree(clk_name); 589 clk_unregister(clk_wzrd->clks_internal[0]); 590 err_disable_clk: 591 clk_disable_unprepare(clk_wzrd->axi_clk); 592 593 return ret; 594 } 595 596 static int clk_wzrd_remove(struct platform_device *pdev) 597 { 598 int i; 599 struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev); 600 601 of_clk_del_provider(pdev->dev.of_node); 602 603 for (i = 0; i < WZRD_NUM_OUTPUTS; i++) 604 clk_unregister(clk_wzrd->clkout[i]); 605 for (i = 0; i < wzrd_clk_int_max; i++) 606 clk_unregister(clk_wzrd->clks_internal[i]); 607 608 if (clk_wzrd->speed_grade) { 609 clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb); 610 clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb); 611 } 612 613 clk_disable_unprepare(clk_wzrd->axi_clk); 614 615 return 0; 616 } 617 618 static const struct of_device_id clk_wzrd_ids[] = { 619 { .compatible = "xlnx,clocking-wizard" }, 620 { .compatible = "xlnx,clocking-wizard-v5.2" }, 621 { .compatible = "xlnx,clocking-wizard-v6.0" }, 622 { }, 623 }; 624 MODULE_DEVICE_TABLE(of, clk_wzrd_ids); 625 626 static struct platform_driver clk_wzrd_driver = { 627 .driver = { 628 .name = "clk-wizard", 629 .of_match_table = clk_wzrd_ids, 630 .pm = &clk_wzrd_dev_pm_ops, 631 }, 632 .probe = clk_wzrd_probe, 633 .remove = clk_wzrd_remove, 634 }; 635 module_platform_driver(clk_wzrd_driver); 636 637 MODULE_LICENSE("GPL"); 638 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com"); 639 MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core"); 640