1# SPDX-License-Identifier: GPL-2.0 2 3config XILINX_VCU 4 tristate "Xilinx VCU logicoreIP Init" 5 depends on HAS_IOMEM && COMMON_CLK 6 select REGMAP_MMIO 7 help 8 Provides the driver to enable and disable the isolation between the 9 processing system and programmable logic part by using the logicoreIP 10 register set. This driver also configures the frequency based on the 11 clock information from the logicoreIP register set. 12 13 If you say yes here you get support for the logicoreIP. 14 15 If unsure, say N. 16 17 To compile this driver as a module, choose M here: the 18 module will be called xlnx_vcu. 19 20config COMMON_CLK_XLNX_CLKWZRD 21 tristate "Xilinx Clocking Wizard" 22 depends on COMMON_CLK && OF 23 depends on HAS_IOMEM 24 help 25 Support for the Xilinx Clocking Wizard IP core clock generator. 26 Adds support for clocking wizard and compatible. 27 This driver supports the Xilinx clocking wizard programmable clock 28 synthesizer. The number of output is configurable in the design. 29 30 If unsure, say N. 31 32