170ee6577SLinus Walleij /* 270ee6577SLinus Walleij * Clock driver for the ARM Integrator/IM-PD1 board 38e048b99SLinus Walleij * Copyright (C) 2012-2013 Linus Walleij 470ee6577SLinus Walleij * 570ee6577SLinus Walleij * This program is free software; you can redistribute it and/or modify 670ee6577SLinus Walleij * it under the terms of the GNU General Public License version 2 as 770ee6577SLinus Walleij * published by the Free Software Foundation. 870ee6577SLinus Walleij */ 970ee6577SLinus Walleij #include <linux/clk-provider.h> 1070ee6577SLinus Walleij #include <linux/clk.h> 1170ee6577SLinus Walleij #include <linux/clkdev.h> 1270ee6577SLinus Walleij #include <linux/err.h> 1370ee6577SLinus Walleij #include <linux/io.h> 1470ee6577SLinus Walleij #include <linux/platform_data/clk-integrator.h> 1570ee6577SLinus Walleij 1670ee6577SLinus Walleij #include <mach/impd1.h> 1770ee6577SLinus Walleij 1870ee6577SLinus Walleij #include "clk-icst.h" 1970ee6577SLinus Walleij 2070ee6577SLinus Walleij struct impd1_clk { 218e048b99SLinus Walleij char *vco1name; 228e048b99SLinus Walleij struct clk *vco1clk; 238e048b99SLinus Walleij char *vco2name; 248e048b99SLinus Walleij struct clk *vco2clk; 258e048b99SLinus Walleij struct clk *mmciclk; 268e048b99SLinus Walleij char *uartname; 2770ee6577SLinus Walleij struct clk *uartclk; 288e048b99SLinus Walleij char *spiname; 298e048b99SLinus Walleij struct clk *spiclk; 308e048b99SLinus Walleij char *scname; 318e048b99SLinus Walleij struct clk *scclk; 328e048b99SLinus Walleij struct clk_lookup *clks[6]; 3370ee6577SLinus Walleij }; 3470ee6577SLinus Walleij 358e048b99SLinus Walleij /* One entry for each connected IM-PD1 LM */ 3670ee6577SLinus Walleij static struct impd1_clk impd1_clks[4]; 3770ee6577SLinus Walleij 3870ee6577SLinus Walleij /* 398e048b99SLinus Walleij * There are two VCO's on the IM-PD1 4070ee6577SLinus Walleij */ 4170ee6577SLinus Walleij 428e048b99SLinus Walleij static const struct icst_params impd1_vco1_params = { 4370ee6577SLinus Walleij .ref = 24000000, /* 24 MHz */ 4470ee6577SLinus Walleij .vco_max = ICST525_VCO_MAX_3V, 4570ee6577SLinus Walleij .vco_min = ICST525_VCO_MIN, 4670ee6577SLinus Walleij .vd_min = 12, 4770ee6577SLinus Walleij .vd_max = 519, 4870ee6577SLinus Walleij .rd_min = 3, 4970ee6577SLinus Walleij .rd_max = 120, 5070ee6577SLinus Walleij .s2div = icst525_s2div, 5170ee6577SLinus Walleij .idx2s = icst525_idx2s, 5270ee6577SLinus Walleij }; 5370ee6577SLinus Walleij 5470ee6577SLinus Walleij static const struct clk_icst_desc impd1_icst1_desc = { 558e048b99SLinus Walleij .params = &impd1_vco1_params, 5670ee6577SLinus Walleij .vco_offset = IMPD1_OSC1, 5770ee6577SLinus Walleij .lock_offset = IMPD1_LOCK, 5870ee6577SLinus Walleij }; 5970ee6577SLinus Walleij 608e048b99SLinus Walleij static const struct icst_params impd1_vco2_params = { 618e048b99SLinus Walleij .ref = 24000000, /* 24 MHz */ 628e048b99SLinus Walleij .vco_max = ICST525_VCO_MAX_3V, 638e048b99SLinus Walleij .vco_min = ICST525_VCO_MIN, 648e048b99SLinus Walleij .vd_min = 12, 658e048b99SLinus Walleij .vd_max = 519, 668e048b99SLinus Walleij .rd_min = 3, 678e048b99SLinus Walleij .rd_max = 120, 688e048b99SLinus Walleij .s2div = icst525_s2div, 698e048b99SLinus Walleij .idx2s = icst525_idx2s, 708e048b99SLinus Walleij }; 718e048b99SLinus Walleij 728e048b99SLinus Walleij static const struct clk_icst_desc impd1_icst2_desc = { 738e048b99SLinus Walleij .params = &impd1_vco2_params, 748e048b99SLinus Walleij .vco_offset = IMPD1_OSC2, 758e048b99SLinus Walleij .lock_offset = IMPD1_LOCK, 768e048b99SLinus Walleij }; 778e048b99SLinus Walleij 7870ee6577SLinus Walleij /** 7970ee6577SLinus Walleij * integrator_impd1_clk_init() - set up the integrator clock tree 8070ee6577SLinus Walleij * @base: base address of the logic module (LM) 8170ee6577SLinus Walleij * @id: the ID of this LM 8270ee6577SLinus Walleij */ 8370ee6577SLinus Walleij void integrator_impd1_clk_init(void __iomem *base, unsigned int id) 8470ee6577SLinus Walleij { 8570ee6577SLinus Walleij struct impd1_clk *imc; 8670ee6577SLinus Walleij struct clk *clk; 8770ee6577SLinus Walleij int i; 8870ee6577SLinus Walleij 8970ee6577SLinus Walleij if (id > 3) { 9070ee6577SLinus Walleij pr_crit("no more than 4 LMs can be attached\n"); 9170ee6577SLinus Walleij return; 9270ee6577SLinus Walleij } 9370ee6577SLinus Walleij imc = &impd1_clks[id]; 9470ee6577SLinus Walleij 958e048b99SLinus Walleij imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id); 96bf6edb4bSLinus Walleij clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, 97bf6edb4bSLinus Walleij base); 98ae6e694eSLinus Walleij imc->vco1clk = clk; 9970ee6577SLinus Walleij imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id); 10070ee6577SLinus Walleij 1018e048b99SLinus Walleij /* VCO2 is also called "CLK2" */ 1028e048b99SLinus Walleij imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id); 103bf6edb4bSLinus Walleij clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, NULL, 104bf6edb4bSLinus Walleij base); 1058e048b99SLinus Walleij imc->vco2clk = clk; 1068e048b99SLinus Walleij 1078e048b99SLinus Walleij /* MMCI uses CLK2 right off */ 1088e048b99SLinus Walleij imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00700", id); 1098e048b99SLinus Walleij 1108e048b99SLinus Walleij /* UART reference clock divides CLK2 by a fixed factor 4 */ 1118e048b99SLinus Walleij imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id); 1128e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name, 1138e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 4); 11470ee6577SLinus Walleij imc->uartclk = clk; 1158e048b99SLinus Walleij imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00100", id); 1168e048b99SLinus Walleij imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00200", id); 1178e048b99SLinus Walleij 1188e048b99SLinus Walleij /* SPI PL022 clock divides CLK2 by a fixed factor 64 */ 1198e048b99SLinus Walleij imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id); 1208e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name, 1218e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 64); 1228e048b99SLinus Walleij imc->clks[4] = clkdev_alloc(clk, NULL, "lm%x:00300", id); 1238e048b99SLinus Walleij 1248e048b99SLinus Walleij /* Smart Card clock divides CLK2 by a fixed factor 4 */ 1258e048b99SLinus Walleij imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id); 1268e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name, 1278e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 4); 1288e048b99SLinus Walleij imc->scclk = clk; 1298e048b99SLinus Walleij imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00600", id); 13070ee6577SLinus Walleij 13170ee6577SLinus Walleij for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 13270ee6577SLinus Walleij clkdev_add(imc->clks[i]); 13370ee6577SLinus Walleij } 13470ee6577SLinus Walleij 13570ee6577SLinus Walleij void integrator_impd1_clk_exit(unsigned int id) 13670ee6577SLinus Walleij { 13770ee6577SLinus Walleij int i; 13870ee6577SLinus Walleij struct impd1_clk *imc; 13970ee6577SLinus Walleij 14070ee6577SLinus Walleij if (id > 3) 14170ee6577SLinus Walleij return; 14270ee6577SLinus Walleij imc = &impd1_clks[id]; 14370ee6577SLinus Walleij 14470ee6577SLinus Walleij for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 14570ee6577SLinus Walleij clkdev_drop(imc->clks[i]); 1468e048b99SLinus Walleij clk_unregister(imc->spiclk); 14770ee6577SLinus Walleij clk_unregister(imc->uartclk); 1488e048b99SLinus Walleij clk_unregister(imc->vco2clk); 1498e048b99SLinus Walleij clk_unregister(imc->vco1clk); 1508e048b99SLinus Walleij kfree(imc->scname); 1518e048b99SLinus Walleij kfree(imc->spiname); 1528e048b99SLinus Walleij kfree(imc->uartname); 1538e048b99SLinus Walleij kfree(imc->vco2name); 1548e048b99SLinus Walleij kfree(imc->vco1name); 15570ee6577SLinus Walleij } 156