170ee6577SLinus Walleij /* 270ee6577SLinus Walleij * Clock driver for the ARM Integrator/IM-PD1 board 38e048b99SLinus Walleij * Copyright (C) 2012-2013 Linus Walleij 470ee6577SLinus Walleij * 570ee6577SLinus Walleij * This program is free software; you can redistribute it and/or modify 670ee6577SLinus Walleij * it under the terms of the GNU General Public License version 2 as 770ee6577SLinus Walleij * published by the Free Software Foundation. 870ee6577SLinus Walleij */ 970ee6577SLinus Walleij #include <linux/clk-provider.h> 1070ee6577SLinus Walleij #include <linux/clkdev.h> 1170ee6577SLinus Walleij #include <linux/err.h> 1270ee6577SLinus Walleij #include <linux/io.h> 1370ee6577SLinus Walleij #include <linux/platform_data/clk-integrator.h> 1470ee6577SLinus Walleij 1570ee6577SLinus Walleij #include "clk-icst.h" 1670ee6577SLinus Walleij 17cc0cc4caSLinus Walleij #define IMPD1_OSC1 0x00 18cc0cc4caSLinus Walleij #define IMPD1_OSC2 0x04 19cc0cc4caSLinus Walleij #define IMPD1_LOCK 0x08 20cc0cc4caSLinus Walleij 2170ee6577SLinus Walleij struct impd1_clk { 22222cb1bfSLinus Walleij char *pclkname; 23222cb1bfSLinus Walleij struct clk *pclk; 248e048b99SLinus Walleij char *vco1name; 258e048b99SLinus Walleij struct clk *vco1clk; 268e048b99SLinus Walleij char *vco2name; 278e048b99SLinus Walleij struct clk *vco2clk; 288e048b99SLinus Walleij struct clk *mmciclk; 298e048b99SLinus Walleij char *uartname; 3070ee6577SLinus Walleij struct clk *uartclk; 318e048b99SLinus Walleij char *spiname; 328e048b99SLinus Walleij struct clk *spiclk; 338e048b99SLinus Walleij char *scname; 348e048b99SLinus Walleij struct clk *scclk; 35222cb1bfSLinus Walleij struct clk_lookup *clks[15]; 3670ee6577SLinus Walleij }; 3770ee6577SLinus Walleij 388e048b99SLinus Walleij /* One entry for each connected IM-PD1 LM */ 3970ee6577SLinus Walleij static struct impd1_clk impd1_clks[4]; 4070ee6577SLinus Walleij 4170ee6577SLinus Walleij /* 428e048b99SLinus Walleij * There are two VCO's on the IM-PD1 4370ee6577SLinus Walleij */ 4470ee6577SLinus Walleij 458e048b99SLinus Walleij static const struct icst_params impd1_vco1_params = { 4670ee6577SLinus Walleij .ref = 24000000, /* 24 MHz */ 4770ee6577SLinus Walleij .vco_max = ICST525_VCO_MAX_3V, 4870ee6577SLinus Walleij .vco_min = ICST525_VCO_MIN, 4970ee6577SLinus Walleij .vd_min = 12, 5070ee6577SLinus Walleij .vd_max = 519, 5170ee6577SLinus Walleij .rd_min = 3, 5270ee6577SLinus Walleij .rd_max = 120, 5370ee6577SLinus Walleij .s2div = icst525_s2div, 5470ee6577SLinus Walleij .idx2s = icst525_idx2s, 5570ee6577SLinus Walleij }; 5670ee6577SLinus Walleij 5770ee6577SLinus Walleij static const struct clk_icst_desc impd1_icst1_desc = { 588e048b99SLinus Walleij .params = &impd1_vco1_params, 5970ee6577SLinus Walleij .vco_offset = IMPD1_OSC1, 6070ee6577SLinus Walleij .lock_offset = IMPD1_LOCK, 6170ee6577SLinus Walleij }; 6270ee6577SLinus Walleij 638e048b99SLinus Walleij static const struct icst_params impd1_vco2_params = { 648e048b99SLinus Walleij .ref = 24000000, /* 24 MHz */ 658e048b99SLinus Walleij .vco_max = ICST525_VCO_MAX_3V, 668e048b99SLinus Walleij .vco_min = ICST525_VCO_MIN, 678e048b99SLinus Walleij .vd_min = 12, 688e048b99SLinus Walleij .vd_max = 519, 698e048b99SLinus Walleij .rd_min = 3, 708e048b99SLinus Walleij .rd_max = 120, 718e048b99SLinus Walleij .s2div = icst525_s2div, 728e048b99SLinus Walleij .idx2s = icst525_idx2s, 738e048b99SLinus Walleij }; 748e048b99SLinus Walleij 758e048b99SLinus Walleij static const struct clk_icst_desc impd1_icst2_desc = { 768e048b99SLinus Walleij .params = &impd1_vco2_params, 778e048b99SLinus Walleij .vco_offset = IMPD1_OSC2, 788e048b99SLinus Walleij .lock_offset = IMPD1_LOCK, 798e048b99SLinus Walleij }; 808e048b99SLinus Walleij 8170ee6577SLinus Walleij /** 8270ee6577SLinus Walleij * integrator_impd1_clk_init() - set up the integrator clock tree 8370ee6577SLinus Walleij * @base: base address of the logic module (LM) 8470ee6577SLinus Walleij * @id: the ID of this LM 8570ee6577SLinus Walleij */ 8670ee6577SLinus Walleij void integrator_impd1_clk_init(void __iomem *base, unsigned int id) 8770ee6577SLinus Walleij { 8870ee6577SLinus Walleij struct impd1_clk *imc; 8970ee6577SLinus Walleij struct clk *clk; 90222cb1bfSLinus Walleij struct clk *pclk; 9170ee6577SLinus Walleij int i; 9270ee6577SLinus Walleij 9370ee6577SLinus Walleij if (id > 3) { 9470ee6577SLinus Walleij pr_crit("no more than 4 LMs can be attached\n"); 9570ee6577SLinus Walleij return; 9670ee6577SLinus Walleij } 9770ee6577SLinus Walleij imc = &impd1_clks[id]; 9870ee6577SLinus Walleij 99222cb1bfSLinus Walleij /* Register the fixed rate PCLK */ 100222cb1bfSLinus Walleij imc->pclkname = kasprintf(GFP_KERNEL, "lm%x-pclk", id); 101ac82a8b5SStephen Boyd pclk = clk_register_fixed_rate(NULL, imc->pclkname, NULL, 0, 0); 102222cb1bfSLinus Walleij imc->pclk = pclk; 103222cb1bfSLinus Walleij 1048e048b99SLinus Walleij imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id); 105bf6edb4bSLinus Walleij clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, 106bf6edb4bSLinus Walleij base); 107ae6e694eSLinus Walleij imc->vco1clk = clk; 108222cb1bfSLinus Walleij imc->clks[0] = clkdev_alloc(pclk, "apb_pclk", "lm%x:01000", id); 109222cb1bfSLinus Walleij imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id); 11070ee6577SLinus Walleij 1118e048b99SLinus Walleij /* VCO2 is also called "CLK2" */ 1128e048b99SLinus Walleij imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id); 113bf6edb4bSLinus Walleij clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, NULL, 114bf6edb4bSLinus Walleij base); 1158e048b99SLinus Walleij imc->vco2clk = clk; 1168e048b99SLinus Walleij 1178e048b99SLinus Walleij /* MMCI uses CLK2 right off */ 118222cb1bfSLinus Walleij imc->clks[2] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00700", id); 119222cb1bfSLinus Walleij imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id); 1208e048b99SLinus Walleij 1218e048b99SLinus Walleij /* UART reference clock divides CLK2 by a fixed factor 4 */ 1228e048b99SLinus Walleij imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id); 1238e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name, 1248e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 4); 12570ee6577SLinus Walleij imc->uartclk = clk; 126222cb1bfSLinus Walleij imc->clks[4] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00100", id); 127222cb1bfSLinus Walleij imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id); 128222cb1bfSLinus Walleij imc->clks[6] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00200", id); 129222cb1bfSLinus Walleij imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id); 1308e048b99SLinus Walleij 1318e048b99SLinus Walleij /* SPI PL022 clock divides CLK2 by a fixed factor 64 */ 1328e048b99SLinus Walleij imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id); 1338e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name, 1348e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 64); 135222cb1bfSLinus Walleij imc->clks[8] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00300", id); 136222cb1bfSLinus Walleij imc->clks[9] = clkdev_alloc(clk, NULL, "lm%x:00300", id); 137222cb1bfSLinus Walleij 138222cb1bfSLinus Walleij /* The GPIO blocks and AACI have only PCLK */ 139222cb1bfSLinus Walleij imc->clks[10] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00400", id); 140222cb1bfSLinus Walleij imc->clks[11] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00500", id); 141222cb1bfSLinus Walleij imc->clks[12] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00800", id); 1428e048b99SLinus Walleij 1438e048b99SLinus Walleij /* Smart Card clock divides CLK2 by a fixed factor 4 */ 1448e048b99SLinus Walleij imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id); 1458e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name, 1468e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 4); 1478e048b99SLinus Walleij imc->scclk = clk; 148222cb1bfSLinus Walleij imc->clks[13] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00600", id); 149222cb1bfSLinus Walleij imc->clks[14] = clkdev_alloc(clk, NULL, "lm%x:00600", id); 15070ee6577SLinus Walleij 15170ee6577SLinus Walleij for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 15270ee6577SLinus Walleij clkdev_add(imc->clks[i]); 15370ee6577SLinus Walleij } 154a218d7faSArnd Bergmann EXPORT_SYMBOL_GPL(integrator_impd1_clk_init); 15570ee6577SLinus Walleij 15670ee6577SLinus Walleij void integrator_impd1_clk_exit(unsigned int id) 15770ee6577SLinus Walleij { 15870ee6577SLinus Walleij int i; 15970ee6577SLinus Walleij struct impd1_clk *imc; 16070ee6577SLinus Walleij 16170ee6577SLinus Walleij if (id > 3) 16270ee6577SLinus Walleij return; 16370ee6577SLinus Walleij imc = &impd1_clks[id]; 16470ee6577SLinus Walleij 16570ee6577SLinus Walleij for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 16670ee6577SLinus Walleij clkdev_drop(imc->clks[i]); 1678e048b99SLinus Walleij clk_unregister(imc->spiclk); 16870ee6577SLinus Walleij clk_unregister(imc->uartclk); 1698e048b99SLinus Walleij clk_unregister(imc->vco2clk); 1708e048b99SLinus Walleij clk_unregister(imc->vco1clk); 171222cb1bfSLinus Walleij clk_unregister(imc->pclk); 1728e048b99SLinus Walleij kfree(imc->scname); 1738e048b99SLinus Walleij kfree(imc->spiname); 1748e048b99SLinus Walleij kfree(imc->uartname); 1758e048b99SLinus Walleij kfree(imc->vco2name); 1768e048b99SLinus Walleij kfree(imc->vco1name); 177222cb1bfSLinus Walleij kfree(imc->pclkname); 17870ee6577SLinus Walleij } 179a218d7faSArnd Bergmann EXPORT_SYMBOL_GPL(integrator_impd1_clk_exit); 180