170ee6577SLinus Walleij /* 270ee6577SLinus Walleij * Clock driver for the ARM Integrator/IM-PD1 board 38e048b99SLinus Walleij * Copyright (C) 2012-2013 Linus Walleij 470ee6577SLinus Walleij * 570ee6577SLinus Walleij * This program is free software; you can redistribute it and/or modify 670ee6577SLinus Walleij * it under the terms of the GNU General Public License version 2 as 770ee6577SLinus Walleij * published by the Free Software Foundation. 870ee6577SLinus Walleij */ 970ee6577SLinus Walleij #include <linux/clk-provider.h> 1070ee6577SLinus Walleij #include <linux/clk.h> 1170ee6577SLinus Walleij #include <linux/clkdev.h> 1270ee6577SLinus Walleij #include <linux/err.h> 1370ee6577SLinus Walleij #include <linux/io.h> 1470ee6577SLinus Walleij #include <linux/platform_data/clk-integrator.h> 1570ee6577SLinus Walleij 1670ee6577SLinus Walleij #include "clk-icst.h" 1770ee6577SLinus Walleij 18cc0cc4caSLinus Walleij #define IMPD1_OSC1 0x00 19cc0cc4caSLinus Walleij #define IMPD1_OSC2 0x04 20cc0cc4caSLinus Walleij #define IMPD1_LOCK 0x08 21cc0cc4caSLinus Walleij 2270ee6577SLinus Walleij struct impd1_clk { 238e048b99SLinus Walleij char *vco1name; 248e048b99SLinus Walleij struct clk *vco1clk; 258e048b99SLinus Walleij char *vco2name; 268e048b99SLinus Walleij struct clk *vco2clk; 278e048b99SLinus Walleij struct clk *mmciclk; 288e048b99SLinus Walleij char *uartname; 2970ee6577SLinus Walleij struct clk *uartclk; 308e048b99SLinus Walleij char *spiname; 318e048b99SLinus Walleij struct clk *spiclk; 328e048b99SLinus Walleij char *scname; 338e048b99SLinus Walleij struct clk *scclk; 348e048b99SLinus Walleij struct clk_lookup *clks[6]; 3570ee6577SLinus Walleij }; 3670ee6577SLinus Walleij 378e048b99SLinus Walleij /* One entry for each connected IM-PD1 LM */ 3870ee6577SLinus Walleij static struct impd1_clk impd1_clks[4]; 3970ee6577SLinus Walleij 4070ee6577SLinus Walleij /* 418e048b99SLinus Walleij * There are two VCO's on the IM-PD1 4270ee6577SLinus Walleij */ 4370ee6577SLinus Walleij 448e048b99SLinus Walleij static const struct icst_params impd1_vco1_params = { 4570ee6577SLinus Walleij .ref = 24000000, /* 24 MHz */ 4670ee6577SLinus Walleij .vco_max = ICST525_VCO_MAX_3V, 4770ee6577SLinus Walleij .vco_min = ICST525_VCO_MIN, 4870ee6577SLinus Walleij .vd_min = 12, 4970ee6577SLinus Walleij .vd_max = 519, 5070ee6577SLinus Walleij .rd_min = 3, 5170ee6577SLinus Walleij .rd_max = 120, 5270ee6577SLinus Walleij .s2div = icst525_s2div, 5370ee6577SLinus Walleij .idx2s = icst525_idx2s, 5470ee6577SLinus Walleij }; 5570ee6577SLinus Walleij 5670ee6577SLinus Walleij static const struct clk_icst_desc impd1_icst1_desc = { 578e048b99SLinus Walleij .params = &impd1_vco1_params, 5870ee6577SLinus Walleij .vco_offset = IMPD1_OSC1, 5970ee6577SLinus Walleij .lock_offset = IMPD1_LOCK, 6070ee6577SLinus Walleij }; 6170ee6577SLinus Walleij 628e048b99SLinus Walleij static const struct icst_params impd1_vco2_params = { 638e048b99SLinus Walleij .ref = 24000000, /* 24 MHz */ 648e048b99SLinus Walleij .vco_max = ICST525_VCO_MAX_3V, 658e048b99SLinus Walleij .vco_min = ICST525_VCO_MIN, 668e048b99SLinus Walleij .vd_min = 12, 678e048b99SLinus Walleij .vd_max = 519, 688e048b99SLinus Walleij .rd_min = 3, 698e048b99SLinus Walleij .rd_max = 120, 708e048b99SLinus Walleij .s2div = icst525_s2div, 718e048b99SLinus Walleij .idx2s = icst525_idx2s, 728e048b99SLinus Walleij }; 738e048b99SLinus Walleij 748e048b99SLinus Walleij static const struct clk_icst_desc impd1_icst2_desc = { 758e048b99SLinus Walleij .params = &impd1_vco2_params, 768e048b99SLinus Walleij .vco_offset = IMPD1_OSC2, 778e048b99SLinus Walleij .lock_offset = IMPD1_LOCK, 788e048b99SLinus Walleij }; 798e048b99SLinus Walleij 8070ee6577SLinus Walleij /** 8170ee6577SLinus Walleij * integrator_impd1_clk_init() - set up the integrator clock tree 8270ee6577SLinus Walleij * @base: base address of the logic module (LM) 8370ee6577SLinus Walleij * @id: the ID of this LM 8470ee6577SLinus Walleij */ 8570ee6577SLinus Walleij void integrator_impd1_clk_init(void __iomem *base, unsigned int id) 8670ee6577SLinus Walleij { 8770ee6577SLinus Walleij struct impd1_clk *imc; 8870ee6577SLinus Walleij struct clk *clk; 8970ee6577SLinus Walleij int i; 9070ee6577SLinus Walleij 9170ee6577SLinus Walleij if (id > 3) { 9270ee6577SLinus Walleij pr_crit("no more than 4 LMs can be attached\n"); 9370ee6577SLinus Walleij return; 9470ee6577SLinus Walleij } 9570ee6577SLinus Walleij imc = &impd1_clks[id]; 9670ee6577SLinus Walleij 978e048b99SLinus Walleij imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id); 98bf6edb4bSLinus Walleij clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, 99bf6edb4bSLinus Walleij base); 100ae6e694eSLinus Walleij imc->vco1clk = clk; 10170ee6577SLinus Walleij imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id); 10270ee6577SLinus Walleij 1038e048b99SLinus Walleij /* VCO2 is also called "CLK2" */ 1048e048b99SLinus Walleij imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id); 105bf6edb4bSLinus Walleij clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, NULL, 106bf6edb4bSLinus Walleij base); 1078e048b99SLinus Walleij imc->vco2clk = clk; 1088e048b99SLinus Walleij 1098e048b99SLinus Walleij /* MMCI uses CLK2 right off */ 1108e048b99SLinus Walleij imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00700", id); 1118e048b99SLinus Walleij 1128e048b99SLinus Walleij /* UART reference clock divides CLK2 by a fixed factor 4 */ 1138e048b99SLinus Walleij imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id); 1148e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name, 1158e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 4); 11670ee6577SLinus Walleij imc->uartclk = clk; 1178e048b99SLinus Walleij imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00100", id); 1188e048b99SLinus Walleij imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00200", id); 1198e048b99SLinus Walleij 1208e048b99SLinus Walleij /* SPI PL022 clock divides CLK2 by a fixed factor 64 */ 1218e048b99SLinus Walleij imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id); 1228e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name, 1238e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 64); 1248e048b99SLinus Walleij imc->clks[4] = clkdev_alloc(clk, NULL, "lm%x:00300", id); 1258e048b99SLinus Walleij 1268e048b99SLinus Walleij /* Smart Card clock divides CLK2 by a fixed factor 4 */ 1278e048b99SLinus Walleij imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id); 1288e048b99SLinus Walleij clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name, 1298e048b99SLinus Walleij CLK_IGNORE_UNUSED, 1, 4); 1308e048b99SLinus Walleij imc->scclk = clk; 1318e048b99SLinus Walleij imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00600", id); 13270ee6577SLinus Walleij 13370ee6577SLinus Walleij for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 13470ee6577SLinus Walleij clkdev_add(imc->clks[i]); 13570ee6577SLinus Walleij } 136a218d7faSArnd Bergmann EXPORT_SYMBOL_GPL(integrator_impd1_clk_init); 13770ee6577SLinus Walleij 13870ee6577SLinus Walleij void integrator_impd1_clk_exit(unsigned int id) 13970ee6577SLinus Walleij { 14070ee6577SLinus Walleij int i; 14170ee6577SLinus Walleij struct impd1_clk *imc; 14270ee6577SLinus Walleij 14370ee6577SLinus Walleij if (id > 3) 14470ee6577SLinus Walleij return; 14570ee6577SLinus Walleij imc = &impd1_clks[id]; 14670ee6577SLinus Walleij 14770ee6577SLinus Walleij for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 14870ee6577SLinus Walleij clkdev_drop(imc->clks[i]); 1498e048b99SLinus Walleij clk_unregister(imc->spiclk); 15070ee6577SLinus Walleij clk_unregister(imc->uartclk); 1518e048b99SLinus Walleij clk_unregister(imc->vco2clk); 1528e048b99SLinus Walleij clk_unregister(imc->vco1clk); 1538e048b99SLinus Walleij kfree(imc->scname); 1548e048b99SLinus Walleij kfree(imc->spiname); 1558e048b99SLinus Walleij kfree(imc->uartname); 1568e048b99SLinus Walleij kfree(imc->vco2name); 1578e048b99SLinus Walleij kfree(imc->vco1name); 15870ee6577SLinus Walleij } 159a218d7faSArnd Bergmann EXPORT_SYMBOL_GPL(integrator_impd1_clk_exit); 160