1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
270ee6577SLinus Walleij /*
370ee6577SLinus Walleij  * Clock driver for the ARM Integrator/IM-PD1 board
48e048b99SLinus Walleij  * Copyright (C) 2012-2013 Linus Walleij
570ee6577SLinus Walleij  */
670ee6577SLinus Walleij #include <linux/clk-provider.h>
770ee6577SLinus Walleij #include <linux/clkdev.h>
870ee6577SLinus Walleij #include <linux/err.h>
970ee6577SLinus Walleij #include <linux/io.h>
1084655b76SLinus Walleij #include <linux/platform_device.h>
1170ee6577SLinus Walleij #include <linux/platform_data/clk-integrator.h>
1284655b76SLinus Walleij #include <linux/module.h>
1384655b76SLinus Walleij #include <linux/mfd/syscon.h>
1484655b76SLinus Walleij #include <linux/regmap.h>
1570ee6577SLinus Walleij 
16ba3fae06SLinus Walleij #include "icst.h"
1770ee6577SLinus Walleij #include "clk-icst.h"
1870ee6577SLinus Walleij 
19cc0cc4caSLinus Walleij #define IMPD1_OSC1	0x00
20cc0cc4caSLinus Walleij #define IMPD1_OSC2	0x04
21cc0cc4caSLinus Walleij #define IMPD1_LOCK	0x08
22cc0cc4caSLinus Walleij 
2370ee6577SLinus Walleij struct impd1_clk {
24222cb1bfSLinus Walleij 	char *pclkname;
25222cb1bfSLinus Walleij 	struct clk *pclk;
268e048b99SLinus Walleij 	char *vco1name;
278e048b99SLinus Walleij 	struct clk *vco1clk;
288e048b99SLinus Walleij 	char *vco2name;
298e048b99SLinus Walleij 	struct clk *vco2clk;
308e048b99SLinus Walleij 	struct clk *mmciclk;
318e048b99SLinus Walleij 	char *uartname;
3270ee6577SLinus Walleij 	struct clk *uartclk;
338e048b99SLinus Walleij 	char *spiname;
348e048b99SLinus Walleij 	struct clk *spiclk;
358e048b99SLinus Walleij 	char *scname;
368e048b99SLinus Walleij 	struct clk *scclk;
37222cb1bfSLinus Walleij 	struct clk_lookup *clks[15];
3870ee6577SLinus Walleij };
3970ee6577SLinus Walleij 
408e048b99SLinus Walleij /* One entry for each connected IM-PD1 LM */
4170ee6577SLinus Walleij static struct impd1_clk impd1_clks[4];
4270ee6577SLinus Walleij 
4370ee6577SLinus Walleij /*
448e048b99SLinus Walleij  * There are two VCO's on the IM-PD1
4570ee6577SLinus Walleij  */
4670ee6577SLinus Walleij 
478e048b99SLinus Walleij static const struct icst_params impd1_vco1_params = {
4870ee6577SLinus Walleij 	.ref		= 24000000,	/* 24 MHz */
4970ee6577SLinus Walleij 	.vco_max	= ICST525_VCO_MAX_3V,
5070ee6577SLinus Walleij 	.vco_min	= ICST525_VCO_MIN,
5170ee6577SLinus Walleij 	.vd_min		= 12,
5270ee6577SLinus Walleij 	.vd_max		= 519,
5370ee6577SLinus Walleij 	.rd_min		= 3,
5470ee6577SLinus Walleij 	.rd_max		= 120,
5570ee6577SLinus Walleij 	.s2div		= icst525_s2div,
5670ee6577SLinus Walleij 	.idx2s		= icst525_idx2s,
5770ee6577SLinus Walleij };
5870ee6577SLinus Walleij 
5970ee6577SLinus Walleij static const struct clk_icst_desc impd1_icst1_desc = {
608e048b99SLinus Walleij 	.params = &impd1_vco1_params,
6170ee6577SLinus Walleij 	.vco_offset = IMPD1_OSC1,
6270ee6577SLinus Walleij 	.lock_offset = IMPD1_LOCK,
6370ee6577SLinus Walleij };
6470ee6577SLinus Walleij 
658e048b99SLinus Walleij static const struct icst_params impd1_vco2_params = {
668e048b99SLinus Walleij 	.ref		= 24000000,	/* 24 MHz */
678e048b99SLinus Walleij 	.vco_max	= ICST525_VCO_MAX_3V,
688e048b99SLinus Walleij 	.vco_min	= ICST525_VCO_MIN,
698e048b99SLinus Walleij 	.vd_min		= 12,
708e048b99SLinus Walleij 	.vd_max		= 519,
718e048b99SLinus Walleij 	.rd_min		= 3,
728e048b99SLinus Walleij 	.rd_max		= 120,
738e048b99SLinus Walleij 	.s2div		= icst525_s2div,
748e048b99SLinus Walleij 	.idx2s		= icst525_idx2s,
758e048b99SLinus Walleij };
768e048b99SLinus Walleij 
778e048b99SLinus Walleij static const struct clk_icst_desc impd1_icst2_desc = {
788e048b99SLinus Walleij 	.params = &impd1_vco2_params,
798e048b99SLinus Walleij 	.vco_offset = IMPD1_OSC2,
808e048b99SLinus Walleij 	.lock_offset = IMPD1_LOCK,
818e048b99SLinus Walleij };
828e048b99SLinus Walleij 
8370ee6577SLinus Walleij /**
8470ee6577SLinus Walleij  * integrator_impd1_clk_init() - set up the integrator clock tree
8570ee6577SLinus Walleij  * @base: base address of the logic module (LM)
8670ee6577SLinus Walleij  * @id: the ID of this LM
8770ee6577SLinus Walleij  */
8870ee6577SLinus Walleij void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
8970ee6577SLinus Walleij {
9070ee6577SLinus Walleij 	struct impd1_clk *imc;
9170ee6577SLinus Walleij 	struct clk *clk;
92222cb1bfSLinus Walleij 	struct clk *pclk;
9370ee6577SLinus Walleij 	int i;
9470ee6577SLinus Walleij 
9570ee6577SLinus Walleij 	if (id > 3) {
9670ee6577SLinus Walleij 		pr_crit("no more than 4 LMs can be attached\n");
9770ee6577SLinus Walleij 		return;
9870ee6577SLinus Walleij 	}
9970ee6577SLinus Walleij 	imc = &impd1_clks[id];
10070ee6577SLinus Walleij 
101222cb1bfSLinus Walleij 	/* Register the fixed rate PCLK */
102222cb1bfSLinus Walleij 	imc->pclkname = kasprintf(GFP_KERNEL, "lm%x-pclk", id);
103ac82a8b5SStephen Boyd 	pclk = clk_register_fixed_rate(NULL, imc->pclkname, NULL, 0, 0);
104222cb1bfSLinus Walleij 	imc->pclk = pclk;
105222cb1bfSLinus Walleij 
1068e048b99SLinus Walleij 	imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id);
107bf6edb4bSLinus Walleij 	clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL,
108bf6edb4bSLinus Walleij 				base);
109ae6e694eSLinus Walleij 	imc->vco1clk = clk;
110222cb1bfSLinus Walleij 	imc->clks[0] = clkdev_alloc(pclk, "apb_pclk", "lm%x:01000", id);
111222cb1bfSLinus Walleij 	imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id);
11270ee6577SLinus Walleij 
1138e048b99SLinus Walleij 	/* VCO2 is also called "CLK2" */
1148e048b99SLinus Walleij 	imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id);
115bf6edb4bSLinus Walleij 	clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, NULL,
116bf6edb4bSLinus Walleij 				base);
1178e048b99SLinus Walleij 	imc->vco2clk = clk;
1188e048b99SLinus Walleij 
1198e048b99SLinus Walleij 	/* MMCI uses CLK2 right off */
120222cb1bfSLinus Walleij 	imc->clks[2] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00700", id);
121222cb1bfSLinus Walleij 	imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id);
1228e048b99SLinus Walleij 
1238e048b99SLinus Walleij 	/* UART reference clock divides CLK2 by a fixed factor 4 */
1248e048b99SLinus Walleij 	imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id);
1258e048b99SLinus Walleij 	clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name,
1268e048b99SLinus Walleij 				   CLK_IGNORE_UNUSED, 1, 4);
12770ee6577SLinus Walleij 	imc->uartclk = clk;
128222cb1bfSLinus Walleij 	imc->clks[4] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00100", id);
129222cb1bfSLinus Walleij 	imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id);
130222cb1bfSLinus Walleij 	imc->clks[6] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00200", id);
131222cb1bfSLinus Walleij 	imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id);
1328e048b99SLinus Walleij 
1338e048b99SLinus Walleij 	/* SPI PL022 clock divides CLK2 by a fixed factor 64 */
1348e048b99SLinus Walleij 	imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id);
1358e048b99SLinus Walleij 	clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name,
1368e048b99SLinus Walleij 				   CLK_IGNORE_UNUSED, 1, 64);
137222cb1bfSLinus Walleij 	imc->clks[8] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00300", id);
138222cb1bfSLinus Walleij 	imc->clks[9] = clkdev_alloc(clk, NULL, "lm%x:00300", id);
139222cb1bfSLinus Walleij 
140222cb1bfSLinus Walleij 	/* The GPIO blocks and AACI have only PCLK */
141222cb1bfSLinus Walleij 	imc->clks[10] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00400", id);
142222cb1bfSLinus Walleij 	imc->clks[11] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00500", id);
143222cb1bfSLinus Walleij 	imc->clks[12] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00800", id);
1448e048b99SLinus Walleij 
1458e048b99SLinus Walleij 	/* Smart Card clock divides CLK2 by a fixed factor 4 */
1468e048b99SLinus Walleij 	imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id);
1478e048b99SLinus Walleij 	clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name,
1488e048b99SLinus Walleij 				   CLK_IGNORE_UNUSED, 1, 4);
1498e048b99SLinus Walleij 	imc->scclk = clk;
150222cb1bfSLinus Walleij 	imc->clks[13] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00600", id);
151222cb1bfSLinus Walleij 	imc->clks[14] = clkdev_alloc(clk, NULL, "lm%x:00600", id);
15270ee6577SLinus Walleij 
15370ee6577SLinus Walleij 	for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
15470ee6577SLinus Walleij 		clkdev_add(imc->clks[i]);
15570ee6577SLinus Walleij }
156a218d7faSArnd Bergmann EXPORT_SYMBOL_GPL(integrator_impd1_clk_init);
15770ee6577SLinus Walleij 
15870ee6577SLinus Walleij void integrator_impd1_clk_exit(unsigned int id)
15970ee6577SLinus Walleij {
16070ee6577SLinus Walleij 	int i;
16170ee6577SLinus Walleij 	struct impd1_clk *imc;
16270ee6577SLinus Walleij 
16370ee6577SLinus Walleij 	if (id > 3)
16470ee6577SLinus Walleij 		return;
16570ee6577SLinus Walleij 	imc = &impd1_clks[id];
16670ee6577SLinus Walleij 
16770ee6577SLinus Walleij 	for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
16870ee6577SLinus Walleij 		clkdev_drop(imc->clks[i]);
1698e048b99SLinus Walleij 	clk_unregister(imc->spiclk);
17070ee6577SLinus Walleij 	clk_unregister(imc->uartclk);
1718e048b99SLinus Walleij 	clk_unregister(imc->vco2clk);
1728e048b99SLinus Walleij 	clk_unregister(imc->vco1clk);
173222cb1bfSLinus Walleij 	clk_unregister(imc->pclk);
1748e048b99SLinus Walleij 	kfree(imc->scname);
1758e048b99SLinus Walleij 	kfree(imc->spiname);
1768e048b99SLinus Walleij 	kfree(imc->uartname);
1778e048b99SLinus Walleij 	kfree(imc->vco2name);
1788e048b99SLinus Walleij 	kfree(imc->vco1name);
179222cb1bfSLinus Walleij 	kfree(imc->pclkname);
18070ee6577SLinus Walleij }
181a218d7faSArnd Bergmann EXPORT_SYMBOL_GPL(integrator_impd1_clk_exit);
18284655b76SLinus Walleij 
18384655b76SLinus Walleij static int integrator_impd1_clk_spawn(struct device *dev,
18484655b76SLinus Walleij 				      struct device_node *parent,
18584655b76SLinus Walleij 				      struct device_node *np)
18684655b76SLinus Walleij {
18784655b76SLinus Walleij 	struct regmap *map;
18884655b76SLinus Walleij 	struct clk *clk = ERR_PTR(-EINVAL);
18984655b76SLinus Walleij 	const char *name = np->name;
19084655b76SLinus Walleij 	const char *parent_name;
19184655b76SLinus Walleij 	const struct clk_icst_desc *desc;
19284655b76SLinus Walleij 	int ret;
19384655b76SLinus Walleij 
19484655b76SLinus Walleij 	map = syscon_node_to_regmap(parent);
19584655b76SLinus Walleij 	if (IS_ERR(map)) {
19684655b76SLinus Walleij 		pr_err("no regmap for syscon IM-PD1 ICST clock parent\n");
19784655b76SLinus Walleij 		return PTR_ERR(map);
19884655b76SLinus Walleij 	}
19984655b76SLinus Walleij 
20084655b76SLinus Walleij 	if (of_device_is_compatible(np, "arm,impd1-vco1")) {
20184655b76SLinus Walleij 		desc = &impd1_icst1_desc;
20284655b76SLinus Walleij 	} else if (of_device_is_compatible(np, "arm,impd1-vco2")) {
20384655b76SLinus Walleij 		desc = &impd1_icst2_desc;
20484655b76SLinus Walleij 	} else {
20584655b76SLinus Walleij 		dev_err(dev, "not a clock node %s\n", name);
20684655b76SLinus Walleij 		return -ENODEV;
20784655b76SLinus Walleij 	}
20884655b76SLinus Walleij 
20984655b76SLinus Walleij 	parent_name = of_clk_get_parent_name(np, 0);
21084655b76SLinus Walleij 	clk = icst_clk_setup(NULL, desc, name, parent_name, map,
21184655b76SLinus Walleij 			     ICST_INTEGRATOR_IM_PD1);
21284655b76SLinus Walleij 	if (!IS_ERR(clk)) {
21384655b76SLinus Walleij 		of_clk_add_provider(np, of_clk_src_simple_get, clk);
21484655b76SLinus Walleij 		ret = 0;
21584655b76SLinus Walleij 	} else {
21684655b76SLinus Walleij 		dev_err(dev, "error setting up IM-PD1 ICST clock\n");
21784655b76SLinus Walleij 		ret = PTR_ERR(clk);
21884655b76SLinus Walleij 	}
21984655b76SLinus Walleij 
22084655b76SLinus Walleij 	return ret;
22184655b76SLinus Walleij }
22284655b76SLinus Walleij 
22384655b76SLinus Walleij static int integrator_impd1_clk_probe(struct platform_device *pdev)
22484655b76SLinus Walleij {
22584655b76SLinus Walleij 	struct device *dev = &pdev->dev;
22684655b76SLinus Walleij 	struct device_node *np = dev->of_node;
22784655b76SLinus Walleij 	struct device_node *child;
22884655b76SLinus Walleij 	int ret = 0;
22984655b76SLinus Walleij 
23084655b76SLinus Walleij 	for_each_available_child_of_node(np, child) {
23184655b76SLinus Walleij 		ret = integrator_impd1_clk_spawn(dev, np, child);
23284655b76SLinus Walleij 		if (ret)
23384655b76SLinus Walleij 			break;
23484655b76SLinus Walleij 	}
23584655b76SLinus Walleij 
23684655b76SLinus Walleij 	return ret;
23784655b76SLinus Walleij }
23884655b76SLinus Walleij 
23984655b76SLinus Walleij static const struct of_device_id impd1_syscon_match[] = {
24084655b76SLinus Walleij 	{ .compatible = "arm,im-pd1-syscon", },
24184655b76SLinus Walleij 	{}
24284655b76SLinus Walleij };
24384655b76SLinus Walleij MODULE_DEVICE_TABLE(of, impd1_syscon_match);
24484655b76SLinus Walleij 
24584655b76SLinus Walleij static struct platform_driver impd1_clk_driver = {
24684655b76SLinus Walleij 	.driver = {
24784655b76SLinus Walleij 		.name = "impd1-clk",
24884655b76SLinus Walleij 		.of_match_table = impd1_syscon_match,
24984655b76SLinus Walleij 	},
25084655b76SLinus Walleij 	.probe  = integrator_impd1_clk_probe,
25184655b76SLinus Walleij };
25284655b76SLinus Walleij builtin_platform_driver(impd1_clk_driver);
25384655b76SLinus Walleij 
25484655b76SLinus Walleij MODULE_AUTHOR("Linus Walleij <linusw@kernel.org>");
25584655b76SLinus Walleij MODULE_DESCRIPTION("Arm IM-PD1 module clock driver");
25684655b76SLinus Walleij MODULE_LICENSE("GPL v2");
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