1 /* 2 * Driver for the ICST307 VCO clock found in the ARM Reference designs. 3 * We wrap the custom interface from <asm/hardware/icst.h> into the generic 4 * clock framework. 5 * 6 * Copyright (C) 2012-2015 Linus Walleij 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * TODO: when all ARM reference designs are migrated to generic clocks, the 13 * ICST clock code from the ARM tree should probably be merged into this 14 * file. 15 */ 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/export.h> 19 #include <linux/err.h> 20 #include <linux/clk-provider.h> 21 #include <linux/io.h> 22 #include <linux/regmap.h> 23 #include <linux/mfd/syscon.h> 24 25 #include "icst.h" 26 #include "clk-icst.h" 27 28 /* Magic unlocking token used on all Versatile boards */ 29 #define VERSATILE_LOCK_VAL 0xA05F 30 31 #define VERSATILE_AUX_OSC_BITS 0x7FFFF 32 #define INTEGRATOR_AP_CM_BITS 0xFF 33 #define INTEGRATOR_AP_SYS_BITS 0xFF 34 #define INTEGRATOR_CP_CM_CORE_BITS 0x7FF 35 #define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000 36 37 #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8) 38 39 /** 40 * enum icst_control_type - the type of ICST control register 41 */ 42 enum icst_control_type { 43 ICST_VERSATILE, /* The standard type, all control bits available */ 44 ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */ 45 ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */ 46 ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ 47 ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ 48 ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ 49 }; 50 51 /** 52 * struct clk_icst - ICST VCO clock wrapper 53 * @hw: corresponding clock hardware entry 54 * @vcoreg: VCO register address 55 * @lockreg: VCO lock register address 56 * @params: parameters for this ICST instance 57 * @rate: current rate 58 * @ctype: the type of control register for the ICST 59 */ 60 struct clk_icst { 61 struct clk_hw hw; 62 struct regmap *map; 63 u32 vcoreg_off; 64 u32 lockreg_off; 65 struct icst_params *params; 66 unsigned long rate; 67 enum icst_control_type ctype; 68 }; 69 70 #define to_icst(_hw) container_of(_hw, struct clk_icst, hw) 71 72 /** 73 * vco_get() - get ICST VCO settings from a certain ICST 74 * @icst: the ICST clock to get 75 * @vco: the VCO struct to return the value in 76 */ 77 static int vco_get(struct clk_icst *icst, struct icst_vco *vco) 78 { 79 u32 val; 80 int ret; 81 82 ret = regmap_read(icst->map, icst->vcoreg_off, &val); 83 if (ret) 84 return ret; 85 86 /* 87 * The Integrator/AP core clock can only access the low eight 88 * bits of the v PLL divider. Bit 8 is tied low and always zero, 89 * r is hardwired to 22 and output divider s is hardwired to 1 90 * (divide by 2) according to the document 91 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and 92 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. 93 */ 94 if (icst->ctype == ICST_INTEGRATOR_AP_CM) { 95 vco->v = val & INTEGRATOR_AP_CM_BITS; 96 vco->r = 22; 97 vco->s = 1; 98 return 0; 99 } 100 101 /* 102 * The Integrator/AP system clock on the base board can only 103 * access the low eight bits of the v PLL divider. Bit 8 is tied low 104 * and always zero, r is hardwired to 46, and the output divider is 105 * hardwired to 3 (divide by 4) according to the document 106 * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B, 107 * page 3-16. 108 */ 109 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { 110 vco->v = val & INTEGRATOR_AP_SYS_BITS; 111 vco->r = 46; 112 vco->s = 3; 113 return 0; 114 } 115 116 /* 117 * The Integrator/AP PCI clock is using an odd pattern to create 118 * the child clock, basically a single bit called DIVX/Y is used 119 * to select between two different hardwired values: setting the 120 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the 121 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies 122 * 33 or 25 MHz respectively. 123 */ 124 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { 125 bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ); 126 127 vco->v = divxy ? 17 : 14; 128 vco->r = divxy ? 22 : 14; 129 vco->s = 1; 130 return 0; 131 } 132 133 /* 134 * The Integrator/CP core clock can access the low eight bits 135 * of the v PLL divider. Bit 8 is tied low and always zero, 136 * r is hardwired to 22 and the output divider s is accessible 137 * in bits 8 thru 10 according to the document 138 * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide" 139 * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10. 140 */ 141 if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) { 142 vco->v = val & 0xFF; 143 vco->r = 22; 144 vco->s = (val >> 8) & 7; 145 return 0; 146 } 147 148 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) { 149 vco->v = (val >> 12) & 0xFF; 150 vco->r = 22; 151 vco->s = (val >> 20) & 7; 152 return 0; 153 } 154 155 vco->v = val & 0x1ff; 156 vco->r = (val >> 9) & 0x7f; 157 vco->s = (val >> 16) & 03; 158 return 0; 159 } 160 161 /** 162 * vco_set() - commit changes to an ICST VCO 163 * @icst: the ICST clock to set 164 * @vco: the VCO struct to set the changes from 165 */ 166 static int vco_set(struct clk_icst *icst, struct icst_vco vco) 167 { 168 u32 mask; 169 u32 val; 170 int ret; 171 172 /* Mask the bits used by the VCO */ 173 switch (icst->ctype) { 174 case ICST_INTEGRATOR_AP_CM: 175 mask = INTEGRATOR_AP_CM_BITS; 176 val = vco.v & 0xFF; 177 if (vco.v & 0x100) 178 pr_err("ICST error: tried to set bit 8 of VDW\n"); 179 if (vco.s != 1) 180 pr_err("ICST error: tried to use VOD != 1\n"); 181 if (vco.r != 22) 182 pr_err("ICST error: tried to use RDW != 22\n"); 183 break; 184 case ICST_INTEGRATOR_AP_SYS: 185 mask = INTEGRATOR_AP_SYS_BITS; 186 val = vco.v & 0xFF; 187 if (vco.v & 0x100) 188 pr_err("ICST error: tried to set bit 8 of VDW\n"); 189 if (vco.s != 3) 190 pr_err("ICST error: tried to use VOD != 1\n"); 191 if (vco.r != 46) 192 pr_err("ICST error: tried to use RDW != 22\n"); 193 break; 194 case ICST_INTEGRATOR_CP_CM_CORE: 195 mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */ 196 val = (vco.v & 0xFF) | vco.s << 8; 197 if (vco.v & 0x100) 198 pr_err("ICST error: tried to set bit 8 of VDW\n"); 199 if (vco.r != 22) 200 pr_err("ICST error: tried to use RDW != 22\n"); 201 break; 202 case ICST_INTEGRATOR_CP_CM_MEM: 203 mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */ 204 val = ((vco.v & 0xFF) << 12) | (vco.s << 20); 205 if (vco.v & 0x100) 206 pr_err("ICST error: tried to set bit 8 of VDW\n"); 207 if (vco.r != 22) 208 pr_err("ICST error: tried to use RDW != 22\n"); 209 break; 210 default: 211 /* Regular auxilary oscillator */ 212 mask = VERSATILE_AUX_OSC_BITS; 213 val = vco.v | (vco.r << 9) | (vco.s << 16); 214 break; 215 } 216 217 pr_debug("ICST: new val = 0x%08x\n", val); 218 219 /* This magic unlocks the VCO so it can be controlled */ 220 ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL); 221 if (ret) 222 return ret; 223 ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val); 224 if (ret) 225 return ret; 226 /* This locks the VCO again */ 227 ret = regmap_write(icst->map, icst->lockreg_off, 0); 228 if (ret) 229 return ret; 230 return 0; 231 } 232 233 static unsigned long icst_recalc_rate(struct clk_hw *hw, 234 unsigned long parent_rate) 235 { 236 struct clk_icst *icst = to_icst(hw); 237 struct icst_vco vco; 238 int ret; 239 240 if (parent_rate) 241 icst->params->ref = parent_rate; 242 ret = vco_get(icst, &vco); 243 if (ret) { 244 pr_err("ICST: could not get VCO setting\n"); 245 return 0; 246 } 247 icst->rate = icst_hz(icst->params, vco); 248 return icst->rate; 249 } 250 251 static long icst_round_rate(struct clk_hw *hw, unsigned long rate, 252 unsigned long *prate) 253 { 254 struct clk_icst *icst = to_icst(hw); 255 struct icst_vco vco; 256 257 if (icst->ctype == ICST_INTEGRATOR_AP_CM || 258 icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) { 259 if (rate <= 12000000) 260 return 12000000; 261 if (rate >= 160000000) 262 return 160000000; 263 /* Slam to closest megahertz */ 264 return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000; 265 } 266 267 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) { 268 if (rate <= 6000000) 269 return 6000000; 270 if (rate >= 66000000) 271 return 66000000; 272 /* Slam to closest 0.5 megahertz */ 273 return DIV_ROUND_CLOSEST(rate, 500000) * 500000; 274 } 275 276 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { 277 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ 278 if (rate <= 3000000) 279 return 3000000; 280 if (rate >= 50000000) 281 return 5000000; 282 /* Slam to closest 0.25 MHz */ 283 return DIV_ROUND_CLOSEST(rate, 250000) * 250000; 284 } 285 286 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { 287 /* 288 * If we're below or less than halfway from 25 to 33 MHz 289 * select 25 MHz 290 */ 291 if (rate <= 25000000 || rate < 29000000) 292 return 25000000; 293 /* Else just return the default frequency */ 294 return 33000000; 295 } 296 297 vco = icst_hz_to_vco(icst->params, rate); 298 return icst_hz(icst->params, vco); 299 } 300 301 static int icst_set_rate(struct clk_hw *hw, unsigned long rate, 302 unsigned long parent_rate) 303 { 304 struct clk_icst *icst = to_icst(hw); 305 struct icst_vco vco; 306 307 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { 308 /* This clock is especially primitive */ 309 unsigned int val; 310 int ret; 311 312 if (rate == 25000000) { 313 val = 0; 314 } else if (rate == 33000000) { 315 val = INTEGRATOR_AP_PCI_25_33_MHZ; 316 } else { 317 pr_err("ICST: cannot set PCI frequency %lu\n", 318 rate); 319 return -EINVAL; 320 } 321 ret = regmap_write(icst->map, icst->lockreg_off, 322 VERSATILE_LOCK_VAL); 323 if (ret) 324 return ret; 325 ret = regmap_update_bits(icst->map, icst->vcoreg_off, 326 INTEGRATOR_AP_PCI_25_33_MHZ, 327 val); 328 if (ret) 329 return ret; 330 /* This locks the VCO again */ 331 ret = regmap_write(icst->map, icst->lockreg_off, 0); 332 if (ret) 333 return ret; 334 return 0; 335 } 336 337 if (parent_rate) 338 icst->params->ref = parent_rate; 339 vco = icst_hz_to_vco(icst->params, rate); 340 icst->rate = icst_hz(icst->params, vco); 341 return vco_set(icst, vco); 342 } 343 344 static const struct clk_ops icst_ops = { 345 .recalc_rate = icst_recalc_rate, 346 .round_rate = icst_round_rate, 347 .set_rate = icst_set_rate, 348 }; 349 350 static struct clk *icst_clk_setup(struct device *dev, 351 const struct clk_icst_desc *desc, 352 const char *name, 353 const char *parent_name, 354 struct regmap *map, 355 enum icst_control_type ctype) 356 { 357 struct clk *clk; 358 struct clk_icst *icst; 359 struct clk_init_data init; 360 struct icst_params *pclone; 361 362 icst = kzalloc(sizeof(*icst), GFP_KERNEL); 363 if (!icst) 364 return ERR_PTR(-ENOMEM); 365 366 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL); 367 if (!pclone) { 368 kfree(icst); 369 return ERR_PTR(-ENOMEM); 370 } 371 372 init.name = name; 373 init.ops = &icst_ops; 374 init.flags = 0; 375 init.parent_names = (parent_name ? &parent_name : NULL); 376 init.num_parents = (parent_name ? 1 : 0); 377 icst->map = map; 378 icst->hw.init = &init; 379 icst->params = pclone; 380 icst->vcoreg_off = desc->vco_offset; 381 icst->lockreg_off = desc->lock_offset; 382 icst->ctype = ctype; 383 384 clk = clk_register(dev, &icst->hw); 385 if (IS_ERR(clk)) { 386 kfree(pclone); 387 kfree(icst); 388 } 389 390 return clk; 391 } 392 393 struct clk *icst_clk_register(struct device *dev, 394 const struct clk_icst_desc *desc, 395 const char *name, 396 const char *parent_name, 397 void __iomem *base) 398 { 399 struct regmap_config icst_regmap_conf = { 400 .reg_bits = 32, 401 .val_bits = 32, 402 .reg_stride = 4, 403 }; 404 struct regmap *map; 405 406 map = regmap_init_mmio(dev, base, &icst_regmap_conf); 407 if (IS_ERR(map)) { 408 pr_err("could not initialize ICST regmap\n"); 409 return ERR_CAST(map); 410 } 411 return icst_clk_setup(dev, desc, name, parent_name, map, 412 ICST_VERSATILE); 413 } 414 EXPORT_SYMBOL_GPL(icst_clk_register); 415 416 #ifdef CONFIG_OF 417 /* 418 * In a device tree, an memory-mapped ICST clock appear as a child 419 * of a syscon node. Assume this and probe it only as a child of a 420 * syscon. 421 */ 422 423 static const struct icst_params icst525_params = { 424 .vco_max = ICST525_VCO_MAX_5V, 425 .vco_min = ICST525_VCO_MIN, 426 .vd_min = 8, 427 .vd_max = 263, 428 .rd_min = 3, 429 .rd_max = 65, 430 .s2div = icst525_s2div, 431 .idx2s = icst525_idx2s, 432 }; 433 434 static const struct icst_params icst307_params = { 435 .vco_max = ICST307_VCO_MAX, 436 .vco_min = ICST307_VCO_MIN, 437 .vd_min = 4 + 8, 438 .vd_max = 511 + 8, 439 .rd_min = 1 + 2, 440 .rd_max = 127 + 2, 441 .s2div = icst307_s2div, 442 .idx2s = icst307_idx2s, 443 }; 444 445 /** 446 * The core modules on the Integrator/AP and Integrator/CP have 447 * especially crippled ICST525 control. 448 */ 449 static const struct icst_params icst525_apcp_cm_params = { 450 .vco_max = ICST525_VCO_MAX_5V, 451 .vco_min = ICST525_VCO_MIN, 452 /* Minimum 12 MHz, VDW = 4 */ 453 .vd_min = 12, 454 /* 455 * Maximum 160 MHz, VDW = 152 for all core modules, but 456 * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually 457 * go to 200 MHz (max VDW = 192). 458 */ 459 .vd_max = 192, 460 /* r is hardcoded to 22 and this is the actual divisor, +2 */ 461 .rd_min = 24, 462 .rd_max = 24, 463 .s2div = icst525_s2div, 464 .idx2s = icst525_idx2s, 465 }; 466 467 static const struct icst_params icst525_ap_sys_params = { 468 .vco_max = ICST525_VCO_MAX_5V, 469 .vco_min = ICST525_VCO_MIN, 470 /* Minimum 3 MHz, VDW = 4 */ 471 .vd_min = 3, 472 /* Maximum 50 MHz, VDW = 192 */ 473 .vd_max = 50, 474 /* r is hardcoded to 46 and this is the actual divisor, +2 */ 475 .rd_min = 48, 476 .rd_max = 48, 477 .s2div = icst525_s2div, 478 .idx2s = icst525_idx2s, 479 }; 480 481 static const struct icst_params icst525_ap_pci_params = { 482 .vco_max = ICST525_VCO_MAX_5V, 483 .vco_min = ICST525_VCO_MIN, 484 /* Minimum 25 MHz */ 485 .vd_min = 25, 486 /* Maximum 33 MHz */ 487 .vd_max = 33, 488 /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */ 489 .rd_min = 16, 490 .rd_max = 24, 491 .s2div = icst525_s2div, 492 .idx2s = icst525_idx2s, 493 }; 494 495 static void __init of_syscon_icst_setup(struct device_node *np) 496 { 497 struct device_node *parent; 498 struct regmap *map; 499 struct clk_icst_desc icst_desc; 500 const char *name = np->name; 501 const char *parent_name; 502 struct clk *regclk; 503 enum icst_control_type ctype; 504 505 /* We do not release this reference, we are using it perpetually */ 506 parent = of_get_parent(np); 507 if (!parent) { 508 pr_err("no parent node for syscon ICST clock\n"); 509 return; 510 } 511 map = syscon_node_to_regmap(parent); 512 if (IS_ERR(map)) { 513 pr_err("no regmap for syscon ICST clock parent\n"); 514 return; 515 } 516 517 if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) { 518 pr_err("no VCO register offset for ICST clock\n"); 519 return; 520 } 521 if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) { 522 pr_err("no lock register offset for ICST clock\n"); 523 return; 524 } 525 526 if (of_device_is_compatible(np, "arm,syscon-icst525")) { 527 icst_desc.params = &icst525_params; 528 ctype = ICST_VERSATILE; 529 } else if (of_device_is_compatible(np, "arm,syscon-icst307")) { 530 icst_desc.params = &icst307_params; 531 ctype = ICST_VERSATILE; 532 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) { 533 icst_desc.params = &icst525_apcp_cm_params; 534 ctype = ICST_INTEGRATOR_AP_CM; 535 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) { 536 icst_desc.params = &icst525_ap_sys_params; 537 ctype = ICST_INTEGRATOR_AP_SYS; 538 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) { 539 icst_desc.params = &icst525_ap_pci_params; 540 ctype = ICST_INTEGRATOR_AP_PCI; 541 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) { 542 icst_desc.params = &icst525_apcp_cm_params; 543 ctype = ICST_INTEGRATOR_CP_CM_CORE; 544 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) { 545 icst_desc.params = &icst525_apcp_cm_params; 546 ctype = ICST_INTEGRATOR_CP_CM_MEM; 547 } else { 548 pr_err("unknown ICST clock %s\n", name); 549 return; 550 } 551 552 /* Parent clock name is not the same as node parent */ 553 parent_name = of_clk_get_parent_name(np, 0); 554 555 regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype); 556 if (IS_ERR(regclk)) { 557 pr_err("error setting up syscon ICST clock %s\n", name); 558 return; 559 } 560 of_clk_add_provider(np, of_clk_src_simple_get, regclk); 561 pr_debug("registered syscon ICST clock %s\n", name); 562 } 563 564 CLK_OF_DECLARE(arm_syscon_icst525_clk, 565 "arm,syscon-icst525", of_syscon_icst_setup); 566 CLK_OF_DECLARE(arm_syscon_icst307_clk, 567 "arm,syscon-icst307", of_syscon_icst_setup); 568 CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk, 569 "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup); 570 CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk, 571 "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup); 572 CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk, 573 "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup); 574 CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk, 575 "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup); 576 CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk, 577 "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup); 578 #endif 579