1 /* 2 * Clock definitions for u8500 platform. 3 * 4 * Copyright (C) 2012 ST-Ericsson SA 5 * Author: Ulf Hansson <ulf.hansson@linaro.org> 6 * 7 * License terms: GNU General Public License (GPL) version 2 8 */ 9 10 #include <linux/of.h> 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/mfd/dbx500-prcmu.h> 15 #include <linux/platform_data/clk-ux500.h> 16 #include "clk.h" 17 18 #define PRCC_NUM_PERIPH_CLUSTERS 6 19 #define PRCC_PERIPHS_PER_CLUSTER 32 20 21 static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; 22 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 23 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 24 25 #define PRCC_SHOW(clk, base, bit) \ 26 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] 27 #define PRCC_PCLK_STORE(clk, base, bit) \ 28 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 29 #define PRCC_KCLK_STORE(clk, base, bit) \ 30 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 31 32 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, 33 void *data) 34 { 35 struct clk **clk_data = data; 36 unsigned int base, bit; 37 38 if (clkspec->args_count != 2) 39 return ERR_PTR(-EINVAL); 40 41 base = clkspec->args[0]; 42 bit = clkspec->args[1]; 43 44 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { 45 pr_err("%s: invalid PRCC base %d\n", __func__, base); 46 return ERR_PTR(-EINVAL); 47 } 48 49 return PRCC_SHOW(clk_data, base, bit); 50 } 51 52 static const struct of_device_id u8500_clk_of_match[] = { 53 { .compatible = "stericsson,u8500-clks", }, 54 { }, 55 }; 56 57 void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 58 u32 clkrst5_base, u32 clkrst6_base) 59 { 60 struct prcmu_fw_version *fw_version; 61 struct device_node *np = NULL; 62 struct device_node *child = NULL; 63 const char *sgaclk_parent = NULL; 64 struct clk *clk, *rtc_clk, *twd_clk; 65 66 if (of_have_populated_dt()) 67 np = of_find_matching_node(NULL, u8500_clk_of_match); 68 if (!np) { 69 pr_err("Either DT or U8500 Clock node not found\n"); 70 return; 71 } 72 73 /* Clock sources */ 74 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, 75 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 76 prcmu_clk[PRCMU_PLLSOC0] = clk; 77 78 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, 79 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 80 prcmu_clk[PRCMU_PLLSOC1] = clk; 81 82 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, 83 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 84 prcmu_clk[PRCMU_PLLDDR] = clk; 85 86 /* FIXME: Add sys, ulp and int clocks here. */ 87 88 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", 89 CLK_IS_ROOT|CLK_IGNORE_UNUSED, 90 32768); 91 92 /* PRCMU clocks */ 93 fw_version = prcmu_get_fw_version(); 94 if (fw_version != NULL) { 95 switch (fw_version->project) { 96 case PRCMU_FW_PROJECT_U8500_C2: 97 case PRCMU_FW_PROJECT_U8520: 98 case PRCMU_FW_PROJECT_U8420: 99 sgaclk_parent = "soc0_pll"; 100 break; 101 default: 102 break; 103 } 104 } 105 106 if (sgaclk_parent) 107 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, 108 PRCMU_SGACLK, 0); 109 else 110 clk = clk_reg_prcmu_gate("sgclk", NULL, 111 PRCMU_SGACLK, CLK_IS_ROOT); 112 prcmu_clk[PRCMU_SGACLK] = clk; 113 114 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); 115 prcmu_clk[PRCMU_UARTCLK] = clk; 116 117 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); 118 prcmu_clk[PRCMU_MSP02CLK] = clk; 119 120 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); 121 prcmu_clk[PRCMU_MSP1CLK] = clk; 122 123 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); 124 prcmu_clk[PRCMU_I2CCLK] = clk; 125 126 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); 127 prcmu_clk[PRCMU_SLIMCLK] = clk; 128 129 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); 130 prcmu_clk[PRCMU_PER1CLK] = clk; 131 132 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); 133 prcmu_clk[PRCMU_PER2CLK] = clk; 134 135 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); 136 prcmu_clk[PRCMU_PER3CLK] = clk; 137 138 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); 139 prcmu_clk[PRCMU_PER5CLK] = clk; 140 141 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); 142 prcmu_clk[PRCMU_PER6CLK] = clk; 143 144 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); 145 prcmu_clk[PRCMU_PER7CLK] = clk; 146 147 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, 148 CLK_IS_ROOT|CLK_SET_RATE_GATE); 149 prcmu_clk[PRCMU_LCDCLK] = clk; 150 151 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); 152 prcmu_clk[PRCMU_BMLCLK] = clk; 153 154 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, 155 CLK_IS_ROOT|CLK_SET_RATE_GATE); 156 prcmu_clk[PRCMU_HSITXCLK] = clk; 157 158 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, 159 CLK_IS_ROOT|CLK_SET_RATE_GATE); 160 prcmu_clk[PRCMU_HSIRXCLK] = clk; 161 162 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, 163 CLK_IS_ROOT|CLK_SET_RATE_GATE); 164 prcmu_clk[PRCMU_HDMICLK] = clk; 165 166 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); 167 prcmu_clk[PRCMU_APEATCLK] = clk; 168 169 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, 170 CLK_IS_ROOT); 171 prcmu_clk[PRCMU_APETRACECLK] = clk; 172 173 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); 174 prcmu_clk[PRCMU_MCDECLK] = clk; 175 176 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 177 CLK_IS_ROOT); 178 prcmu_clk[PRCMU_IPI2CCLK] = clk; 179 180 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 181 CLK_IS_ROOT); 182 prcmu_clk[PRCMU_DSIALTCLK] = clk; 183 184 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); 185 prcmu_clk[PRCMU_DMACLK] = clk; 186 187 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); 188 prcmu_clk[PRCMU_B2R2CLK] = clk; 189 190 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, 191 CLK_IS_ROOT|CLK_SET_RATE_GATE); 192 prcmu_clk[PRCMU_TVCLK] = clk; 193 194 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); 195 prcmu_clk[PRCMU_SSPCLK] = clk; 196 197 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); 198 prcmu_clk[PRCMU_RNGCLK] = clk; 199 200 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); 201 prcmu_clk[PRCMU_UICCCLK] = clk; 202 203 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); 204 prcmu_clk[PRCMU_TIMCLK] = clk; 205 206 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, 207 100000000, 208 CLK_IS_ROOT|CLK_SET_RATE_GATE); 209 prcmu_clk[PRCMU_SDMMCCLK] = clk; 210 211 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", 212 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); 213 prcmu_clk[PRCMU_PLLDSI] = clk; 214 215 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", 216 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); 217 prcmu_clk[PRCMU_DSI0CLK] = clk; 218 219 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", 220 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); 221 prcmu_clk[PRCMU_DSI1CLK] = clk; 222 223 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", 224 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); 225 prcmu_clk[PRCMU_DSI0ESCCLK] = clk; 226 227 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", 228 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); 229 prcmu_clk[PRCMU_DSI1ESCCLK] = clk; 230 231 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", 232 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); 233 prcmu_clk[PRCMU_DSI2ESCCLK] = clk; 234 235 clk = clk_reg_prcmu_scalable_rate("armss", NULL, 236 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); 237 prcmu_clk[PRCMU_ARMSS] = clk; 238 239 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", 240 CLK_IGNORE_UNUSED, 1, 2); 241 242 /* 243 * FIXME: Add special handled PRCMU clocks here: 244 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. 245 * 2. ab9540_clkout1yuv, see clkout0yuv 246 */ 247 248 /* PRCC P-clocks */ 249 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, 250 BIT(0), 0); 251 PRCC_PCLK_STORE(clk, 1, 0); 252 253 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, 254 BIT(1), 0); 255 PRCC_PCLK_STORE(clk, 1, 1); 256 257 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, 258 BIT(2), 0); 259 PRCC_PCLK_STORE(clk, 1, 2); 260 261 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, 262 BIT(3), 0); 263 PRCC_PCLK_STORE(clk, 1, 3); 264 265 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, 266 BIT(4), 0); 267 PRCC_PCLK_STORE(clk, 1, 4); 268 269 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, 270 BIT(5), 0); 271 PRCC_PCLK_STORE(clk, 1, 5); 272 273 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, 274 BIT(6), 0); 275 PRCC_PCLK_STORE(clk, 1, 6); 276 277 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, 278 BIT(7), 0); 279 PRCC_PCLK_STORE(clk, 1, 7); 280 281 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, 282 BIT(8), 0); 283 PRCC_PCLK_STORE(clk, 1, 8); 284 285 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, 286 BIT(9), 0); 287 PRCC_PCLK_STORE(clk, 1, 9); 288 289 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, 290 BIT(10), 0); 291 PRCC_PCLK_STORE(clk, 1, 10); 292 293 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, 294 BIT(11), 0); 295 PRCC_PCLK_STORE(clk, 1, 11); 296 297 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, 298 BIT(0), 0); 299 PRCC_PCLK_STORE(clk, 2, 0); 300 301 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, 302 BIT(1), 0); 303 PRCC_PCLK_STORE(clk, 2, 1); 304 305 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, 306 BIT(2), 0); 307 PRCC_PCLK_STORE(clk, 2, 2); 308 309 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, 310 BIT(3), 0); 311 PRCC_PCLK_STORE(clk, 2, 3); 312 313 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, 314 BIT(4), 0); 315 PRCC_PCLK_STORE(clk, 2, 4); 316 317 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, 318 BIT(5), 0); 319 PRCC_PCLK_STORE(clk, 2, 5); 320 321 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, 322 BIT(6), 0); 323 PRCC_PCLK_STORE(clk, 2, 6); 324 325 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, 326 BIT(7), 0); 327 PRCC_PCLK_STORE(clk, 2, 7); 328 329 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, 330 BIT(8), 0); 331 PRCC_PCLK_STORE(clk, 2, 8); 332 333 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, 334 BIT(9), 0); 335 PRCC_PCLK_STORE(clk, 2, 9); 336 337 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, 338 BIT(10), 0); 339 PRCC_PCLK_STORE(clk, 2, 10); 340 341 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, 342 BIT(11), 0); 343 PRCC_PCLK_STORE(clk, 2, 11); 344 345 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, 346 BIT(12), 0); 347 PRCC_PCLK_STORE(clk, 2, 12); 348 349 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, 350 BIT(0), 0); 351 PRCC_PCLK_STORE(clk, 3, 0); 352 353 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, 354 BIT(1), 0); 355 PRCC_PCLK_STORE(clk, 3, 1); 356 357 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, 358 BIT(2), 0); 359 PRCC_PCLK_STORE(clk, 3, 2); 360 361 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, 362 BIT(3), 0); 363 PRCC_PCLK_STORE(clk, 3, 3); 364 365 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, 366 BIT(4), 0); 367 PRCC_PCLK_STORE(clk, 3, 4); 368 369 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, 370 BIT(5), 0); 371 PRCC_PCLK_STORE(clk, 3, 5); 372 373 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, 374 BIT(6), 0); 375 PRCC_PCLK_STORE(clk, 3, 6); 376 377 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, 378 BIT(7), 0); 379 PRCC_PCLK_STORE(clk, 3, 7); 380 381 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, 382 BIT(8), 0); 383 PRCC_PCLK_STORE(clk, 3, 8); 384 385 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, 386 BIT(0), 0); 387 PRCC_PCLK_STORE(clk, 5, 0); 388 389 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, 390 BIT(1), 0); 391 PRCC_PCLK_STORE(clk, 5, 1); 392 393 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, 394 BIT(0), 0); 395 PRCC_PCLK_STORE(clk, 6, 0); 396 397 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, 398 BIT(1), 0); 399 PRCC_PCLK_STORE(clk, 6, 1); 400 401 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, 402 BIT(2), 0); 403 PRCC_PCLK_STORE(clk, 6, 2); 404 405 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, 406 BIT(3), 0); 407 PRCC_PCLK_STORE(clk, 6, 3); 408 409 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, 410 BIT(4), 0); 411 PRCC_PCLK_STORE(clk, 6, 4); 412 413 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, 414 BIT(5), 0); 415 PRCC_PCLK_STORE(clk, 6, 5); 416 417 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, 418 BIT(6), 0); 419 PRCC_PCLK_STORE(clk, 6, 6); 420 421 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, 422 BIT(7), 0); 423 PRCC_PCLK_STORE(clk, 6, 7); 424 425 /* PRCC K-clocks 426 * 427 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled 428 * by enabling just the K-clock, even if it is not a valid parent to 429 * the K-clock. Until drivers get fixed we might need some kind of 430 * "parent muxed join". 431 */ 432 433 /* Periph1 */ 434 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", 435 clkrst1_base, BIT(0), CLK_SET_RATE_GATE); 436 PRCC_KCLK_STORE(clk, 1, 0); 437 438 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", 439 clkrst1_base, BIT(1), CLK_SET_RATE_GATE); 440 PRCC_KCLK_STORE(clk, 1, 1); 441 442 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", 443 clkrst1_base, BIT(2), CLK_SET_RATE_GATE); 444 PRCC_KCLK_STORE(clk, 1, 2); 445 446 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", 447 clkrst1_base, BIT(3), CLK_SET_RATE_GATE); 448 PRCC_KCLK_STORE(clk, 1, 3); 449 450 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", 451 clkrst1_base, BIT(4), CLK_SET_RATE_GATE); 452 PRCC_KCLK_STORE(clk, 1, 4); 453 454 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", 455 clkrst1_base, BIT(5), CLK_SET_RATE_GATE); 456 PRCC_KCLK_STORE(clk, 1, 5); 457 458 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", 459 clkrst1_base, BIT(6), CLK_SET_RATE_GATE); 460 PRCC_KCLK_STORE(clk, 1, 6); 461 462 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", 463 clkrst1_base, BIT(8), CLK_SET_RATE_GATE); 464 PRCC_KCLK_STORE(clk, 1, 8); 465 466 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", 467 clkrst1_base, BIT(9), CLK_SET_RATE_GATE); 468 PRCC_KCLK_STORE(clk, 1, 9); 469 470 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", 471 clkrst1_base, BIT(10), CLK_SET_RATE_GATE); 472 PRCC_KCLK_STORE(clk, 1, 10); 473 474 /* Periph2 */ 475 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", 476 clkrst2_base, BIT(0), CLK_SET_RATE_GATE); 477 PRCC_KCLK_STORE(clk, 2, 0); 478 479 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", 480 clkrst2_base, BIT(2), CLK_SET_RATE_GATE); 481 PRCC_KCLK_STORE(clk, 2, 2); 482 483 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", 484 clkrst2_base, BIT(3), CLK_SET_RATE_GATE); 485 PRCC_KCLK_STORE(clk, 2, 3); 486 487 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", 488 clkrst2_base, BIT(4), CLK_SET_RATE_GATE); 489 PRCC_KCLK_STORE(clk, 2, 4); 490 491 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", 492 clkrst2_base, BIT(5), CLK_SET_RATE_GATE); 493 PRCC_KCLK_STORE(clk, 2, 5); 494 495 /* Note that rate is received from parent. */ 496 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", 497 clkrst2_base, BIT(6), 498 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 499 PRCC_KCLK_STORE(clk, 2, 6); 500 501 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", 502 clkrst2_base, BIT(7), 503 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 504 PRCC_KCLK_STORE(clk, 2, 7); 505 506 /* Periph3 */ 507 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", 508 clkrst3_base, BIT(1), CLK_SET_RATE_GATE); 509 PRCC_KCLK_STORE(clk, 3, 1); 510 511 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", 512 clkrst3_base, BIT(2), CLK_SET_RATE_GATE); 513 PRCC_KCLK_STORE(clk, 3, 2); 514 515 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", 516 clkrst3_base, BIT(3), CLK_SET_RATE_GATE); 517 PRCC_KCLK_STORE(clk, 3, 3); 518 519 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", 520 clkrst3_base, BIT(4), CLK_SET_RATE_GATE); 521 PRCC_KCLK_STORE(clk, 3, 4); 522 523 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 524 clkrst3_base, BIT(5), CLK_SET_RATE_GATE); 525 PRCC_KCLK_STORE(clk, 3, 5); 526 527 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 528 clkrst3_base, BIT(6), CLK_SET_RATE_GATE); 529 PRCC_KCLK_STORE(clk, 3, 6); 530 531 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", 532 clkrst3_base, BIT(7), CLK_SET_RATE_GATE); 533 PRCC_KCLK_STORE(clk, 3, 7); 534 535 /* Periph6 */ 536 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 537 clkrst6_base, BIT(0), CLK_SET_RATE_GATE); 538 PRCC_KCLK_STORE(clk, 6, 0); 539 540 for_each_child_of_node(np, child) { 541 static struct clk_onecell_data clk_data; 542 543 if (!of_node_cmp(child->name, "prcmu-clock")) { 544 clk_data.clks = prcmu_clk; 545 clk_data.clk_num = ARRAY_SIZE(prcmu_clk); 546 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data); 547 } 548 if (!of_node_cmp(child->name, "prcc-periph-clock")) 549 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk); 550 551 if (!of_node_cmp(child->name, "prcc-kernel-clock")) 552 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk); 553 554 if (!of_node_cmp(child->name, "rtc32k-clock")) 555 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk); 556 557 if (!of_node_cmp(child->name, "smp-twd-clock")) 558 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk); 559 } 560 } 561