1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clock definitions for u8500 platform. 4 * 5 * Copyright (C) 2012 ST-Ericsson SA 6 * Author: Ulf Hansson <ulf.hansson@linaro.org> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/clk-provider.h> 12 #include <linux/mfd/dbx500-prcmu.h> 13 #include "clk.h" 14 15 #define PRCC_NUM_PERIPH_CLUSTERS 6 16 #define PRCC_PERIPHS_PER_CLUSTER 32 17 18 static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; 19 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 20 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 21 22 #define PRCC_SHOW(clk, base, bit) \ 23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] 24 #define PRCC_PCLK_STORE(clk, base, bit) \ 25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 26 #define PRCC_KCLK_STORE(clk, base, bit) \ 27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 28 29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, 30 void *data) 31 { 32 struct clk **clk_data = data; 33 unsigned int base, bit; 34 35 if (clkspec->args_count != 2) 36 return ERR_PTR(-EINVAL); 37 38 base = clkspec->args[0]; 39 bit = clkspec->args[1]; 40 41 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { 42 pr_err("%s: invalid PRCC base %d\n", __func__, base); 43 return ERR_PTR(-EINVAL); 44 } 45 46 return PRCC_SHOW(clk_data, base, bit); 47 } 48 49 /* CLKRST4 is missing making it hard to index things */ 50 enum clkrst_index { 51 CLKRST1_INDEX = 0, 52 CLKRST2_INDEX, 53 CLKRST3_INDEX, 54 CLKRST5_INDEX, 55 CLKRST6_INDEX, 56 CLKRST_MAX, 57 }; 58 59 static void u8500_clk_init(struct device_node *np) 60 { 61 struct prcmu_fw_version *fw_version; 62 struct device_node *child = NULL; 63 const char *sgaclk_parent = NULL; 64 struct clk *clk, *rtc_clk, *twd_clk; 65 u32 bases[CLKRST_MAX]; 66 int i; 67 68 for (i = 0; i < ARRAY_SIZE(bases); i++) { 69 struct resource r; 70 71 if (of_address_to_resource(np, i, &r)) 72 /* Not much choice but to continue */ 73 pr_err("failed to get CLKRST %d base address\n", 74 i + 1); 75 bases[i] = r.start; 76 } 77 78 /* Clock sources */ 79 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, 80 CLK_IGNORE_UNUSED); 81 prcmu_clk[PRCMU_PLLSOC0] = clk; 82 83 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, 84 CLK_IGNORE_UNUSED); 85 prcmu_clk[PRCMU_PLLSOC1] = clk; 86 87 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, 88 CLK_IGNORE_UNUSED); 89 prcmu_clk[PRCMU_PLLDDR] = clk; 90 91 /* FIXME: Add sys, ulp and int clocks here. */ 92 93 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", 94 CLK_IGNORE_UNUSED, 95 32768); 96 97 /* PRCMU clocks */ 98 fw_version = prcmu_get_fw_version(); 99 if (fw_version != NULL) { 100 switch (fw_version->project) { 101 case PRCMU_FW_PROJECT_U8500_C2: 102 case PRCMU_FW_PROJECT_U8520: 103 case PRCMU_FW_PROJECT_U8420: 104 sgaclk_parent = "soc0_pll"; 105 break; 106 default: 107 break; 108 } 109 } 110 111 if (sgaclk_parent) 112 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, 113 PRCMU_SGACLK, 0); 114 else 115 clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0); 116 prcmu_clk[PRCMU_SGACLK] = clk; 117 118 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0); 119 prcmu_clk[PRCMU_UARTCLK] = clk; 120 121 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0); 122 prcmu_clk[PRCMU_MSP02CLK] = clk; 123 124 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0); 125 prcmu_clk[PRCMU_MSP1CLK] = clk; 126 127 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0); 128 prcmu_clk[PRCMU_I2CCLK] = clk; 129 130 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0); 131 prcmu_clk[PRCMU_SLIMCLK] = clk; 132 133 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0); 134 prcmu_clk[PRCMU_PER1CLK] = clk; 135 136 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0); 137 prcmu_clk[PRCMU_PER2CLK] = clk; 138 139 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0); 140 prcmu_clk[PRCMU_PER3CLK] = clk; 141 142 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0); 143 prcmu_clk[PRCMU_PER5CLK] = clk; 144 145 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0); 146 prcmu_clk[PRCMU_PER6CLK] = clk; 147 148 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0); 149 prcmu_clk[PRCMU_PER7CLK] = clk; 150 151 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, 152 CLK_SET_RATE_GATE); 153 prcmu_clk[PRCMU_LCDCLK] = clk; 154 155 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0); 156 prcmu_clk[PRCMU_BMLCLK] = clk; 157 158 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, 159 CLK_SET_RATE_GATE); 160 prcmu_clk[PRCMU_HSITXCLK] = clk; 161 162 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, 163 CLK_SET_RATE_GATE); 164 prcmu_clk[PRCMU_HSIRXCLK] = clk; 165 166 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, 167 CLK_SET_RATE_GATE); 168 prcmu_clk[PRCMU_HDMICLK] = clk; 169 170 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0); 171 prcmu_clk[PRCMU_APEATCLK] = clk; 172 173 clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0, 174 CLK_SET_RATE_GATE); 175 prcmu_clk[PRCMU_APETRACECLK] = clk; 176 177 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0); 178 prcmu_clk[PRCMU_MCDECLK] = clk; 179 180 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0); 181 prcmu_clk[PRCMU_IPI2CCLK] = clk; 182 183 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0); 184 prcmu_clk[PRCMU_DSIALTCLK] = clk; 185 186 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0); 187 prcmu_clk[PRCMU_DMACLK] = clk; 188 189 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0); 190 prcmu_clk[PRCMU_B2R2CLK] = clk; 191 192 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, 193 CLK_SET_RATE_GATE); 194 prcmu_clk[PRCMU_TVCLK] = clk; 195 196 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0); 197 prcmu_clk[PRCMU_SSPCLK] = clk; 198 199 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0); 200 prcmu_clk[PRCMU_RNGCLK] = clk; 201 202 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0); 203 prcmu_clk[PRCMU_UICCCLK] = clk; 204 205 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0); 206 prcmu_clk[PRCMU_TIMCLK] = clk; 207 208 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0); 209 prcmu_clk[PRCMU_SYSCLK] = clk; 210 211 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, 212 100000000, CLK_SET_RATE_GATE); 213 prcmu_clk[PRCMU_SDMMCCLK] = clk; 214 215 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", 216 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); 217 prcmu_clk[PRCMU_PLLDSI] = clk; 218 219 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", 220 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); 221 prcmu_clk[PRCMU_DSI0CLK] = clk; 222 223 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", 224 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); 225 prcmu_clk[PRCMU_DSI1CLK] = clk; 226 227 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", 228 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); 229 prcmu_clk[PRCMU_DSI0ESCCLK] = clk; 230 231 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", 232 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); 233 prcmu_clk[PRCMU_DSI1ESCCLK] = clk; 234 235 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", 236 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); 237 prcmu_clk[PRCMU_DSI2ESCCLK] = clk; 238 239 clk = clk_reg_prcmu_scalable_rate("armss", NULL, 240 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED); 241 prcmu_clk[PRCMU_ARMSS] = clk; 242 243 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", 244 CLK_IGNORE_UNUSED, 1, 2); 245 246 /* 247 * FIXME: Add special handled PRCMU clocks here: 248 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. 249 * 2. ab9540_clkout1yuv, see clkout0yuv 250 */ 251 252 /* PRCC P-clocks */ 253 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], 254 BIT(0), 0); 255 PRCC_PCLK_STORE(clk, 1, 0); 256 257 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], 258 BIT(1), 0); 259 PRCC_PCLK_STORE(clk, 1, 1); 260 261 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], 262 BIT(2), 0); 263 PRCC_PCLK_STORE(clk, 1, 2); 264 265 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], 266 BIT(3), 0); 267 PRCC_PCLK_STORE(clk, 1, 3); 268 269 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], 270 BIT(4), 0); 271 PRCC_PCLK_STORE(clk, 1, 4); 272 273 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], 274 BIT(5), 0); 275 PRCC_PCLK_STORE(clk, 1, 5); 276 277 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], 278 BIT(6), 0); 279 PRCC_PCLK_STORE(clk, 1, 6); 280 281 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], 282 BIT(7), 0); 283 PRCC_PCLK_STORE(clk, 1, 7); 284 285 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], 286 BIT(8), 0); 287 PRCC_PCLK_STORE(clk, 1, 8); 288 289 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], 290 BIT(9), 0); 291 PRCC_PCLK_STORE(clk, 1, 9); 292 293 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], 294 BIT(10), 0); 295 PRCC_PCLK_STORE(clk, 1, 10); 296 297 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], 298 BIT(11), 0); 299 PRCC_PCLK_STORE(clk, 1, 11); 300 301 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], 302 BIT(0), 0); 303 PRCC_PCLK_STORE(clk, 2, 0); 304 305 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], 306 BIT(1), 0); 307 PRCC_PCLK_STORE(clk, 2, 1); 308 309 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], 310 BIT(2), 0); 311 PRCC_PCLK_STORE(clk, 2, 2); 312 313 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], 314 BIT(3), 0); 315 PRCC_PCLK_STORE(clk, 2, 3); 316 317 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], 318 BIT(4), 0); 319 PRCC_PCLK_STORE(clk, 2, 4); 320 321 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], 322 BIT(5), 0); 323 PRCC_PCLK_STORE(clk, 2, 5); 324 325 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], 326 BIT(6), 0); 327 PRCC_PCLK_STORE(clk, 2, 6); 328 329 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], 330 BIT(7), 0); 331 PRCC_PCLK_STORE(clk, 2, 7); 332 333 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], 334 BIT(8), 0); 335 PRCC_PCLK_STORE(clk, 2, 8); 336 337 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], 338 BIT(9), 0); 339 PRCC_PCLK_STORE(clk, 2, 9); 340 341 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], 342 BIT(10), 0); 343 PRCC_PCLK_STORE(clk, 2, 10); 344 345 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], 346 BIT(11), 0); 347 PRCC_PCLK_STORE(clk, 2, 11); 348 349 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], 350 BIT(12), 0); 351 PRCC_PCLK_STORE(clk, 2, 12); 352 353 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], 354 BIT(0), 0); 355 PRCC_PCLK_STORE(clk, 3, 0); 356 357 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], 358 BIT(1), 0); 359 PRCC_PCLK_STORE(clk, 3, 1); 360 361 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], 362 BIT(2), 0); 363 PRCC_PCLK_STORE(clk, 3, 2); 364 365 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], 366 BIT(3), 0); 367 PRCC_PCLK_STORE(clk, 3, 3); 368 369 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], 370 BIT(4), 0); 371 PRCC_PCLK_STORE(clk, 3, 4); 372 373 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], 374 BIT(5), 0); 375 PRCC_PCLK_STORE(clk, 3, 5); 376 377 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], 378 BIT(6), 0); 379 PRCC_PCLK_STORE(clk, 3, 6); 380 381 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], 382 BIT(7), 0); 383 PRCC_PCLK_STORE(clk, 3, 7); 384 385 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], 386 BIT(8), 0); 387 PRCC_PCLK_STORE(clk, 3, 8); 388 389 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], 390 BIT(0), 0); 391 PRCC_PCLK_STORE(clk, 5, 0); 392 393 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], 394 BIT(1), 0); 395 PRCC_PCLK_STORE(clk, 5, 1); 396 397 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], 398 BIT(0), 0); 399 PRCC_PCLK_STORE(clk, 6, 0); 400 401 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], 402 BIT(1), 0); 403 PRCC_PCLK_STORE(clk, 6, 1); 404 405 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], 406 BIT(2), 0); 407 PRCC_PCLK_STORE(clk, 6, 2); 408 409 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], 410 BIT(3), 0); 411 PRCC_PCLK_STORE(clk, 6, 3); 412 413 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], 414 BIT(4), 0); 415 PRCC_PCLK_STORE(clk, 6, 4); 416 417 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], 418 BIT(5), 0); 419 PRCC_PCLK_STORE(clk, 6, 5); 420 421 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], 422 BIT(6), 0); 423 PRCC_PCLK_STORE(clk, 6, 6); 424 425 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], 426 BIT(7), 0); 427 PRCC_PCLK_STORE(clk, 6, 7); 428 429 /* PRCC K-clocks 430 * 431 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled 432 * by enabling just the K-clock, even if it is not a valid parent to 433 * the K-clock. Until drivers get fixed we might need some kind of 434 * "parent muxed join". 435 */ 436 437 /* Periph1 */ 438 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", 439 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); 440 PRCC_KCLK_STORE(clk, 1, 0); 441 442 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", 443 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); 444 PRCC_KCLK_STORE(clk, 1, 1); 445 446 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", 447 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); 448 PRCC_KCLK_STORE(clk, 1, 2); 449 450 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", 451 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); 452 PRCC_KCLK_STORE(clk, 1, 3); 453 454 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", 455 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); 456 PRCC_KCLK_STORE(clk, 1, 4); 457 458 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", 459 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); 460 PRCC_KCLK_STORE(clk, 1, 5); 461 462 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", 463 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); 464 PRCC_KCLK_STORE(clk, 1, 6); 465 466 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", 467 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); 468 PRCC_KCLK_STORE(clk, 1, 8); 469 470 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", 471 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); 472 PRCC_KCLK_STORE(clk, 1, 9); 473 474 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", 475 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); 476 PRCC_KCLK_STORE(clk, 1, 10); 477 478 /* Periph2 */ 479 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", 480 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); 481 PRCC_KCLK_STORE(clk, 2, 0); 482 483 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", 484 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); 485 PRCC_KCLK_STORE(clk, 2, 2); 486 487 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", 488 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); 489 PRCC_KCLK_STORE(clk, 2, 3); 490 491 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", 492 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); 493 PRCC_KCLK_STORE(clk, 2, 4); 494 495 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", 496 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); 497 PRCC_KCLK_STORE(clk, 2, 5); 498 499 /* Note that rate is received from parent. */ 500 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", 501 bases[CLKRST2_INDEX], BIT(6), 502 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 503 PRCC_KCLK_STORE(clk, 2, 6); 504 505 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", 506 bases[CLKRST2_INDEX], BIT(7), 507 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 508 PRCC_KCLK_STORE(clk, 2, 7); 509 510 /* Periph3 */ 511 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", 512 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); 513 PRCC_KCLK_STORE(clk, 3, 1); 514 515 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", 516 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); 517 PRCC_KCLK_STORE(clk, 3, 2); 518 519 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", 520 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); 521 PRCC_KCLK_STORE(clk, 3, 3); 522 523 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", 524 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); 525 PRCC_KCLK_STORE(clk, 3, 4); 526 527 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 528 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); 529 PRCC_KCLK_STORE(clk, 3, 5); 530 531 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 532 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); 533 PRCC_KCLK_STORE(clk, 3, 6); 534 535 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", 536 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); 537 PRCC_KCLK_STORE(clk, 3, 7); 538 539 /* Periph6 */ 540 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 541 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); 542 PRCC_KCLK_STORE(clk, 6, 0); 543 544 for_each_child_of_node(np, child) { 545 static struct clk_onecell_data clk_data; 546 547 if (of_node_name_eq(child, "prcmu-clock")) { 548 clk_data.clks = prcmu_clk; 549 clk_data.clk_num = ARRAY_SIZE(prcmu_clk); 550 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data); 551 } 552 if (of_node_name_eq(child, "prcc-periph-clock")) 553 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk); 554 555 if (of_node_name_eq(child, "prcc-kernel-clock")) 556 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk); 557 558 if (of_node_name_eq(child, "rtc32k-clock")) 559 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk); 560 561 if (of_node_name_eq(child, "smp-twd-clock")) 562 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk); 563 } 564 } 565 CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init); 566