1 /* 2 * Clock definitions for u8500 platform. 3 * 4 * Copyright (C) 2012 ST-Ericsson SA 5 * Author: Ulf Hansson <ulf.hansson@linaro.org> 6 * 7 * License terms: GNU General Public License (GPL) version 2 8 */ 9 10 #include <linux/of.h> 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/mfd/dbx500-prcmu.h> 15 #include <linux/platform_data/clk-ux500.h> 16 #include "clk.h" 17 18 #define PRCC_NUM_PERIPH_CLUSTERS 6 19 #define PRCC_PERIPHS_PER_CLUSTER 32 20 21 static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; 22 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 23 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 24 25 #define PRCC_SHOW(clk, base, bit) \ 26 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] 27 #define PRCC_PCLK_STORE(clk, base, bit) \ 28 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 29 #define PRCC_KCLK_STORE(clk, base, bit) \ 30 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 31 32 struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, void *data) 33 { 34 struct clk **clk_data = data; 35 unsigned int base, bit; 36 37 if (clkspec->args_count != 2) 38 return ERR_PTR(-EINVAL); 39 40 base = clkspec->args[0]; 41 bit = clkspec->args[1]; 42 43 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { 44 pr_err("%s: invalid PRCC base %d\n", __func__, base); 45 return ERR_PTR(-EINVAL); 46 } 47 48 return PRCC_SHOW(clk_data, base, bit); 49 } 50 51 static const struct of_device_id u8500_clk_of_match[] = { 52 { .compatible = "stericsson,u8500-clks", }, 53 { }, 54 }; 55 56 void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 57 u32 clkrst5_base, u32 clkrst6_base) 58 { 59 struct prcmu_fw_version *fw_version; 60 struct device_node *np = NULL; 61 struct device_node *child = NULL; 62 const char *sgaclk_parent = NULL; 63 struct clk *clk, *rtc_clk, *twd_clk; 64 65 if (of_have_populated_dt()) 66 np = of_find_matching_node(NULL, u8500_clk_of_match); 67 if (!np) { 68 pr_err("Either DT or U8500 Clock node not found\n"); 69 return; 70 } 71 72 /* Clock sources */ 73 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, 74 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 75 prcmu_clk[PRCMU_PLLSOC0] = clk; 76 77 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, 78 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 79 prcmu_clk[PRCMU_PLLSOC1] = clk; 80 81 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, 82 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 83 prcmu_clk[PRCMU_PLLDDR] = clk; 84 85 /* FIXME: Add sys, ulp and int clocks here. */ 86 87 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", 88 CLK_IS_ROOT|CLK_IGNORE_UNUSED, 89 32768); 90 91 /* PRCMU clocks */ 92 fw_version = prcmu_get_fw_version(); 93 if (fw_version != NULL) { 94 switch (fw_version->project) { 95 case PRCMU_FW_PROJECT_U8500_C2: 96 case PRCMU_FW_PROJECT_U8520: 97 case PRCMU_FW_PROJECT_U8420: 98 sgaclk_parent = "soc0_pll"; 99 break; 100 default: 101 break; 102 } 103 } 104 105 if (sgaclk_parent) 106 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, 107 PRCMU_SGACLK, 0); 108 else 109 clk = clk_reg_prcmu_gate("sgclk", NULL, 110 PRCMU_SGACLK, CLK_IS_ROOT); 111 prcmu_clk[PRCMU_SGACLK] = clk; 112 113 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); 114 prcmu_clk[PRCMU_UARTCLK] = clk; 115 116 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); 117 prcmu_clk[PRCMU_MSP02CLK] = clk; 118 119 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); 120 prcmu_clk[PRCMU_MSP1CLK] = clk; 121 122 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); 123 prcmu_clk[PRCMU_I2CCLK] = clk; 124 125 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); 126 prcmu_clk[PRCMU_SLIMCLK] = clk; 127 128 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); 129 prcmu_clk[PRCMU_PER1CLK] = clk; 130 131 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); 132 prcmu_clk[PRCMU_PER2CLK] = clk; 133 134 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); 135 prcmu_clk[PRCMU_PER3CLK] = clk; 136 137 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); 138 prcmu_clk[PRCMU_PER5CLK] = clk; 139 140 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); 141 prcmu_clk[PRCMU_PER6CLK] = clk; 142 143 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); 144 prcmu_clk[PRCMU_PER7CLK] = clk; 145 146 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, 147 CLK_IS_ROOT|CLK_SET_RATE_GATE); 148 prcmu_clk[PRCMU_LCDCLK] = clk; 149 150 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); 151 prcmu_clk[PRCMU_BMLCLK] = clk; 152 153 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, 154 CLK_IS_ROOT|CLK_SET_RATE_GATE); 155 prcmu_clk[PRCMU_HSITXCLK] = clk; 156 157 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, 158 CLK_IS_ROOT|CLK_SET_RATE_GATE); 159 prcmu_clk[PRCMU_HSIRXCLK] = clk; 160 161 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, 162 CLK_IS_ROOT|CLK_SET_RATE_GATE); 163 prcmu_clk[PRCMU_HDMICLK] = clk; 164 165 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); 166 prcmu_clk[PRCMU_APEATCLK] = clk; 167 168 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, 169 CLK_IS_ROOT); 170 prcmu_clk[PRCMU_APETRACECLK] = clk; 171 172 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); 173 prcmu_clk[PRCMU_MCDECLK] = clk; 174 175 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 176 CLK_IS_ROOT); 177 prcmu_clk[PRCMU_IPI2CCLK] = clk; 178 179 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 180 CLK_IS_ROOT); 181 prcmu_clk[PRCMU_DSIALTCLK] = clk; 182 183 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); 184 prcmu_clk[PRCMU_DMACLK] = clk; 185 186 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); 187 prcmu_clk[PRCMU_B2R2CLK] = clk; 188 189 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, 190 CLK_IS_ROOT|CLK_SET_RATE_GATE); 191 prcmu_clk[PRCMU_TVCLK] = clk; 192 193 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); 194 prcmu_clk[PRCMU_SSPCLK] = clk; 195 196 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); 197 prcmu_clk[PRCMU_RNGCLK] = clk; 198 199 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); 200 prcmu_clk[PRCMU_UICCCLK] = clk; 201 202 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); 203 prcmu_clk[PRCMU_TIMCLK] = clk; 204 205 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, 206 100000000, 207 CLK_IS_ROOT|CLK_SET_RATE_GATE); 208 prcmu_clk[PRCMU_SDMMCCLK] = clk; 209 210 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", 211 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); 212 prcmu_clk[PRCMU_PLLDSI] = clk; 213 214 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", 215 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); 216 prcmu_clk[PRCMU_DSI0CLK] = clk; 217 218 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", 219 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); 220 prcmu_clk[PRCMU_DSI1CLK] = clk; 221 222 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", 223 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); 224 prcmu_clk[PRCMU_DSI0ESCCLK] = clk; 225 226 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", 227 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); 228 prcmu_clk[PRCMU_DSI1ESCCLK] = clk; 229 230 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", 231 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); 232 prcmu_clk[PRCMU_DSI2ESCCLK] = clk; 233 234 clk = clk_reg_prcmu_scalable_rate("armss", NULL, 235 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); 236 prcmu_clk[PRCMU_ARMSS] = clk; 237 238 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", 239 CLK_IGNORE_UNUSED, 1, 2); 240 241 /* 242 * FIXME: Add special handled PRCMU clocks here: 243 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. 244 * 2. ab9540_clkout1yuv, see clkout0yuv 245 */ 246 247 /* PRCC P-clocks */ 248 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, 249 BIT(0), 0); 250 PRCC_PCLK_STORE(clk, 1, 0); 251 252 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, 253 BIT(1), 0); 254 PRCC_PCLK_STORE(clk, 1, 1); 255 256 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, 257 BIT(2), 0); 258 PRCC_PCLK_STORE(clk, 1, 2); 259 260 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, 261 BIT(3), 0); 262 PRCC_PCLK_STORE(clk, 1, 3); 263 264 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, 265 BIT(4), 0); 266 PRCC_PCLK_STORE(clk, 1, 4); 267 268 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, 269 BIT(5), 0); 270 PRCC_PCLK_STORE(clk, 1, 5); 271 272 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, 273 BIT(6), 0); 274 PRCC_PCLK_STORE(clk, 1, 6); 275 276 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, 277 BIT(7), 0); 278 PRCC_PCLK_STORE(clk, 1, 7); 279 280 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, 281 BIT(8), 0); 282 PRCC_PCLK_STORE(clk, 1, 8); 283 284 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, 285 BIT(9), 0); 286 PRCC_PCLK_STORE(clk, 1, 9); 287 288 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, 289 BIT(10), 0); 290 PRCC_PCLK_STORE(clk, 1, 10); 291 292 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, 293 BIT(11), 0); 294 PRCC_PCLK_STORE(clk, 1, 11); 295 296 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, 297 BIT(0), 0); 298 PRCC_PCLK_STORE(clk, 2, 0); 299 300 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, 301 BIT(1), 0); 302 PRCC_PCLK_STORE(clk, 2, 1); 303 304 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, 305 BIT(2), 0); 306 PRCC_PCLK_STORE(clk, 2, 2); 307 308 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, 309 BIT(3), 0); 310 PRCC_PCLK_STORE(clk, 2, 3); 311 312 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, 313 BIT(4), 0); 314 PRCC_PCLK_STORE(clk, 2, 4); 315 316 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, 317 BIT(5), 0); 318 PRCC_PCLK_STORE(clk, 2, 5); 319 320 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, 321 BIT(6), 0); 322 PRCC_PCLK_STORE(clk, 2, 6); 323 324 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, 325 BIT(7), 0); 326 PRCC_PCLK_STORE(clk, 2, 7); 327 328 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, 329 BIT(8), 0); 330 PRCC_PCLK_STORE(clk, 2, 8); 331 332 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, 333 BIT(9), 0); 334 PRCC_PCLK_STORE(clk, 2, 9); 335 336 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, 337 BIT(10), 0); 338 PRCC_PCLK_STORE(clk, 2, 10); 339 340 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, 341 BIT(11), 0); 342 PRCC_PCLK_STORE(clk, 2, 11); 343 344 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, 345 BIT(12), 0); 346 PRCC_PCLK_STORE(clk, 2, 12); 347 348 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, 349 BIT(0), 0); 350 PRCC_PCLK_STORE(clk, 3, 0); 351 352 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, 353 BIT(1), 0); 354 PRCC_PCLK_STORE(clk, 3, 1); 355 356 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, 357 BIT(2), 0); 358 PRCC_PCLK_STORE(clk, 3, 2); 359 360 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, 361 BIT(3), 0); 362 PRCC_PCLK_STORE(clk, 3, 3); 363 364 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, 365 BIT(4), 0); 366 PRCC_PCLK_STORE(clk, 3, 4); 367 368 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, 369 BIT(5), 0); 370 PRCC_PCLK_STORE(clk, 3, 5); 371 372 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, 373 BIT(6), 0); 374 PRCC_PCLK_STORE(clk, 3, 6); 375 376 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, 377 BIT(7), 0); 378 PRCC_PCLK_STORE(clk, 3, 7); 379 380 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, 381 BIT(8), 0); 382 PRCC_PCLK_STORE(clk, 3, 8); 383 384 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, 385 BIT(0), 0); 386 PRCC_PCLK_STORE(clk, 5, 0); 387 388 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, 389 BIT(1), 0); 390 PRCC_PCLK_STORE(clk, 5, 1); 391 392 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, 393 BIT(0), 0); 394 PRCC_PCLK_STORE(clk, 6, 0); 395 396 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, 397 BIT(1), 0); 398 PRCC_PCLK_STORE(clk, 6, 1); 399 400 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, 401 BIT(2), 0); 402 PRCC_PCLK_STORE(clk, 6, 2); 403 404 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, 405 BIT(3), 0); 406 PRCC_PCLK_STORE(clk, 6, 3); 407 408 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, 409 BIT(4), 0); 410 PRCC_PCLK_STORE(clk, 6, 4); 411 412 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, 413 BIT(5), 0); 414 PRCC_PCLK_STORE(clk, 6, 5); 415 416 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, 417 BIT(6), 0); 418 PRCC_PCLK_STORE(clk, 6, 6); 419 420 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, 421 BIT(7), 0); 422 PRCC_PCLK_STORE(clk, 6, 7); 423 424 /* PRCC K-clocks 425 * 426 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled 427 * by enabling just the K-clock, even if it is not a valid parent to 428 * the K-clock. Until drivers get fixed we might need some kind of 429 * "parent muxed join". 430 */ 431 432 /* Periph1 */ 433 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", 434 clkrst1_base, BIT(0), CLK_SET_RATE_GATE); 435 PRCC_KCLK_STORE(clk, 1, 0); 436 437 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", 438 clkrst1_base, BIT(1), CLK_SET_RATE_GATE); 439 PRCC_KCLK_STORE(clk, 1, 1); 440 441 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", 442 clkrst1_base, BIT(2), CLK_SET_RATE_GATE); 443 PRCC_KCLK_STORE(clk, 1, 2); 444 445 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", 446 clkrst1_base, BIT(3), CLK_SET_RATE_GATE); 447 PRCC_KCLK_STORE(clk, 1, 3); 448 449 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", 450 clkrst1_base, BIT(4), CLK_SET_RATE_GATE); 451 PRCC_KCLK_STORE(clk, 1, 4); 452 453 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", 454 clkrst1_base, BIT(5), CLK_SET_RATE_GATE); 455 PRCC_KCLK_STORE(clk, 1, 5); 456 457 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", 458 clkrst1_base, BIT(6), CLK_SET_RATE_GATE); 459 PRCC_KCLK_STORE(clk, 1, 6); 460 461 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", 462 clkrst1_base, BIT(8), CLK_SET_RATE_GATE); 463 PRCC_KCLK_STORE(clk, 1, 8); 464 465 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", 466 clkrst1_base, BIT(9), CLK_SET_RATE_GATE); 467 PRCC_KCLK_STORE(clk, 1, 9); 468 469 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", 470 clkrst1_base, BIT(10), CLK_SET_RATE_GATE); 471 PRCC_KCLK_STORE(clk, 1, 10); 472 473 /* Periph2 */ 474 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", 475 clkrst2_base, BIT(0), CLK_SET_RATE_GATE); 476 PRCC_KCLK_STORE(clk, 2, 0); 477 478 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", 479 clkrst2_base, BIT(2), CLK_SET_RATE_GATE); 480 PRCC_KCLK_STORE(clk, 2, 2); 481 482 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", 483 clkrst2_base, BIT(3), CLK_SET_RATE_GATE); 484 PRCC_KCLK_STORE(clk, 2, 3); 485 486 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", 487 clkrst2_base, BIT(4), CLK_SET_RATE_GATE); 488 PRCC_KCLK_STORE(clk, 2, 4); 489 490 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", 491 clkrst2_base, BIT(5), CLK_SET_RATE_GATE); 492 PRCC_KCLK_STORE(clk, 2, 5); 493 494 /* Note that rate is received from parent. */ 495 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", 496 clkrst2_base, BIT(6), 497 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 498 PRCC_KCLK_STORE(clk, 2, 6); 499 500 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", 501 clkrst2_base, BIT(7), 502 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 503 PRCC_KCLK_STORE(clk, 2, 7); 504 505 /* Periph3 */ 506 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", 507 clkrst3_base, BIT(1), CLK_SET_RATE_GATE); 508 PRCC_KCLK_STORE(clk, 3, 1); 509 510 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", 511 clkrst3_base, BIT(2), CLK_SET_RATE_GATE); 512 PRCC_KCLK_STORE(clk, 3, 2); 513 514 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", 515 clkrst3_base, BIT(3), CLK_SET_RATE_GATE); 516 PRCC_KCLK_STORE(clk, 3, 3); 517 518 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", 519 clkrst3_base, BIT(4), CLK_SET_RATE_GATE); 520 PRCC_KCLK_STORE(clk, 3, 4); 521 522 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 523 clkrst3_base, BIT(5), CLK_SET_RATE_GATE); 524 PRCC_KCLK_STORE(clk, 3, 5); 525 526 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 527 clkrst3_base, BIT(6), CLK_SET_RATE_GATE); 528 PRCC_KCLK_STORE(clk, 3, 6); 529 530 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", 531 clkrst3_base, BIT(7), CLK_SET_RATE_GATE); 532 PRCC_KCLK_STORE(clk, 3, 7); 533 534 /* Periph6 */ 535 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 536 clkrst6_base, BIT(0), CLK_SET_RATE_GATE); 537 PRCC_KCLK_STORE(clk, 6, 0); 538 539 for_each_child_of_node(np, child) { 540 static struct clk_onecell_data clk_data; 541 542 if (!of_node_cmp(child->name, "prcmu-clock")) { 543 clk_data.clks = prcmu_clk; 544 clk_data.clk_num = ARRAY_SIZE(prcmu_clk); 545 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data); 546 } 547 if (!of_node_cmp(child->name, "prcc-periph-clock")) 548 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk); 549 550 if (!of_node_cmp(child->name, "prcc-kernel-clock")) 551 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk); 552 553 if (!of_node_cmp(child->name, "rtc32k-clock")) 554 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk); 555 556 if (!of_node_cmp(child->name, "smp-twd-clock")) 557 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk); 558 } 559 } 560