1*b14cbdfdSLinus Walleij /* SPDX-License-Identifier: GPL-2.0-only */ 2*b14cbdfdSLinus Walleij 3*b14cbdfdSLinus Walleij #ifndef __RESET_PRCC_H 4*b14cbdfdSLinus Walleij #define __RESET_PRCC_H 5*b14cbdfdSLinus Walleij 6*b14cbdfdSLinus Walleij #include <linux/reset-controller.h> 7*b14cbdfdSLinus Walleij #include <linux/io.h> 8*b14cbdfdSLinus Walleij 9*b14cbdfdSLinus Walleij /** 10*b14cbdfdSLinus Walleij * struct u8500_prcc_reset - U8500 PRCC reset controller state 11*b14cbdfdSLinus Walleij * @rcdev: reset controller device 12*b14cbdfdSLinus Walleij * @phy_base: the physical base address for each PRCC block 13*b14cbdfdSLinus Walleij * @base: the remapped PRCC bases 14*b14cbdfdSLinus Walleij */ 15*b14cbdfdSLinus Walleij struct u8500_prcc_reset { 16*b14cbdfdSLinus Walleij struct reset_controller_dev rcdev; 17*b14cbdfdSLinus Walleij u32 phy_base[CLKRST_MAX]; 18*b14cbdfdSLinus Walleij void __iomem *base[CLKRST_MAX]; 19*b14cbdfdSLinus Walleij }; 20*b14cbdfdSLinus Walleij 21*b14cbdfdSLinus Walleij void u8500_prcc_reset_init(struct device_node *np, struct u8500_prcc_reset *ur); 22*b14cbdfdSLinus Walleij 23*b14cbdfdSLinus Walleij #endif 24