1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/stddef.h> 17 18 #include "clk-uniphier.h" 19 20 #define UNIPHIER_LD4_SYS_CLK_SD \ 21 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \ 22 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2) 23 24 #define UNIPHIER_PRO5_SYS_CLK_SD \ 25 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \ 26 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18) 27 28 #define UNIPHIER_LD20_SYS_CLK_SD \ 29 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ 30 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) 31 32 #define UNIPHIER_LD4_SYS_CLK_NAND(idx) \ 33 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \ 34 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2) 35 36 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \ 37 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \ 38 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2) 39 40 #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ 41 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \ 42 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0) 43 44 #define UNIPHIER_SYS_CLK_NAND_4X(idx) \ 45 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1) 46 47 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \ 48 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2) 49 50 #define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \ 51 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10) 52 53 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \ 54 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8) 55 56 #define UNIPHIER_LD11_SYS_CLK_HSC(idx) \ 57 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9) 58 59 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \ 60 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6) 61 62 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \ 63 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch)) 64 65 #define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \ 66 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \ 67 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13) 68 69 #define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \ 70 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \ 71 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13) 72 73 #define UNIPHIER_LD11_SYS_CLK_AIO(idx) \ 74 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \ 75 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0) 76 77 #define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \ 78 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \ 79 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1) 80 81 #define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \ 82 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \ 83 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2) 84 85 #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \ 86 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12) 87 88 #define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \ 89 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6) 90 91 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = { 92 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ 93 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ 94 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */ 95 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ 96 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), 97 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 98 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32), 99 UNIPHIER_LD4_SYS_CLK_NAND(2), 100 UNIPHIER_SYS_CLK_NAND_4X(3), 101 UNIPHIER_LD4_SYS_CLK_SD, 102 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 103 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 104 { /* sentinel */ } 105 }; 106 107 const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { 108 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 109 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 110 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */ 111 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 112 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */ 113 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8), 114 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32), 115 UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32), 116 UNIPHIER_LD4_SYS_CLK_NAND(2), 117 UNIPHIER_SYS_CLK_NAND_4X(3), 118 UNIPHIER_LD4_SYS_CLK_SD, 119 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 120 UNIPHIER_PRO4_SYS_CLK_ETHER(6), 121 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5), 122 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */ 123 UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0), 124 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */ 125 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 126 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 127 UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12), 128 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1), 129 UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1), 130 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18), 131 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19), 132 UNIPHIER_PRO4_SYS_CLK_AIO(40), 133 { /* sentinel */ } 134 }; 135 136 const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { 137 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 138 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 139 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 140 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20), 141 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 142 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32), 143 UNIPHIER_LD4_SYS_CLK_NAND(2), 144 UNIPHIER_SYS_CLK_NAND_4X(3), 145 UNIPHIER_LD4_SYS_CLK_SD, 146 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 147 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 148 { /* sentinel */ } 149 }; 150 151 const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { 152 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ 153 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ 154 UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */ 155 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), 156 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 157 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48), 158 UNIPHIER_PRO5_SYS_CLK_NAND(2), 159 UNIPHIER_SYS_CLK_NAND_4X(3), 160 UNIPHIER_PRO5_SYS_CLK_SD, 161 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */ 162 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */ 163 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 164 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 165 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2), 166 UNIPHIER_PRO5_SYS_CLK_AIO(40), 167 { /* sentinel */ } 168 }; 169 170 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 171 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */ 172 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27), 173 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 174 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48), 175 UNIPHIER_PRO5_SYS_CLK_NAND(2), 176 UNIPHIER_SYS_CLK_NAND_4X(3), 177 UNIPHIER_PRO5_SYS_CLK_SD, 178 UNIPHIER_PRO4_SYS_CLK_ETHER(6), 179 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */ 180 /* GIO is always clock-enabled: no function for 0x2104 bit6 */ 181 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 182 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 183 /* The document mentions 0x2104 bit 18, but not functional */ 184 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19), 185 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1), 186 UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1), 187 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20), 188 UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1), 189 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22), 190 UNIPHIER_PRO5_SYS_CLK_AIO(40), 191 { /* sentinel */ } 192 }; 193 194 const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { 195 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */ 196 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */ 197 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 198 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */ 199 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 200 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 201 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40), 202 UNIPHIER_LD11_SYS_CLK_NAND(2), 203 UNIPHIER_SYS_CLK_NAND_4X(3), 204 UNIPHIER_LD11_SYS_CLK_EMMC(4), 205 /* Index 5 reserved for eMMC PHY */ 206 UNIPHIER_LD11_SYS_CLK_ETHER(6), 207 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ 208 UNIPHIER_LD11_SYS_CLK_HSC(9), 209 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), 210 UNIPHIER_LD11_SYS_CLK_AIO(40), 211 UNIPHIER_LD11_SYS_CLK_EVEA(41), 212 UNIPHIER_LD11_SYS_CLK_EXIV(42), 213 /* CPU gears */ 214 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 215 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), 216 UNIPHIER_CLK_DIV3("spll", 3, 4, 8), 217 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */ 218 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 219 "cpll/2", "spll/4", "cpll/3", "spll/3", 220 "spll/4", "spll/8", "cpll/4", "cpll/8"), 221 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 222 "mpll/2", "spll/4", "mpll/3", "spll/3", 223 "spll/4", "spll/8", "mpll/4", "mpll/8"), 224 { /* sentinel */ } 225 }; 226 227 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 228 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */ 229 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */ 230 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */ 231 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 232 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */ 233 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */ 234 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 235 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 236 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40), 237 UNIPHIER_LD11_SYS_CLK_NAND(2), 238 UNIPHIER_SYS_CLK_NAND_4X(3), 239 UNIPHIER_LD11_SYS_CLK_EMMC(4), 240 /* Index 5 reserved for eMMC PHY */ 241 UNIPHIER_LD20_SYS_CLK_SD, 242 UNIPHIER_LD11_SYS_CLK_ETHER(6), 243 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */ 244 UNIPHIER_LD11_SYS_CLK_HSC(9), 245 /* GIO is always clock-enabled: no function for 0x210c bit5 */ 246 /* 247 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15. 248 * We do not use bit 15 here. 249 */ 250 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14), 251 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12), 252 UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13), 253 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1), 254 UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1), 255 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4), 256 UNIPHIER_LD11_SYS_CLK_AIO(40), 257 UNIPHIER_LD11_SYS_CLK_EVEA(41), 258 UNIPHIER_LD11_SYS_CLK_EXIV(42), 259 /* CPU gears */ 260 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 261 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), 262 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), 263 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8, 264 "cpll/2", "spll/2", "cpll/3", "spll/3", 265 "spll/4", "spll/8", "cpll/4", "cpll/8"), 266 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 267 "cpll/2", "spll/2", "cpll/3", "spll/3", 268 "spll/4", "spll/8", "cpll/4", "cpll/8"), 269 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 270 "s2pll/2", "spll/2", "s2pll/3", "spll/3", 271 "spll/4", "spll/8", "s2pll/4", "s2pll/8"), 272 { /* sentinel */ } 273 }; 274 275 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { 276 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */ 277 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 278 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */ 279 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 280 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 281 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40), 282 UNIPHIER_LD20_SYS_CLK_SD, 283 UNIPHIER_LD11_SYS_CLK_NAND(2), 284 UNIPHIER_SYS_CLK_NAND_4X(3), 285 UNIPHIER_LD11_SYS_CLK_EMMC(4), 286 UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9), 287 UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10), 288 UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */ 289 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */ 290 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */ 291 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16), 292 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18), 293 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20), 294 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17), 295 UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19), 296 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3), 297 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7), 298 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8), 299 UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21), 300 /* CPU gears */ 301 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 302 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), 303 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), 304 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 305 "cpll/2", "spll/2", "cpll/3", "spll/3", 306 "spll/4", "spll/8", "cpll/4", "cpll/8"), 307 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 308 "s2pll/2", "spll/2", "s2pll/3", "spll/3", 309 "spll/4", "spll/8", "s2pll/4", "s2pll/8"), 310 { /* sentinel */ } 311 }; 312