1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/stddef.h> 17 18 #include "clk-uniphier.h" 19 20 #define UNIPHIER_SLD3_SYS_CLK_SD \ 21 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \ 22 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2) 23 24 #define UNIPHIER_PRO5_SYS_CLK_SD \ 25 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \ 26 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18) 27 28 #define UNIPHIER_LD20_SYS_CLK_SD \ 29 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ 30 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) 31 32 /* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ 33 #define UNIPHIER_SLD3_SYS_CLK_NAND(idx) \ 34 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \ 35 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2) 36 37 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \ 38 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \ 39 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2) 40 41 #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ 42 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \ 43 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0) 44 45 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \ 46 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2) 47 48 #define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \ 49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10) 50 51 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \ 52 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8) 53 54 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \ 55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6) 56 57 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \ 58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch)) 59 60 const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = { 61 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ 62 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ 63 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */ 64 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ 65 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), 66 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 67 UNIPHIER_SLD3_SYS_CLK_NAND(2), 68 UNIPHIER_SLD3_SYS_CLK_SD, 69 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 70 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), 71 { /* sentinel */ } 72 }; 73 74 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = { 75 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ 76 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ 77 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */ 78 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ 79 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), 80 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 81 UNIPHIER_SLD3_SYS_CLK_NAND(2), 82 UNIPHIER_SLD3_SYS_CLK_SD, 83 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 84 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 85 { /* sentinel */ } 86 }; 87 88 const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { 89 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 90 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 91 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */ 92 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 93 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8), 94 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32), 95 UNIPHIER_SLD3_SYS_CLK_NAND(2), 96 UNIPHIER_SLD3_SYS_CLK_SD, 97 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 98 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */ 99 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */ 100 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 101 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 102 { /* sentinel */ } 103 }; 104 105 const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { 106 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 107 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 108 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 109 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20), 110 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 111 UNIPHIER_SLD3_SYS_CLK_NAND(2), 112 UNIPHIER_SLD3_SYS_CLK_SD, 113 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 114 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 115 { /* sentinel */ } 116 }; 117 118 const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { 119 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ 120 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ 121 UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ 122 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), 123 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 124 UNIPHIER_PRO5_SYS_CLK_NAND(2), 125 UNIPHIER_PRO5_SYS_CLK_SD, 126 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */ 127 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */ 128 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 129 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 130 { /* sentinel */ } 131 }; 132 133 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 134 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */ 135 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27), 136 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 137 UNIPHIER_PRO5_SYS_CLK_NAND(2), 138 UNIPHIER_PRO5_SYS_CLK_SD, 139 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */ 140 /* GIO is always clock-enabled: no function for 0x2104 bit6 */ 141 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 142 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 143 /* The document mentions 0x2104 bit 18, but not functional */ 144 UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19), 145 UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20), 146 { /* sentinel */ } 147 }; 148 149 const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { 150 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */ 151 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */ 152 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 153 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */ 154 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 155 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 156 UNIPHIER_LD11_SYS_CLK_NAND(2), 157 UNIPHIER_LD11_SYS_CLK_EMMC(4), 158 /* Index 5 reserved for eMMC PHY */ 159 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ 160 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), 161 /* CPU gears */ 162 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 163 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), 164 UNIPHIER_CLK_DIV3("spll", 3, 4, 8), 165 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */ 166 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 167 "cpll/2", "spll/4", "cpll/3", "spll/3", 168 "spll/4", "spll/8", "cpll/4", "cpll/8"), 169 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 170 "mpll/2", "spll/4", "mpll/3", "spll/3", 171 "spll/4", "spll/8", "mpll/4", "mpll/8"), 172 { /* sentinel */ } 173 }; 174 175 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 176 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */ 177 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */ 178 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */ 179 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 180 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */ 181 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */ 182 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 183 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 184 UNIPHIER_LD11_SYS_CLK_NAND(2), 185 UNIPHIER_LD11_SYS_CLK_EMMC(4), 186 /* Index 5 reserved for eMMC PHY */ 187 UNIPHIER_LD20_SYS_CLK_SD, 188 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */ 189 /* GIO is always clock-enabled: no function for 0x210c bit5 */ 190 /* 191 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15. 192 * We do not use bit 15 here. 193 */ 194 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14), 195 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12), 196 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), 197 /* CPU gears */ 198 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 199 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), 200 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), 201 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8, 202 "cpll/2", "spll/2", "cpll/3", "spll/3", 203 "spll/4", "spll/8", "cpll/4", "cpll/8"), 204 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 205 "cpll/2", "spll/2", "cpll/3", "spll/3", 206 "spll/4", "spll/8", "cpll/4", "cpll/8"), 207 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 208 "s2pll/2", "spll/2", "s2pll/3", "spll/3", 209 "spll/4", "spll/8", "s2pll/4", "s2pll/8"), 210 { /* sentinel */ } 211 }; 212