1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/stddef.h> 17 18 #include "clk-uniphier.h" 19 20 #define UNIPHIER_SLD3_SYS_CLK_SD \ 21 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \ 22 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2) 23 24 #define UNIPHIER_PRO5_SYS_CLK_SD \ 25 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \ 26 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18) 27 28 #define UNIPHIER_LD20_SYS_CLK_SD \ 29 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ 30 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) 31 32 #define UNIPHIER_SLD3_SYS_CLK_NAND(idx) \ 33 UNIPHIER_CLK_GATE("nand", (idx), NULL, 0x2104, 2) 34 35 #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ 36 UNIPHIER_CLK_GATE("nand", (idx), NULL, 0x210c, 0) 37 38 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \ 39 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2) 40 41 #define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \ 42 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10) 43 44 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \ 45 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8) 46 47 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \ 48 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6) 49 50 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \ 51 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch)) 52 53 const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = { 54 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ 55 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ 56 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */ 57 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ 58 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), 59 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 60 UNIPHIER_SLD3_SYS_CLK_NAND(2), 61 UNIPHIER_SLD3_SYS_CLK_SD, 62 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 63 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), 64 { /* sentinel */ } 65 }; 66 67 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = { 68 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ 69 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ 70 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */ 71 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ 72 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), 73 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 74 UNIPHIER_SLD3_SYS_CLK_NAND(2), 75 UNIPHIER_SLD3_SYS_CLK_SD, 76 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 77 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 78 { /* sentinel */ } 79 }; 80 81 const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { 82 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 83 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 84 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */ 85 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 86 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8), 87 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32), 88 UNIPHIER_SLD3_SYS_CLK_NAND(2), 89 UNIPHIER_SLD3_SYS_CLK_SD, 90 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 91 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */ 92 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */ 93 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 94 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 95 { /* sentinel */ } 96 }; 97 98 const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { 99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 101 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 102 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20), 103 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 104 UNIPHIER_SLD3_SYS_CLK_NAND(2), 105 UNIPHIER_SLD3_SYS_CLK_SD, 106 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 107 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 108 { /* sentinel */ } 109 }; 110 111 const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { 112 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ 113 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ 114 UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ 115 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), 116 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 117 UNIPHIER_SLD3_SYS_CLK_NAND(2), 118 UNIPHIER_PRO5_SYS_CLK_SD, 119 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */ 120 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */ 121 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 122 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 123 { /* sentinel */ } 124 }; 125 126 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 127 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */ 128 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27), 129 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 130 UNIPHIER_SLD3_SYS_CLK_NAND(2), 131 UNIPHIER_PRO5_SYS_CLK_SD, 132 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */ 133 /* GIO is always clock-enabled: no function for 0x2104 bit6 */ 134 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 135 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 136 /* The document mentions 0x2104 bit 18, but not functional */ 137 UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19), 138 UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20), 139 { /* sentinel */ } 140 }; 141 142 const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { 143 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */ 144 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */ 145 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 146 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */ 147 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 148 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 149 UNIPHIER_LD11_SYS_CLK_NAND(2), 150 UNIPHIER_LD11_SYS_CLK_EMMC(4), 151 /* Index 5 reserved for eMMC PHY */ 152 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ 153 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), 154 /* CPU gears */ 155 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 156 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), 157 UNIPHIER_CLK_DIV3("spll", 3, 4, 8), 158 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */ 159 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 160 "cpll/2", "spll/4", "cpll/3", "spll/3", 161 "spll/4", "spll/8", "cpll/4", "cpll/8"), 162 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 163 "mpll/2", "spll/4", "mpll/3", "spll/3", 164 "spll/4", "spll/8", "mpll/4", "mpll/8"), 165 { /* sentinel */ } 166 }; 167 168 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 169 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */ 170 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */ 171 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */ 172 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 173 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */ 174 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */ 175 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 176 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 177 UNIPHIER_LD11_SYS_CLK_NAND(2), 178 UNIPHIER_LD11_SYS_CLK_EMMC(4), 179 /* Index 5 reserved for eMMC PHY */ 180 UNIPHIER_LD20_SYS_CLK_SD, 181 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */ 182 /* GIO is always clock-enabled: no function for 0x210c bit5 */ 183 /* 184 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15. 185 * We do not use bit 15 here. 186 */ 187 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14), 188 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12), 189 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), 190 /* CPU gears */ 191 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 192 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), 193 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), 194 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8, 195 "cpll/2", "spll/2", "cpll/3", "spll/3", 196 "spll/4", "spll/8", "cpll/4", "cpll/8"), 197 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 198 "cpll/2", "spll/2", "cpll/3", "spll/3", 199 "spll/4", "spll/8", "cpll/4", "cpll/8"), 200 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 201 "s2pll/2", "spll/2", "s2pll/3", "spll/3", 202 "spll/4", "spll/8", "s2pll/4", "s2pll/8"), 203 { /* sentinel */ } 204 }; 205