1 /* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License as 4 * published by the Free Software Foundation version 2. 5 * 6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 7 * kind, whether express or implied; without even the implied warranty 8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/math64.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/clk/ti.h> 21 22 #include "clock.h" 23 24 /* FAPLL Control Register PLL_CTRL */ 25 #define FAPLL_MAIN_MULT_N_SHIFT 16 26 #define FAPLL_MAIN_DIV_P_SHIFT 8 27 #define FAPLL_MAIN_LOCK BIT(7) 28 #define FAPLL_MAIN_PLLEN BIT(3) 29 #define FAPLL_MAIN_BP BIT(2) 30 #define FAPLL_MAIN_LOC_CTL BIT(0) 31 32 #define FAPLL_MAIN_MAX_MULT_N 0xffff 33 #define FAPLL_MAIN_MAX_DIV_P 0xff 34 #define FAPLL_MAIN_CLEAR_MASK \ 35 ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \ 36 (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \ 37 FAPLL_MAIN_LOC_CTL) 38 39 /* FAPLL powerdown register PWD */ 40 #define FAPLL_PWD_OFFSET 4 41 42 #define MAX_FAPLL_OUTPUTS 7 43 #define FAPLL_MAX_RETRIES 1000 44 45 #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw) 46 #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw) 47 48 /* The bypass bit is inverted on the ddr_pll.. */ 49 #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440) 50 51 /* 52 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 53 * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output. 54 */ 55 #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c) 56 #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8) 57 58 /* Synthesizer divider register */ 59 #define SYNTH_LDMDIV1 BIT(8) 60 61 /* Synthesizer frequency register */ 62 #define SYNTH_LDFREQ BIT(31) 63 64 #define SYNTH_PHASE_K 8 65 #define SYNTH_MAX_INT_DIV 0xf 66 #define SYNTH_MAX_DIV_M 0xff 67 68 struct fapll_data { 69 struct clk_hw hw; 70 void __iomem *base; 71 const char *name; 72 struct clk *clk_ref; 73 struct clk *clk_bypass; 74 struct clk_onecell_data outputs; 75 bool bypass_bit_inverted; 76 }; 77 78 struct fapll_synth { 79 struct clk_hw hw; 80 struct fapll_data *fd; 81 int index; 82 void __iomem *freq; 83 void __iomem *div; 84 const char *name; 85 struct clk *clk_pll; 86 }; 87 88 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd) 89 { 90 u32 v = readl_relaxed(fd->base); 91 92 if (fd->bypass_bit_inverted) 93 return !(v & FAPLL_MAIN_BP); 94 else 95 return !!(v & FAPLL_MAIN_BP); 96 } 97 98 static void ti_fapll_set_bypass(struct fapll_data *fd) 99 { 100 u32 v = readl_relaxed(fd->base); 101 102 if (fd->bypass_bit_inverted) 103 v &= ~FAPLL_MAIN_BP; 104 else 105 v |= FAPLL_MAIN_BP; 106 writel_relaxed(v, fd->base); 107 } 108 109 static void ti_fapll_clear_bypass(struct fapll_data *fd) 110 { 111 u32 v = readl_relaxed(fd->base); 112 113 if (fd->bypass_bit_inverted) 114 v |= FAPLL_MAIN_BP; 115 else 116 v &= ~FAPLL_MAIN_BP; 117 writel_relaxed(v, fd->base); 118 } 119 120 static int ti_fapll_wait_lock(struct fapll_data *fd) 121 { 122 int retries = FAPLL_MAX_RETRIES; 123 u32 v; 124 125 while ((v = readl_relaxed(fd->base))) { 126 if (v & FAPLL_MAIN_LOCK) 127 return 0; 128 129 if (retries-- <= 0) 130 break; 131 132 udelay(1); 133 } 134 135 pr_err("%s failed to lock\n", fd->name); 136 137 return -ETIMEDOUT; 138 } 139 140 static int ti_fapll_enable(struct clk_hw *hw) 141 { 142 struct fapll_data *fd = to_fapll(hw); 143 u32 v = readl_relaxed(fd->base); 144 145 v |= FAPLL_MAIN_PLLEN; 146 writel_relaxed(v, fd->base); 147 ti_fapll_wait_lock(fd); 148 149 return 0; 150 } 151 152 static void ti_fapll_disable(struct clk_hw *hw) 153 { 154 struct fapll_data *fd = to_fapll(hw); 155 u32 v = readl_relaxed(fd->base); 156 157 v &= ~FAPLL_MAIN_PLLEN; 158 writel_relaxed(v, fd->base); 159 } 160 161 static int ti_fapll_is_enabled(struct clk_hw *hw) 162 { 163 struct fapll_data *fd = to_fapll(hw); 164 u32 v = readl_relaxed(fd->base); 165 166 return v & FAPLL_MAIN_PLLEN; 167 } 168 169 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 170 unsigned long parent_rate) 171 { 172 struct fapll_data *fd = to_fapll(hw); 173 u32 fapll_n, fapll_p, v; 174 u64 rate; 175 176 if (ti_fapll_clock_is_bypass(fd)) 177 return parent_rate; 178 179 rate = parent_rate; 180 181 /* PLL pre-divider is P and multiplier is N */ 182 v = readl_relaxed(fd->base); 183 fapll_p = (v >> 8) & 0xff; 184 if (fapll_p) 185 do_div(rate, fapll_p); 186 fapll_n = v >> 16; 187 if (fapll_n) 188 rate *= fapll_n; 189 190 return rate; 191 } 192 193 static u8 ti_fapll_get_parent(struct clk_hw *hw) 194 { 195 struct fapll_data *fd = to_fapll(hw); 196 197 if (ti_fapll_clock_is_bypass(fd)) 198 return 1; 199 200 return 0; 201 } 202 203 static int ti_fapll_set_div_mult(unsigned long rate, 204 unsigned long parent_rate, 205 u32 *pre_div_p, u32 *mult_n) 206 { 207 /* 208 * So far no luck getting decent clock with PLL divider, 209 * PLL does not seem to lock and the signal does not look 210 * right. It seems the divider can only be used together 211 * with the multiplier? 212 */ 213 if (rate < parent_rate) { 214 pr_warn("FAPLL main divider rates unsupported\n"); 215 return -EINVAL; 216 } 217 218 *mult_n = rate / parent_rate; 219 if (*mult_n > FAPLL_MAIN_MAX_MULT_N) 220 return -EINVAL; 221 *pre_div_p = 1; 222 223 return 0; 224 } 225 226 static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate, 227 unsigned long *parent_rate) 228 { 229 u32 pre_div_p, mult_n; 230 int error; 231 232 if (!rate) 233 return -EINVAL; 234 235 error = ti_fapll_set_div_mult(rate, *parent_rate, 236 &pre_div_p, &mult_n); 237 if (error) 238 return error; 239 240 rate = *parent_rate / pre_div_p; 241 rate *= mult_n; 242 243 return rate; 244 } 245 246 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate, 247 unsigned long parent_rate) 248 { 249 struct fapll_data *fd = to_fapll(hw); 250 u32 pre_div_p, mult_n, v; 251 int error; 252 253 if (!rate) 254 return -EINVAL; 255 256 error = ti_fapll_set_div_mult(rate, parent_rate, 257 &pre_div_p, &mult_n); 258 if (error) 259 return error; 260 261 ti_fapll_set_bypass(fd); 262 v = readl_relaxed(fd->base); 263 v &= ~FAPLL_MAIN_CLEAR_MASK; 264 v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT; 265 v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT; 266 writel_relaxed(v, fd->base); 267 if (ti_fapll_is_enabled(hw)) 268 ti_fapll_wait_lock(fd); 269 ti_fapll_clear_bypass(fd); 270 271 return 0; 272 } 273 274 static const struct clk_ops ti_fapll_ops = { 275 .enable = ti_fapll_enable, 276 .disable = ti_fapll_disable, 277 .is_enabled = ti_fapll_is_enabled, 278 .recalc_rate = ti_fapll_recalc_rate, 279 .get_parent = ti_fapll_get_parent, 280 .round_rate = ti_fapll_round_rate, 281 .set_rate = ti_fapll_set_rate, 282 }; 283 284 static int ti_fapll_synth_enable(struct clk_hw *hw) 285 { 286 struct fapll_synth *synth = to_synth(hw); 287 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 288 289 v &= ~(1 << synth->index); 290 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 291 292 return 0; 293 } 294 295 static void ti_fapll_synth_disable(struct clk_hw *hw) 296 { 297 struct fapll_synth *synth = to_synth(hw); 298 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 299 300 v |= 1 << synth->index; 301 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 302 } 303 304 static int ti_fapll_synth_is_enabled(struct clk_hw *hw) 305 { 306 struct fapll_synth *synth = to_synth(hw); 307 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 308 309 return !(v & (1 << synth->index)); 310 } 311 312 /* 313 * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info 314 */ 315 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, 316 unsigned long parent_rate) 317 { 318 struct fapll_synth *synth = to_synth(hw); 319 u32 synth_div_m; 320 u64 rate; 321 322 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ 323 if (!synth->div) 324 return 32768; 325 326 /* 327 * PLL in bypass sets the synths in bypass mode too. The PLL rate 328 * can be also be set to 27MHz, so we can't use parent_rate to 329 * check for bypass mode. 330 */ 331 if (ti_fapll_clock_is_bypass(synth->fd)) 332 return parent_rate; 333 334 rate = parent_rate; 335 336 /* 337 * Synth frequency integer and fractional divider. 338 * Note that the phase output K is 8, so the result needs 339 * to be multiplied by SYNTH_PHASE_K. 340 */ 341 if (synth->freq) { 342 u32 v, synth_int_div, synth_frac_div, synth_div_freq; 343 344 v = readl_relaxed(synth->freq); 345 synth_int_div = (v >> 24) & 0xf; 346 synth_frac_div = v & 0xffffff; 347 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; 348 rate *= 10000000; 349 do_div(rate, synth_div_freq); 350 rate *= SYNTH_PHASE_K; 351 } 352 353 /* Synth post-divider M */ 354 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 355 356 return DIV_ROUND_UP_ULL(rate, synth_div_m); 357 } 358 359 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw, 360 unsigned long parent_rate) 361 { 362 struct fapll_synth *synth = to_synth(hw); 363 unsigned long current_rate, frac_rate; 364 u32 post_div_m; 365 366 current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate); 367 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 368 frac_rate = current_rate * post_div_m; 369 370 return frac_rate; 371 } 372 373 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth, 374 unsigned long rate, 375 unsigned long parent_rate) 376 { 377 u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v; 378 379 post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate); 380 post_div_m = post_div_m / SYNTH_MAX_INT_DIV; 381 if (post_div_m > SYNTH_MAX_DIV_M) 382 return -EINVAL; 383 if (!post_div_m) 384 post_div_m = 1; 385 386 for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) { 387 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate * 388 SYNTH_PHASE_K * 389 10000000, 390 rate * post_div_m); 391 synth_frac_div = synth_int_div % 10000000; 392 synth_int_div /= 10000000; 393 394 if (synth_int_div <= SYNTH_MAX_INT_DIV) 395 break; 396 } 397 398 if (synth_int_div > SYNTH_MAX_INT_DIV) 399 return -EINVAL; 400 401 v = readl_relaxed(synth->freq); 402 v &= ~0x1fffffff; 403 v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24; 404 v |= (synth_frac_div & 0xffffff); 405 v |= SYNTH_LDFREQ; 406 writel_relaxed(v, synth->freq); 407 408 return post_div_m; 409 } 410 411 static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate, 412 unsigned long *parent_rate) 413 { 414 struct fapll_synth *synth = to_synth(hw); 415 struct fapll_data *fd = synth->fd; 416 unsigned long r; 417 418 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 419 return -EINVAL; 420 421 /* Only post divider m available with no fractional divider? */ 422 if (!synth->freq) { 423 unsigned long frac_rate; 424 u32 synth_post_div_m; 425 426 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate); 427 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate); 428 r = DIV_ROUND_UP(frac_rate, synth_post_div_m); 429 goto out; 430 } 431 432 r = *parent_rate * SYNTH_PHASE_K; 433 if (rate > r) 434 goto out; 435 436 r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); 437 if (rate < r) 438 goto out; 439 440 r = rate; 441 out: 442 return r; 443 } 444 445 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate, 446 unsigned long parent_rate) 447 { 448 struct fapll_synth *synth = to_synth(hw); 449 struct fapll_data *fd = synth->fd; 450 unsigned long frac_rate, post_rate = 0; 451 u32 post_div_m = 0, v; 452 453 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 454 return -EINVAL; 455 456 /* Produce the rate with just post divider M? */ 457 frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate); 458 if (frac_rate < rate) { 459 if (!synth->freq) 460 return -EINVAL; 461 } else { 462 post_div_m = DIV_ROUND_UP(frac_rate, rate); 463 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M)) 464 post_rate = DIV_ROUND_UP(frac_rate, post_div_m); 465 if (!synth->freq && !post_rate) 466 return -EINVAL; 467 } 468 469 /* Need to recalculate the fractional divider? */ 470 if ((post_rate != rate) && synth->freq) 471 post_div_m = ti_fapll_synth_set_frac_rate(synth, 472 rate, 473 parent_rate); 474 475 v = readl_relaxed(synth->div); 476 v &= ~SYNTH_MAX_DIV_M; 477 v |= post_div_m; 478 v |= SYNTH_LDMDIV1; 479 writel_relaxed(v, synth->div); 480 481 return 0; 482 } 483 484 static const struct clk_ops ti_fapll_synt_ops = { 485 .enable = ti_fapll_synth_enable, 486 .disable = ti_fapll_synth_disable, 487 .is_enabled = ti_fapll_synth_is_enabled, 488 .recalc_rate = ti_fapll_synth_recalc_rate, 489 .round_rate = ti_fapll_synth_round_rate, 490 .set_rate = ti_fapll_synth_set_rate, 491 }; 492 493 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd, 494 void __iomem *freq, 495 void __iomem *div, 496 int index, 497 const char *name, 498 const char *parent, 499 struct clk *pll_clk) 500 { 501 struct clk_init_data *init; 502 struct fapll_synth *synth; 503 struct clk *clk = ERR_PTR(-ENOMEM); 504 505 init = kzalloc(sizeof(*init), GFP_KERNEL); 506 if (!init) 507 return ERR_PTR(-ENOMEM); 508 509 init->ops = &ti_fapll_synt_ops; 510 init->name = name; 511 init->parent_names = &parent; 512 init->num_parents = 1; 513 514 synth = kzalloc(sizeof(*synth), GFP_KERNEL); 515 if (!synth) 516 goto free; 517 518 synth->fd = fd; 519 synth->index = index; 520 synth->freq = freq; 521 synth->div = div; 522 synth->name = name; 523 synth->hw.init = init; 524 synth->clk_pll = pll_clk; 525 526 clk = clk_register(NULL, &synth->hw); 527 if (IS_ERR(clk)) { 528 pr_err("failed to register clock\n"); 529 goto free; 530 } 531 532 return clk; 533 534 free: 535 kfree(synth); 536 kfree(init); 537 538 return clk; 539 } 540 541 static void __init ti_fapll_setup(struct device_node *node) 542 { 543 struct fapll_data *fd; 544 struct clk_init_data *init = NULL; 545 const char *parent_name[2]; 546 struct clk *pll_clk; 547 const char *name; 548 int i; 549 550 fd = kzalloc(sizeof(*fd), GFP_KERNEL); 551 if (!fd) 552 return; 553 554 fd->outputs.clks = kzalloc(sizeof(struct clk *) * 555 MAX_FAPLL_OUTPUTS + 1, 556 GFP_KERNEL); 557 if (!fd->outputs.clks) 558 goto free; 559 560 init = kzalloc(sizeof(*init), GFP_KERNEL); 561 if (!init) 562 goto free; 563 564 init->ops = &ti_fapll_ops; 565 name = ti_dt_clk_name(node); 566 init->name = name; 567 568 init->num_parents = of_clk_get_parent_count(node); 569 if (init->num_parents != 2) { 570 pr_err("%pOFn must have two parents\n", node); 571 goto free; 572 } 573 574 of_clk_parent_fill(node, parent_name, 2); 575 init->parent_names = parent_name; 576 577 fd->clk_ref = of_clk_get(node, 0); 578 if (IS_ERR(fd->clk_ref)) { 579 pr_err("%pOFn could not get clk_ref\n", node); 580 goto free; 581 } 582 583 fd->clk_bypass = of_clk_get(node, 1); 584 if (IS_ERR(fd->clk_bypass)) { 585 pr_err("%pOFn could not get clk_bypass\n", node); 586 goto free; 587 } 588 589 fd->base = of_iomap(node, 0); 590 if (!fd->base) { 591 pr_err("%pOFn could not get IO base\n", node); 592 goto free; 593 } 594 595 if (fapll_is_ddr_pll(fd->base)) 596 fd->bypass_bit_inverted = true; 597 598 fd->name = name; 599 fd->hw.init = init; 600 601 /* Register the parent PLL */ 602 pll_clk = clk_register(NULL, &fd->hw); 603 if (IS_ERR(pll_clk)) 604 goto unmap; 605 606 fd->outputs.clks[0] = pll_clk; 607 fd->outputs.clk_num++; 608 609 /* 610 * Set up the child synthesizers starting at index 1 as the 611 * PLL output is at index 0. We need to check the clock-indices 612 * for numbering in case there are holes in the synth mapping, 613 * and then probe the synth register to see if it has a FREQ 614 * register available. 615 */ 616 for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) { 617 const char *output_name; 618 void __iomem *freq, *div; 619 struct clk *synth_clk; 620 int output_instance; 621 u32 v; 622 623 if (of_property_read_string_index(node, "clock-output-names", 624 i, &output_name)) 625 continue; 626 627 if (of_property_read_u32_index(node, "clock-indices", i, 628 &output_instance)) 629 output_instance = i; 630 631 freq = fd->base + (output_instance * 8); 632 div = freq + 4; 633 634 /* Check for hardwired audio_pll_clk1 */ 635 if (is_audio_pll_clk1(freq)) { 636 freq = NULL; 637 div = NULL; 638 } else { 639 /* Does the synthesizer have a FREQ register? */ 640 v = readl_relaxed(freq); 641 if (!v) 642 freq = NULL; 643 } 644 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, 645 output_name, name, pll_clk); 646 if (IS_ERR(synth_clk)) 647 continue; 648 649 fd->outputs.clks[output_instance] = synth_clk; 650 fd->outputs.clk_num++; 651 652 clk_register_clkdev(synth_clk, output_name, NULL); 653 } 654 655 /* Register the child synthesizers as the FAPLL outputs */ 656 of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs); 657 /* Add clock alias for the outputs */ 658 659 kfree(init); 660 661 return; 662 663 unmap: 664 iounmap(fd->base); 665 free: 666 if (fd->clk_bypass) 667 clk_put(fd->clk_bypass); 668 if (fd->clk_ref) 669 clk_put(fd->clk_ref); 670 kfree(fd->outputs.clks); 671 kfree(fd); 672 kfree(init); 673 } 674 675 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup); 676