1 /* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License as 4 * published by the Free Software Foundation version 2. 5 * 6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 7 * kind, whether express or implied; without even the implied warranty 8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/math64.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/clk/ti.h> 20 21 /* FAPLL Control Register PLL_CTRL */ 22 #define FAPLL_MAIN_MULT_N_SHIFT 16 23 #define FAPLL_MAIN_DIV_P_SHIFT 8 24 #define FAPLL_MAIN_LOCK BIT(7) 25 #define FAPLL_MAIN_PLLEN BIT(3) 26 #define FAPLL_MAIN_BP BIT(2) 27 #define FAPLL_MAIN_LOC_CTL BIT(0) 28 29 #define FAPLL_MAIN_MAX_MULT_N 0xffff 30 #define FAPLL_MAIN_MAX_DIV_P 0xff 31 #define FAPLL_MAIN_CLEAR_MASK \ 32 ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \ 33 (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \ 34 FAPLL_MAIN_LOC_CTL) 35 36 /* FAPLL powerdown register PWD */ 37 #define FAPLL_PWD_OFFSET 4 38 39 #define MAX_FAPLL_OUTPUTS 7 40 #define FAPLL_MAX_RETRIES 1000 41 42 #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw) 43 #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw) 44 45 /* The bypass bit is inverted on the ddr_pll.. */ 46 #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440) 47 48 /* 49 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 50 * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output. 51 */ 52 #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c) 53 #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8) 54 55 /* Synthesizer divider register */ 56 #define SYNTH_LDMDIV1 BIT(8) 57 58 /* Synthesizer frequency register */ 59 #define SYNTH_LDFREQ BIT(31) 60 61 #define SYNTH_PHASE_K 8 62 #define SYNTH_MAX_INT_DIV 0xf 63 #define SYNTH_MAX_DIV_M 0xff 64 65 struct fapll_data { 66 struct clk_hw hw; 67 void __iomem *base; 68 const char *name; 69 struct clk *clk_ref; 70 struct clk *clk_bypass; 71 struct clk_onecell_data outputs; 72 bool bypass_bit_inverted; 73 }; 74 75 struct fapll_synth { 76 struct clk_hw hw; 77 struct fapll_data *fd; 78 int index; 79 void __iomem *freq; 80 void __iomem *div; 81 const char *name; 82 struct clk *clk_pll; 83 }; 84 85 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd) 86 { 87 u32 v = readl_relaxed(fd->base); 88 89 if (fd->bypass_bit_inverted) 90 return !(v & FAPLL_MAIN_BP); 91 else 92 return !!(v & FAPLL_MAIN_BP); 93 } 94 95 static void ti_fapll_set_bypass(struct fapll_data *fd) 96 { 97 u32 v = readl_relaxed(fd->base); 98 99 if (fd->bypass_bit_inverted) 100 v &= ~FAPLL_MAIN_BP; 101 else 102 v |= FAPLL_MAIN_BP; 103 writel_relaxed(v, fd->base); 104 } 105 106 static void ti_fapll_clear_bypass(struct fapll_data *fd) 107 { 108 u32 v = readl_relaxed(fd->base); 109 110 if (fd->bypass_bit_inverted) 111 v |= FAPLL_MAIN_BP; 112 else 113 v &= ~FAPLL_MAIN_BP; 114 writel_relaxed(v, fd->base); 115 } 116 117 static int ti_fapll_wait_lock(struct fapll_data *fd) 118 { 119 int retries = FAPLL_MAX_RETRIES; 120 u32 v; 121 122 while ((v = readl_relaxed(fd->base))) { 123 if (v & FAPLL_MAIN_LOCK) 124 return 0; 125 126 if (retries-- <= 0) 127 break; 128 129 udelay(1); 130 } 131 132 pr_err("%s failed to lock\n", fd->name); 133 134 return -ETIMEDOUT; 135 } 136 137 static int ti_fapll_enable(struct clk_hw *hw) 138 { 139 struct fapll_data *fd = to_fapll(hw); 140 u32 v = readl_relaxed(fd->base); 141 142 v |= FAPLL_MAIN_PLLEN; 143 writel_relaxed(v, fd->base); 144 ti_fapll_wait_lock(fd); 145 146 return 0; 147 } 148 149 static void ti_fapll_disable(struct clk_hw *hw) 150 { 151 struct fapll_data *fd = to_fapll(hw); 152 u32 v = readl_relaxed(fd->base); 153 154 v &= ~FAPLL_MAIN_PLLEN; 155 writel_relaxed(v, fd->base); 156 } 157 158 static int ti_fapll_is_enabled(struct clk_hw *hw) 159 { 160 struct fapll_data *fd = to_fapll(hw); 161 u32 v = readl_relaxed(fd->base); 162 163 return v & FAPLL_MAIN_PLLEN; 164 } 165 166 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 167 unsigned long parent_rate) 168 { 169 struct fapll_data *fd = to_fapll(hw); 170 u32 fapll_n, fapll_p, v; 171 u64 rate; 172 173 if (ti_fapll_clock_is_bypass(fd)) 174 return parent_rate; 175 176 rate = parent_rate; 177 178 /* PLL pre-divider is P and multiplier is N */ 179 v = readl_relaxed(fd->base); 180 fapll_p = (v >> 8) & 0xff; 181 if (fapll_p) 182 do_div(rate, fapll_p); 183 fapll_n = v >> 16; 184 if (fapll_n) 185 rate *= fapll_n; 186 187 return rate; 188 } 189 190 static u8 ti_fapll_get_parent(struct clk_hw *hw) 191 { 192 struct fapll_data *fd = to_fapll(hw); 193 194 if (ti_fapll_clock_is_bypass(fd)) 195 return 1; 196 197 return 0; 198 } 199 200 static int ti_fapll_set_div_mult(unsigned long rate, 201 unsigned long parent_rate, 202 u32 *pre_div_p, u32 *mult_n) 203 { 204 /* 205 * So far no luck getting decent clock with PLL divider, 206 * PLL does not seem to lock and the signal does not look 207 * right. It seems the divider can only be used together 208 * with the multiplier? 209 */ 210 if (rate < parent_rate) { 211 pr_warn("FAPLL main divider rates unsupported\n"); 212 return -EINVAL; 213 } 214 215 *mult_n = rate / parent_rate; 216 if (*mult_n > FAPLL_MAIN_MAX_MULT_N) 217 return -EINVAL; 218 *pre_div_p = 1; 219 220 return 0; 221 } 222 223 static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate, 224 unsigned long *parent_rate) 225 { 226 u32 pre_div_p, mult_n; 227 int error; 228 229 if (!rate) 230 return -EINVAL; 231 232 error = ti_fapll_set_div_mult(rate, *parent_rate, 233 &pre_div_p, &mult_n); 234 if (error) 235 return error; 236 237 rate = *parent_rate / pre_div_p; 238 rate *= mult_n; 239 240 return rate; 241 } 242 243 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate, 244 unsigned long parent_rate) 245 { 246 struct fapll_data *fd = to_fapll(hw); 247 u32 pre_div_p, mult_n, v; 248 int error; 249 250 if (!rate) 251 return -EINVAL; 252 253 error = ti_fapll_set_div_mult(rate, parent_rate, 254 &pre_div_p, &mult_n); 255 if (error) 256 return error; 257 258 ti_fapll_set_bypass(fd); 259 v = readl_relaxed(fd->base); 260 v &= ~FAPLL_MAIN_CLEAR_MASK; 261 v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT; 262 v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT; 263 writel_relaxed(v, fd->base); 264 if (ti_fapll_is_enabled(hw)) 265 ti_fapll_wait_lock(fd); 266 ti_fapll_clear_bypass(fd); 267 268 return 0; 269 } 270 271 static struct clk_ops ti_fapll_ops = { 272 .enable = ti_fapll_enable, 273 .disable = ti_fapll_disable, 274 .is_enabled = ti_fapll_is_enabled, 275 .recalc_rate = ti_fapll_recalc_rate, 276 .get_parent = ti_fapll_get_parent, 277 .round_rate = ti_fapll_round_rate, 278 .set_rate = ti_fapll_set_rate, 279 }; 280 281 static int ti_fapll_synth_enable(struct clk_hw *hw) 282 { 283 struct fapll_synth *synth = to_synth(hw); 284 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 285 286 v &= ~(1 << synth->index); 287 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 288 289 return 0; 290 } 291 292 static void ti_fapll_synth_disable(struct clk_hw *hw) 293 { 294 struct fapll_synth *synth = to_synth(hw); 295 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 296 297 v |= 1 << synth->index; 298 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 299 } 300 301 static int ti_fapll_synth_is_enabled(struct clk_hw *hw) 302 { 303 struct fapll_synth *synth = to_synth(hw); 304 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 305 306 return !(v & (1 << synth->index)); 307 } 308 309 /* 310 * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info 311 */ 312 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, 313 unsigned long parent_rate) 314 { 315 struct fapll_synth *synth = to_synth(hw); 316 u32 synth_div_m; 317 u64 rate; 318 319 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ 320 if (!synth->div) 321 return 32768; 322 323 /* 324 * PLL in bypass sets the synths in bypass mode too. The PLL rate 325 * can be also be set to 27MHz, so we can't use parent_rate to 326 * check for bypass mode. 327 */ 328 if (ti_fapll_clock_is_bypass(synth->fd)) 329 return parent_rate; 330 331 rate = parent_rate; 332 333 /* 334 * Synth frequency integer and fractional divider. 335 * Note that the phase output K is 8, so the result needs 336 * to be multiplied by SYNTH_PHASE_K. 337 */ 338 if (synth->freq) { 339 u32 v, synth_int_div, synth_frac_div, synth_div_freq; 340 341 v = readl_relaxed(synth->freq); 342 synth_int_div = (v >> 24) & 0xf; 343 synth_frac_div = v & 0xffffff; 344 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; 345 rate *= 10000000; 346 do_div(rate, synth_div_freq); 347 rate *= SYNTH_PHASE_K; 348 } 349 350 /* Synth post-divider M */ 351 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 352 353 return DIV_ROUND_UP_ULL(rate, synth_div_m); 354 } 355 356 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw, 357 unsigned long parent_rate) 358 { 359 struct fapll_synth *synth = to_synth(hw); 360 unsigned long current_rate, frac_rate; 361 u32 post_div_m; 362 363 current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate); 364 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 365 frac_rate = current_rate * post_div_m; 366 367 return frac_rate; 368 } 369 370 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth, 371 unsigned long rate, 372 unsigned long parent_rate) 373 { 374 u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v; 375 376 post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate); 377 post_div_m = post_div_m / SYNTH_MAX_INT_DIV; 378 if (post_div_m > SYNTH_MAX_DIV_M) 379 return -EINVAL; 380 if (!post_div_m) 381 post_div_m = 1; 382 383 for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) { 384 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate * 385 SYNTH_PHASE_K * 386 10000000, 387 rate * post_div_m); 388 synth_frac_div = synth_int_div % 10000000; 389 synth_int_div /= 10000000; 390 391 if (synth_int_div <= SYNTH_MAX_INT_DIV) 392 break; 393 } 394 395 if (synth_int_div > SYNTH_MAX_INT_DIV) 396 return -EINVAL; 397 398 v = readl_relaxed(synth->freq); 399 v &= ~0x1fffffff; 400 v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24; 401 v |= (synth_frac_div & 0xffffff); 402 v |= SYNTH_LDFREQ; 403 writel_relaxed(v, synth->freq); 404 405 return post_div_m; 406 } 407 408 static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate, 409 unsigned long *parent_rate) 410 { 411 struct fapll_synth *synth = to_synth(hw); 412 struct fapll_data *fd = synth->fd; 413 unsigned long r; 414 415 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 416 return -EINVAL; 417 418 /* Only post divider m available with no fractional divider? */ 419 if (!synth->freq) { 420 unsigned long frac_rate; 421 u32 synth_post_div_m; 422 423 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate); 424 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate); 425 r = DIV_ROUND_UP(frac_rate, synth_post_div_m); 426 goto out; 427 } 428 429 r = *parent_rate * SYNTH_PHASE_K; 430 if (rate > r) 431 goto out; 432 433 r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); 434 if (rate < r) 435 goto out; 436 437 r = rate; 438 out: 439 return r; 440 } 441 442 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate, 443 unsigned long parent_rate) 444 { 445 struct fapll_synth *synth = to_synth(hw); 446 struct fapll_data *fd = synth->fd; 447 unsigned long frac_rate, post_rate = 0; 448 u32 post_div_m = 0, v; 449 450 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 451 return -EINVAL; 452 453 /* Produce the rate with just post divider M? */ 454 frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate); 455 if (frac_rate < rate) { 456 if (!synth->freq) 457 return -EINVAL; 458 } else { 459 post_div_m = DIV_ROUND_UP(frac_rate, rate); 460 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M)) 461 post_rate = DIV_ROUND_UP(frac_rate, post_div_m); 462 if (!synth->freq && !post_rate) 463 return -EINVAL; 464 } 465 466 /* Need to recalculate the fractional divider? */ 467 if ((post_rate != rate) && synth->freq) 468 post_div_m = ti_fapll_synth_set_frac_rate(synth, 469 rate, 470 parent_rate); 471 472 v = readl_relaxed(synth->div); 473 v &= ~SYNTH_MAX_DIV_M; 474 v |= post_div_m; 475 v |= SYNTH_LDMDIV1; 476 writel_relaxed(v, synth->div); 477 478 return 0; 479 } 480 481 static struct clk_ops ti_fapll_synt_ops = { 482 .enable = ti_fapll_synth_enable, 483 .disable = ti_fapll_synth_disable, 484 .is_enabled = ti_fapll_synth_is_enabled, 485 .recalc_rate = ti_fapll_synth_recalc_rate, 486 .round_rate = ti_fapll_synth_round_rate, 487 .set_rate = ti_fapll_synth_set_rate, 488 }; 489 490 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd, 491 void __iomem *freq, 492 void __iomem *div, 493 int index, 494 const char *name, 495 const char *parent, 496 struct clk *pll_clk) 497 { 498 struct clk_init_data *init; 499 struct fapll_synth *synth; 500 501 init = kzalloc(sizeof(*init), GFP_KERNEL); 502 if (!init) 503 return ERR_PTR(-ENOMEM); 504 505 init->ops = &ti_fapll_synt_ops; 506 init->name = name; 507 init->parent_names = &parent; 508 init->num_parents = 1; 509 510 synth = kzalloc(sizeof(*synth), GFP_KERNEL); 511 if (!synth) 512 goto free; 513 514 synth->fd = fd; 515 synth->index = index; 516 synth->freq = freq; 517 synth->div = div; 518 synth->name = name; 519 synth->hw.init = init; 520 synth->clk_pll = pll_clk; 521 522 return clk_register(NULL, &synth->hw); 523 524 free: 525 kfree(synth); 526 kfree(init); 527 528 return ERR_PTR(-ENOMEM); 529 } 530 531 static void __init ti_fapll_setup(struct device_node *node) 532 { 533 struct fapll_data *fd; 534 struct clk_init_data *init = NULL; 535 const char *parent_name[2]; 536 struct clk *pll_clk; 537 int i; 538 539 fd = kzalloc(sizeof(*fd), GFP_KERNEL); 540 if (!fd) 541 return; 542 543 fd->outputs.clks = kzalloc(sizeof(struct clk *) * 544 MAX_FAPLL_OUTPUTS + 1, 545 GFP_KERNEL); 546 if (!fd->outputs.clks) 547 goto free; 548 549 init = kzalloc(sizeof(*init), GFP_KERNEL); 550 if (!init) 551 goto free; 552 553 init->ops = &ti_fapll_ops; 554 init->name = node->name; 555 556 init->num_parents = of_clk_get_parent_count(node); 557 if (init->num_parents != 2) { 558 pr_err("%s must have two parents\n", node->name); 559 goto free; 560 } 561 562 of_clk_parent_fill(node, parent_name, 2); 563 init->parent_names = parent_name; 564 565 fd->clk_ref = of_clk_get(node, 0); 566 if (IS_ERR(fd->clk_ref)) { 567 pr_err("%s could not get clk_ref\n", node->name); 568 goto free; 569 } 570 571 fd->clk_bypass = of_clk_get(node, 1); 572 if (IS_ERR(fd->clk_bypass)) { 573 pr_err("%s could not get clk_bypass\n", node->name); 574 goto free; 575 } 576 577 fd->base = of_iomap(node, 0); 578 if (!fd->base) { 579 pr_err("%s could not get IO base\n", node->name); 580 goto free; 581 } 582 583 if (fapll_is_ddr_pll(fd->base)) 584 fd->bypass_bit_inverted = true; 585 586 fd->name = node->name; 587 fd->hw.init = init; 588 589 /* Register the parent PLL */ 590 pll_clk = clk_register(NULL, &fd->hw); 591 if (IS_ERR(pll_clk)) 592 goto unmap; 593 594 fd->outputs.clks[0] = pll_clk; 595 fd->outputs.clk_num++; 596 597 /* 598 * Set up the child synthesizers starting at index 1 as the 599 * PLL output is at index 0. We need to check the clock-indices 600 * for numbering in case there are holes in the synth mapping, 601 * and then probe the synth register to see if it has a FREQ 602 * register available. 603 */ 604 for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) { 605 const char *output_name; 606 void __iomem *freq, *div; 607 struct clk *synth_clk; 608 int output_instance; 609 u32 v; 610 611 if (of_property_read_string_index(node, "clock-output-names", 612 i, &output_name)) 613 continue; 614 615 if (of_property_read_u32_index(node, "clock-indices", i, 616 &output_instance)) 617 output_instance = i; 618 619 freq = fd->base + (output_instance * 8); 620 div = freq + 4; 621 622 /* Check for hardwired audio_pll_clk1 */ 623 if (is_audio_pll_clk1(freq)) { 624 freq = NULL; 625 div = NULL; 626 } else { 627 /* Does the synthesizer have a FREQ register? */ 628 v = readl_relaxed(freq); 629 if (!v) 630 freq = NULL; 631 } 632 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, 633 output_name, node->name, 634 pll_clk); 635 if (IS_ERR(synth_clk)) 636 continue; 637 638 fd->outputs.clks[output_instance] = synth_clk; 639 fd->outputs.clk_num++; 640 641 clk_register_clkdev(synth_clk, output_name, NULL); 642 } 643 644 /* Register the child synthesizers as the FAPLL outputs */ 645 of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs); 646 /* Add clock alias for the outputs */ 647 648 kfree(init); 649 650 return; 651 652 unmap: 653 iounmap(fd->base); 654 free: 655 if (fd->clk_bypass) 656 clk_put(fd->clk_bypass); 657 if (fd->clk_ref) 658 clk_put(fd->clk_ref); 659 kfree(fd->outputs.clks); 660 kfree(fd); 661 kfree(init); 662 } 663 664 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup); 665