1163152cbSTony Lindgren /* 2163152cbSTony Lindgren * This program is free software; you can redistribute it and/or 3163152cbSTony Lindgren * modify it under the terms of the GNU General Public License as 4163152cbSTony Lindgren * published by the Free Software Foundation version 2. 5163152cbSTony Lindgren * 6163152cbSTony Lindgren * This program is distributed "as is" WITHOUT ANY WARRANTY of any 7163152cbSTony Lindgren * kind, whether express or implied; without even the implied warranty 8163152cbSTony Lindgren * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9163152cbSTony Lindgren * GNU General Public License for more details. 10163152cbSTony Lindgren */ 11163152cbSTony Lindgren 12163152cbSTony Lindgren #include <linux/clk-provider.h> 13163152cbSTony Lindgren #include <linux/delay.h> 14163152cbSTony Lindgren #include <linux/err.h> 15cafeb002STony Lindgren #include <linux/math64.h> 16163152cbSTony Lindgren #include <linux/of.h> 17163152cbSTony Lindgren #include <linux/of_address.h> 18163152cbSTony Lindgren #include <linux/clk/ti.h> 19163152cbSTony Lindgren 20163152cbSTony Lindgren /* FAPLL Control Register PLL_CTRL */ 219089848dSTony Lindgren #define FAPLL_MAIN_MULT_N_SHIFT 16 229089848dSTony Lindgren #define FAPLL_MAIN_DIV_P_SHIFT 8 23163152cbSTony Lindgren #define FAPLL_MAIN_LOCK BIT(7) 24163152cbSTony Lindgren #define FAPLL_MAIN_PLLEN BIT(3) 25163152cbSTony Lindgren #define FAPLL_MAIN_BP BIT(2) 26163152cbSTony Lindgren #define FAPLL_MAIN_LOC_CTL BIT(0) 27163152cbSTony Lindgren 289089848dSTony Lindgren #define FAPLL_MAIN_MAX_MULT_N 0xffff 299089848dSTony Lindgren #define FAPLL_MAIN_MAX_DIV_P 0xff 309089848dSTony Lindgren #define FAPLL_MAIN_CLEAR_MASK \ 319089848dSTony Lindgren ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \ 329089848dSTony Lindgren (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \ 339089848dSTony Lindgren FAPLL_MAIN_LOC_CTL) 349089848dSTony Lindgren 35163152cbSTony Lindgren /* FAPLL powerdown register PWD */ 36163152cbSTony Lindgren #define FAPLL_PWD_OFFSET 4 37163152cbSTony Lindgren 38163152cbSTony Lindgren #define MAX_FAPLL_OUTPUTS 7 39163152cbSTony Lindgren #define FAPLL_MAX_RETRIES 1000 40163152cbSTony Lindgren 41163152cbSTony Lindgren #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw) 42163152cbSTony Lindgren #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw) 43163152cbSTony Lindgren 44163152cbSTony Lindgren /* The bypass bit is inverted on the ddr_pll.. */ 45163152cbSTony Lindgren #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440) 46163152cbSTony Lindgren 47163152cbSTony Lindgren /* 48163152cbSTony Lindgren * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 49163152cbSTony Lindgren * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output. 50163152cbSTony Lindgren */ 51163152cbSTony Lindgren #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c) 52163152cbSTony Lindgren #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8) 53163152cbSTony Lindgren 54163152cbSTony Lindgren /* Synthesizer divider register */ 55163152cbSTony Lindgren #define SYNTH_LDMDIV1 BIT(8) 56163152cbSTony Lindgren 57163152cbSTony Lindgren /* Synthesizer frequency register */ 58163152cbSTony Lindgren #define SYNTH_LDFREQ BIT(31) 59163152cbSTony Lindgren 60cafeb002STony Lindgren #define SYNTH_PHASE_K 8 61cafeb002STony Lindgren #define SYNTH_MAX_INT_DIV 0xf 6233ca29c9STony Lindgren #define SYNTH_MAX_DIV_M 0xff 6333ca29c9STony Lindgren 64163152cbSTony Lindgren struct fapll_data { 65163152cbSTony Lindgren struct clk_hw hw; 66163152cbSTony Lindgren void __iomem *base; 67163152cbSTony Lindgren const char *name; 68163152cbSTony Lindgren struct clk *clk_ref; 69163152cbSTony Lindgren struct clk *clk_bypass; 70163152cbSTony Lindgren struct clk_onecell_data outputs; 71163152cbSTony Lindgren bool bypass_bit_inverted; 72163152cbSTony Lindgren }; 73163152cbSTony Lindgren 74163152cbSTony Lindgren struct fapll_synth { 75163152cbSTony Lindgren struct clk_hw hw; 76163152cbSTony Lindgren struct fapll_data *fd; 77163152cbSTony Lindgren int index; 78163152cbSTony Lindgren void __iomem *freq; 79163152cbSTony Lindgren void __iomem *div; 80163152cbSTony Lindgren const char *name; 81163152cbSTony Lindgren struct clk *clk_pll; 82163152cbSTony Lindgren }; 83163152cbSTony Lindgren 84163152cbSTony Lindgren static bool ti_fapll_clock_is_bypass(struct fapll_data *fd) 85163152cbSTony Lindgren { 86163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 87163152cbSTony Lindgren 88163152cbSTony Lindgren if (fd->bypass_bit_inverted) 89163152cbSTony Lindgren return !(v & FAPLL_MAIN_BP); 90163152cbSTony Lindgren else 91163152cbSTony Lindgren return !!(v & FAPLL_MAIN_BP); 92163152cbSTony Lindgren } 93163152cbSTony Lindgren 949089848dSTony Lindgren static void ti_fapll_set_bypass(struct fapll_data *fd) 959089848dSTony Lindgren { 969089848dSTony Lindgren u32 v = readl_relaxed(fd->base); 979089848dSTony Lindgren 989089848dSTony Lindgren if (fd->bypass_bit_inverted) 999089848dSTony Lindgren v &= ~FAPLL_MAIN_BP; 1009089848dSTony Lindgren else 1019089848dSTony Lindgren v |= FAPLL_MAIN_BP; 1029089848dSTony Lindgren writel_relaxed(v, fd->base); 1039089848dSTony Lindgren } 1049089848dSTony Lindgren 1059089848dSTony Lindgren static void ti_fapll_clear_bypass(struct fapll_data *fd) 1069089848dSTony Lindgren { 1079089848dSTony Lindgren u32 v = readl_relaxed(fd->base); 1089089848dSTony Lindgren 1099089848dSTony Lindgren if (fd->bypass_bit_inverted) 1109089848dSTony Lindgren v |= FAPLL_MAIN_BP; 1119089848dSTony Lindgren else 1129089848dSTony Lindgren v &= ~FAPLL_MAIN_BP; 1139089848dSTony Lindgren writel_relaxed(v, fd->base); 1149089848dSTony Lindgren } 1159089848dSTony Lindgren 1169089848dSTony Lindgren static int ti_fapll_wait_lock(struct fapll_data *fd) 1179089848dSTony Lindgren { 1189089848dSTony Lindgren int retries = FAPLL_MAX_RETRIES; 1199089848dSTony Lindgren u32 v; 1209089848dSTony Lindgren 1219089848dSTony Lindgren while ((v = readl_relaxed(fd->base))) { 1229089848dSTony Lindgren if (v & FAPLL_MAIN_LOCK) 1239089848dSTony Lindgren return 0; 1249089848dSTony Lindgren 1259089848dSTony Lindgren if (retries-- <= 0) 1269089848dSTony Lindgren break; 1279089848dSTony Lindgren 1289089848dSTony Lindgren udelay(1); 1299089848dSTony Lindgren } 1309089848dSTony Lindgren 1319089848dSTony Lindgren pr_err("%s failed to lock\n", fd->name); 1329089848dSTony Lindgren 1339089848dSTony Lindgren return -ETIMEDOUT; 1349089848dSTony Lindgren } 1359089848dSTony Lindgren 136163152cbSTony Lindgren static int ti_fapll_enable(struct clk_hw *hw) 137163152cbSTony Lindgren { 138163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 139163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 140163152cbSTony Lindgren 14103208cc6STony Lindgren v |= FAPLL_MAIN_PLLEN; 142163152cbSTony Lindgren writel_relaxed(v, fd->base); 1439089848dSTony Lindgren ti_fapll_wait_lock(fd); 144163152cbSTony Lindgren 145163152cbSTony Lindgren return 0; 146163152cbSTony Lindgren } 147163152cbSTony Lindgren 148163152cbSTony Lindgren static void ti_fapll_disable(struct clk_hw *hw) 149163152cbSTony Lindgren { 150163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 151163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 152163152cbSTony Lindgren 15303208cc6STony Lindgren v &= ~FAPLL_MAIN_PLLEN; 154163152cbSTony Lindgren writel_relaxed(v, fd->base); 155163152cbSTony Lindgren } 156163152cbSTony Lindgren 157163152cbSTony Lindgren static int ti_fapll_is_enabled(struct clk_hw *hw) 158163152cbSTony Lindgren { 159163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 160163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 161163152cbSTony Lindgren 16203208cc6STony Lindgren return v & FAPLL_MAIN_PLLEN; 163163152cbSTony Lindgren } 164163152cbSTony Lindgren 165163152cbSTony Lindgren static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 166163152cbSTony Lindgren unsigned long parent_rate) 167163152cbSTony Lindgren { 168163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 169163152cbSTony Lindgren u32 fapll_n, fapll_p, v; 170163152cbSTony Lindgren long long rate; 171163152cbSTony Lindgren 172163152cbSTony Lindgren if (ti_fapll_clock_is_bypass(fd)) 173163152cbSTony Lindgren return parent_rate; 174163152cbSTony Lindgren 175163152cbSTony Lindgren rate = parent_rate; 176163152cbSTony Lindgren 177163152cbSTony Lindgren /* PLL pre-divider is P and multiplier is N */ 178163152cbSTony Lindgren v = readl_relaxed(fd->base); 179163152cbSTony Lindgren fapll_p = (v >> 8) & 0xff; 180163152cbSTony Lindgren if (fapll_p) 181163152cbSTony Lindgren do_div(rate, fapll_p); 182163152cbSTony Lindgren fapll_n = v >> 16; 183163152cbSTony Lindgren if (fapll_n) 184163152cbSTony Lindgren rate *= fapll_n; 185163152cbSTony Lindgren 186163152cbSTony Lindgren return rate; 187163152cbSTony Lindgren } 188163152cbSTony Lindgren 189163152cbSTony Lindgren static u8 ti_fapll_get_parent(struct clk_hw *hw) 190163152cbSTony Lindgren { 191163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 192163152cbSTony Lindgren 193163152cbSTony Lindgren if (ti_fapll_clock_is_bypass(fd)) 194163152cbSTony Lindgren return 1; 195163152cbSTony Lindgren 196163152cbSTony Lindgren return 0; 197163152cbSTony Lindgren } 198163152cbSTony Lindgren 1999089848dSTony Lindgren static int ti_fapll_set_div_mult(unsigned long rate, 2009089848dSTony Lindgren unsigned long parent_rate, 2019089848dSTony Lindgren u32 *pre_div_p, u32 *mult_n) 2029089848dSTony Lindgren { 2039089848dSTony Lindgren /* 2049089848dSTony Lindgren * So far no luck getting decent clock with PLL divider, 2059089848dSTony Lindgren * PLL does not seem to lock and the signal does not look 2069089848dSTony Lindgren * right. It seems the divider can only be used together 2079089848dSTony Lindgren * with the multiplier? 2089089848dSTony Lindgren */ 2099089848dSTony Lindgren if (rate < parent_rate) { 2109089848dSTony Lindgren pr_warn("FAPLL main divider rates unsupported\n"); 2119089848dSTony Lindgren return -EINVAL; 2129089848dSTony Lindgren } 2139089848dSTony Lindgren 2149089848dSTony Lindgren *mult_n = rate / parent_rate; 2159089848dSTony Lindgren if (*mult_n > FAPLL_MAIN_MAX_MULT_N) 2169089848dSTony Lindgren return -EINVAL; 2179089848dSTony Lindgren *pre_div_p = 1; 2189089848dSTony Lindgren 2199089848dSTony Lindgren return 0; 2209089848dSTony Lindgren } 2219089848dSTony Lindgren 2229089848dSTony Lindgren static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate, 2239089848dSTony Lindgren unsigned long *parent_rate) 2249089848dSTony Lindgren { 2259089848dSTony Lindgren u32 pre_div_p, mult_n; 2269089848dSTony Lindgren int error; 2279089848dSTony Lindgren 2289089848dSTony Lindgren if (!rate) 2299089848dSTony Lindgren return -EINVAL; 2309089848dSTony Lindgren 2319089848dSTony Lindgren error = ti_fapll_set_div_mult(rate, *parent_rate, 2329089848dSTony Lindgren &pre_div_p, &mult_n); 2339089848dSTony Lindgren if (error) 2349089848dSTony Lindgren return error; 2359089848dSTony Lindgren 2369089848dSTony Lindgren rate = *parent_rate / pre_div_p; 2379089848dSTony Lindgren rate *= mult_n; 2389089848dSTony Lindgren 2399089848dSTony Lindgren return rate; 2409089848dSTony Lindgren } 2419089848dSTony Lindgren 2429089848dSTony Lindgren static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate, 2439089848dSTony Lindgren unsigned long parent_rate) 2449089848dSTony Lindgren { 2459089848dSTony Lindgren struct fapll_data *fd = to_fapll(hw); 2469089848dSTony Lindgren u32 pre_div_p, mult_n, v; 2479089848dSTony Lindgren int error; 2489089848dSTony Lindgren 2499089848dSTony Lindgren if (!rate) 2509089848dSTony Lindgren return -EINVAL; 2519089848dSTony Lindgren 2529089848dSTony Lindgren error = ti_fapll_set_div_mult(rate, parent_rate, 2539089848dSTony Lindgren &pre_div_p, &mult_n); 2549089848dSTony Lindgren if (error) 2559089848dSTony Lindgren return error; 2569089848dSTony Lindgren 2579089848dSTony Lindgren ti_fapll_set_bypass(fd); 2589089848dSTony Lindgren v = readl_relaxed(fd->base); 2599089848dSTony Lindgren v &= ~FAPLL_MAIN_CLEAR_MASK; 2609089848dSTony Lindgren v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT; 2619089848dSTony Lindgren v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT; 2629089848dSTony Lindgren writel_relaxed(v, fd->base); 2639089848dSTony Lindgren if (ti_fapll_is_enabled(hw)) 2649089848dSTony Lindgren ti_fapll_wait_lock(fd); 2659089848dSTony Lindgren ti_fapll_clear_bypass(fd); 2669089848dSTony Lindgren 2679089848dSTony Lindgren return 0; 2689089848dSTony Lindgren } 2699089848dSTony Lindgren 270163152cbSTony Lindgren static struct clk_ops ti_fapll_ops = { 271163152cbSTony Lindgren .enable = ti_fapll_enable, 272163152cbSTony Lindgren .disable = ti_fapll_disable, 273163152cbSTony Lindgren .is_enabled = ti_fapll_is_enabled, 274163152cbSTony Lindgren .recalc_rate = ti_fapll_recalc_rate, 275163152cbSTony Lindgren .get_parent = ti_fapll_get_parent, 2769089848dSTony Lindgren .round_rate = ti_fapll_round_rate, 2779089848dSTony Lindgren .set_rate = ti_fapll_set_rate, 278163152cbSTony Lindgren }; 279163152cbSTony Lindgren 280163152cbSTony Lindgren static int ti_fapll_synth_enable(struct clk_hw *hw) 281163152cbSTony Lindgren { 282163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 283163152cbSTony Lindgren u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 284163152cbSTony Lindgren 285163152cbSTony Lindgren v &= ~(1 << synth->index); 286163152cbSTony Lindgren writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 287163152cbSTony Lindgren 288163152cbSTony Lindgren return 0; 289163152cbSTony Lindgren } 290163152cbSTony Lindgren 291163152cbSTony Lindgren static void ti_fapll_synth_disable(struct clk_hw *hw) 292163152cbSTony Lindgren { 293163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 294163152cbSTony Lindgren u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 295163152cbSTony Lindgren 296163152cbSTony Lindgren v |= 1 << synth->index; 297163152cbSTony Lindgren writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 298163152cbSTony Lindgren } 299163152cbSTony Lindgren 300163152cbSTony Lindgren static int ti_fapll_synth_is_enabled(struct clk_hw *hw) 301163152cbSTony Lindgren { 302163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 303163152cbSTony Lindgren u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 304163152cbSTony Lindgren 305163152cbSTony Lindgren return !(v & (1 << synth->index)); 306163152cbSTony Lindgren } 307163152cbSTony Lindgren 308163152cbSTony Lindgren /* 309163152cbSTony Lindgren * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info 310163152cbSTony Lindgren */ 311163152cbSTony Lindgren static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, 312163152cbSTony Lindgren unsigned long parent_rate) 313163152cbSTony Lindgren { 314163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 315163152cbSTony Lindgren u32 synth_div_m; 316163152cbSTony Lindgren long long rate; 317163152cbSTony Lindgren 318163152cbSTony Lindgren /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ 319163152cbSTony Lindgren if (!synth->div) 320163152cbSTony Lindgren return 32768; 321163152cbSTony Lindgren 322163152cbSTony Lindgren /* 323163152cbSTony Lindgren * PLL in bypass sets the synths in bypass mode too. The PLL rate 324163152cbSTony Lindgren * can be also be set to 27MHz, so we can't use parent_rate to 325163152cbSTony Lindgren * check for bypass mode. 326163152cbSTony Lindgren */ 327163152cbSTony Lindgren if (ti_fapll_clock_is_bypass(synth->fd)) 328163152cbSTony Lindgren return parent_rate; 329163152cbSTony Lindgren 330163152cbSTony Lindgren rate = parent_rate; 331163152cbSTony Lindgren 332163152cbSTony Lindgren /* 333163152cbSTony Lindgren * Synth frequency integer and fractional divider. 334163152cbSTony Lindgren * Note that the phase output K is 8, so the result needs 335cafeb002STony Lindgren * to be multiplied by SYNTH_PHASE_K. 336163152cbSTony Lindgren */ 337163152cbSTony Lindgren if (synth->freq) { 338163152cbSTony Lindgren u32 v, synth_int_div, synth_frac_div, synth_div_freq; 339163152cbSTony Lindgren 340163152cbSTony Lindgren v = readl_relaxed(synth->freq); 341163152cbSTony Lindgren synth_int_div = (v >> 24) & 0xf; 342163152cbSTony Lindgren synth_frac_div = v & 0xffffff; 343163152cbSTony Lindgren synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; 344163152cbSTony Lindgren rate *= 10000000; 345163152cbSTony Lindgren do_div(rate, synth_div_freq); 346cafeb002STony Lindgren rate *= SYNTH_PHASE_K; 347163152cbSTony Lindgren } 348163152cbSTony Lindgren 34933ca29c9STony Lindgren /* Synth post-divider M */ 35033ca29c9STony Lindgren synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 351163152cbSTony Lindgren 35233ca29c9STony Lindgren return DIV_ROUND_UP_ULL(rate, synth_div_m); 353163152cbSTony Lindgren } 354163152cbSTony Lindgren 355cafeb002STony Lindgren static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw, 356cafeb002STony Lindgren unsigned long parent_rate) 357cafeb002STony Lindgren { 358cafeb002STony Lindgren struct fapll_synth *synth = to_synth(hw); 359cafeb002STony Lindgren unsigned long current_rate, frac_rate; 360cafeb002STony Lindgren u32 post_div_m; 361cafeb002STony Lindgren 362cafeb002STony Lindgren current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate); 363cafeb002STony Lindgren post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 364cafeb002STony Lindgren frac_rate = current_rate * post_div_m; 365cafeb002STony Lindgren 366cafeb002STony Lindgren return frac_rate; 367cafeb002STony Lindgren } 368cafeb002STony Lindgren 369cafeb002STony Lindgren static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth, 370cafeb002STony Lindgren unsigned long rate, 371cafeb002STony Lindgren unsigned long parent_rate) 372cafeb002STony Lindgren { 373cafeb002STony Lindgren u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v; 374cafeb002STony Lindgren 375cafeb002STony Lindgren post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate); 376cafeb002STony Lindgren post_div_m = post_div_m / SYNTH_MAX_INT_DIV; 377cafeb002STony Lindgren if (post_div_m > SYNTH_MAX_DIV_M) 378cafeb002STony Lindgren return -EINVAL; 379cafeb002STony Lindgren if (!post_div_m) 380cafeb002STony Lindgren post_div_m = 1; 381cafeb002STony Lindgren 382cafeb002STony Lindgren for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) { 383cafeb002STony Lindgren synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate * 384cafeb002STony Lindgren SYNTH_PHASE_K * 385cafeb002STony Lindgren 10000000, 386cafeb002STony Lindgren rate * post_div_m); 387cafeb002STony Lindgren synth_frac_div = synth_int_div % 10000000; 388cafeb002STony Lindgren synth_int_div /= 10000000; 389cafeb002STony Lindgren 390cafeb002STony Lindgren if (synth_int_div <= SYNTH_MAX_INT_DIV) 391cafeb002STony Lindgren break; 392cafeb002STony Lindgren } 393cafeb002STony Lindgren 394cafeb002STony Lindgren if (synth_int_div > SYNTH_MAX_INT_DIV) 395cafeb002STony Lindgren return -EINVAL; 396cafeb002STony Lindgren 397cafeb002STony Lindgren v = readl_relaxed(synth->freq); 398cafeb002STony Lindgren v &= ~0x1fffffff; 399cafeb002STony Lindgren v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24; 400cafeb002STony Lindgren v |= (synth_frac_div & 0xffffff); 401cafeb002STony Lindgren v |= SYNTH_LDFREQ; 402cafeb002STony Lindgren writel_relaxed(v, synth->freq); 403cafeb002STony Lindgren 404cafeb002STony Lindgren return post_div_m; 405cafeb002STony Lindgren } 406cafeb002STony Lindgren 407cafeb002STony Lindgren static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate, 408cafeb002STony Lindgren unsigned long *parent_rate) 409cafeb002STony Lindgren { 410cafeb002STony Lindgren struct fapll_synth *synth = to_synth(hw); 411cafeb002STony Lindgren struct fapll_data *fd = synth->fd; 412cafeb002STony Lindgren unsigned long r; 413cafeb002STony Lindgren 414cafeb002STony Lindgren if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 415cafeb002STony Lindgren return -EINVAL; 416cafeb002STony Lindgren 417cafeb002STony Lindgren /* Only post divider m available with no fractional divider? */ 418cafeb002STony Lindgren if (!synth->freq) { 419cafeb002STony Lindgren unsigned long frac_rate; 420cafeb002STony Lindgren u32 synth_post_div_m; 421cafeb002STony Lindgren 422cafeb002STony Lindgren frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate); 423cafeb002STony Lindgren synth_post_div_m = DIV_ROUND_UP(frac_rate, rate); 424cafeb002STony Lindgren r = DIV_ROUND_UP(frac_rate, synth_post_div_m); 425cafeb002STony Lindgren goto out; 426cafeb002STony Lindgren } 427cafeb002STony Lindgren 428cafeb002STony Lindgren r = *parent_rate * SYNTH_PHASE_K; 429cafeb002STony Lindgren if (rate > r) 430cafeb002STony Lindgren goto out; 431cafeb002STony Lindgren 432cafeb002STony Lindgren r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); 433cafeb002STony Lindgren if (rate < r) 434cafeb002STony Lindgren goto out; 435cafeb002STony Lindgren 436cafeb002STony Lindgren r = rate; 437cafeb002STony Lindgren out: 438cafeb002STony Lindgren return r; 439cafeb002STony Lindgren } 440cafeb002STony Lindgren 441cafeb002STony Lindgren static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate, 442cafeb002STony Lindgren unsigned long parent_rate) 443cafeb002STony Lindgren { 444cafeb002STony Lindgren struct fapll_synth *synth = to_synth(hw); 445cafeb002STony Lindgren struct fapll_data *fd = synth->fd; 446cafeb002STony Lindgren unsigned long frac_rate, post_rate = 0; 447cafeb002STony Lindgren u32 post_div_m = 0, v; 448cafeb002STony Lindgren 449cafeb002STony Lindgren if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 450cafeb002STony Lindgren return -EINVAL; 451cafeb002STony Lindgren 452cafeb002STony Lindgren /* Produce the rate with just post divider M? */ 453cafeb002STony Lindgren frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate); 454cafeb002STony Lindgren if (frac_rate < rate) { 455cafeb002STony Lindgren if (!synth->freq) 456cafeb002STony Lindgren return -EINVAL; 457cafeb002STony Lindgren } else { 458cafeb002STony Lindgren post_div_m = DIV_ROUND_UP(frac_rate, rate); 459cafeb002STony Lindgren if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M)) 460cafeb002STony Lindgren post_rate = DIV_ROUND_UP(frac_rate, post_div_m); 461cafeb002STony Lindgren if (!synth->freq && !post_rate) 462cafeb002STony Lindgren return -EINVAL; 463cafeb002STony Lindgren } 464cafeb002STony Lindgren 465cafeb002STony Lindgren /* Need to recalculate the fractional divider? */ 466cafeb002STony Lindgren if ((post_rate != rate) && synth->freq) 467cafeb002STony Lindgren post_div_m = ti_fapll_synth_set_frac_rate(synth, 468cafeb002STony Lindgren rate, 469cafeb002STony Lindgren parent_rate); 470cafeb002STony Lindgren 471cafeb002STony Lindgren v = readl_relaxed(synth->div); 472cafeb002STony Lindgren v &= ~SYNTH_MAX_DIV_M; 473cafeb002STony Lindgren v |= post_div_m; 474cafeb002STony Lindgren v |= SYNTH_LDMDIV1; 475cafeb002STony Lindgren writel_relaxed(v, synth->div); 476cafeb002STony Lindgren 477cafeb002STony Lindgren return 0; 478163152cbSTony Lindgren } 479163152cbSTony Lindgren 480163152cbSTony Lindgren static struct clk_ops ti_fapll_synt_ops = { 481163152cbSTony Lindgren .enable = ti_fapll_synth_enable, 482163152cbSTony Lindgren .disable = ti_fapll_synth_disable, 483163152cbSTony Lindgren .is_enabled = ti_fapll_synth_is_enabled, 484163152cbSTony Lindgren .recalc_rate = ti_fapll_synth_recalc_rate, 485cafeb002STony Lindgren .round_rate = ti_fapll_synth_round_rate, 486cafeb002STony Lindgren .set_rate = ti_fapll_synth_set_rate, 487163152cbSTony Lindgren }; 488163152cbSTony Lindgren 489163152cbSTony Lindgren static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd, 490163152cbSTony Lindgren void __iomem *freq, 491163152cbSTony Lindgren void __iomem *div, 492163152cbSTony Lindgren int index, 493163152cbSTony Lindgren const char *name, 494163152cbSTony Lindgren const char *parent, 495163152cbSTony Lindgren struct clk *pll_clk) 496163152cbSTony Lindgren { 497163152cbSTony Lindgren struct clk_init_data *init; 498163152cbSTony Lindgren struct fapll_synth *synth; 499163152cbSTony Lindgren 500163152cbSTony Lindgren init = kzalloc(sizeof(*init), GFP_KERNEL); 501163152cbSTony Lindgren if (!init) 502163152cbSTony Lindgren return ERR_PTR(-ENOMEM); 503163152cbSTony Lindgren 504163152cbSTony Lindgren init->ops = &ti_fapll_synt_ops; 505163152cbSTony Lindgren init->name = name; 506163152cbSTony Lindgren init->parent_names = &parent; 507163152cbSTony Lindgren init->num_parents = 1; 508163152cbSTony Lindgren 509163152cbSTony Lindgren synth = kzalloc(sizeof(*synth), GFP_KERNEL); 510163152cbSTony Lindgren if (!synth) 511163152cbSTony Lindgren goto free; 512163152cbSTony Lindgren 513163152cbSTony Lindgren synth->fd = fd; 514163152cbSTony Lindgren synth->index = index; 515163152cbSTony Lindgren synth->freq = freq; 516163152cbSTony Lindgren synth->div = div; 517163152cbSTony Lindgren synth->name = name; 518163152cbSTony Lindgren synth->hw.init = init; 519163152cbSTony Lindgren synth->clk_pll = pll_clk; 520163152cbSTony Lindgren 521163152cbSTony Lindgren return clk_register(NULL, &synth->hw); 522163152cbSTony Lindgren 523163152cbSTony Lindgren free: 524163152cbSTony Lindgren kfree(synth); 525163152cbSTony Lindgren kfree(init); 526163152cbSTony Lindgren 527163152cbSTony Lindgren return ERR_PTR(-ENOMEM); 528163152cbSTony Lindgren } 529163152cbSTony Lindgren 530163152cbSTony Lindgren static void __init ti_fapll_setup(struct device_node *node) 531163152cbSTony Lindgren { 532163152cbSTony Lindgren struct fapll_data *fd; 533163152cbSTony Lindgren struct clk_init_data *init = NULL; 534163152cbSTony Lindgren const char *parent_name[2]; 535163152cbSTony Lindgren struct clk *pll_clk; 536163152cbSTony Lindgren int i; 537163152cbSTony Lindgren 538163152cbSTony Lindgren fd = kzalloc(sizeof(*fd), GFP_KERNEL); 539163152cbSTony Lindgren if (!fd) 540163152cbSTony Lindgren return; 541163152cbSTony Lindgren 542163152cbSTony Lindgren fd->outputs.clks = kzalloc(sizeof(struct clk *) * 543163152cbSTony Lindgren MAX_FAPLL_OUTPUTS + 1, 544163152cbSTony Lindgren GFP_KERNEL); 545163152cbSTony Lindgren if (!fd->outputs.clks) 546163152cbSTony Lindgren goto free; 547163152cbSTony Lindgren 548163152cbSTony Lindgren init = kzalloc(sizeof(*init), GFP_KERNEL); 549163152cbSTony Lindgren if (!init) 550163152cbSTony Lindgren goto free; 551163152cbSTony Lindgren 552163152cbSTony Lindgren init->ops = &ti_fapll_ops; 553163152cbSTony Lindgren init->name = node->name; 554163152cbSTony Lindgren 555163152cbSTony Lindgren init->num_parents = of_clk_get_parent_count(node); 556163152cbSTony Lindgren if (init->num_parents != 2) { 557163152cbSTony Lindgren pr_err("%s must have two parents\n", node->name); 558163152cbSTony Lindgren goto free; 559163152cbSTony Lindgren } 560163152cbSTony Lindgren 561163152cbSTony Lindgren parent_name[0] = of_clk_get_parent_name(node, 0); 562163152cbSTony Lindgren parent_name[1] = of_clk_get_parent_name(node, 1); 563163152cbSTony Lindgren init->parent_names = parent_name; 564163152cbSTony Lindgren 565163152cbSTony Lindgren fd->clk_ref = of_clk_get(node, 0); 566163152cbSTony Lindgren if (IS_ERR(fd->clk_ref)) { 567163152cbSTony Lindgren pr_err("%s could not get clk_ref\n", node->name); 568163152cbSTony Lindgren goto free; 569163152cbSTony Lindgren } 570163152cbSTony Lindgren 571163152cbSTony Lindgren fd->clk_bypass = of_clk_get(node, 1); 572163152cbSTony Lindgren if (IS_ERR(fd->clk_bypass)) { 573163152cbSTony Lindgren pr_err("%s could not get clk_bypass\n", node->name); 574163152cbSTony Lindgren goto free; 575163152cbSTony Lindgren } 576163152cbSTony Lindgren 577163152cbSTony Lindgren fd->base = of_iomap(node, 0); 578163152cbSTony Lindgren if (!fd->base) { 579163152cbSTony Lindgren pr_err("%s could not get IO base\n", node->name); 580163152cbSTony Lindgren goto free; 581163152cbSTony Lindgren } 582163152cbSTony Lindgren 583163152cbSTony Lindgren if (fapll_is_ddr_pll(fd->base)) 584163152cbSTony Lindgren fd->bypass_bit_inverted = true; 585163152cbSTony Lindgren 586163152cbSTony Lindgren fd->name = node->name; 587163152cbSTony Lindgren fd->hw.init = init; 588163152cbSTony Lindgren 589163152cbSTony Lindgren /* Register the parent PLL */ 590163152cbSTony Lindgren pll_clk = clk_register(NULL, &fd->hw); 591163152cbSTony Lindgren if (IS_ERR(pll_clk)) 592163152cbSTony Lindgren goto unmap; 593163152cbSTony Lindgren 594163152cbSTony Lindgren fd->outputs.clks[0] = pll_clk; 595163152cbSTony Lindgren fd->outputs.clk_num++; 596163152cbSTony Lindgren 597163152cbSTony Lindgren /* 598163152cbSTony Lindgren * Set up the child synthesizers starting at index 1 as the 599163152cbSTony Lindgren * PLL output is at index 0. We need to check the clock-indices 600163152cbSTony Lindgren * for numbering in case there are holes in the synth mapping, 601163152cbSTony Lindgren * and then probe the synth register to see if it has a FREQ 602163152cbSTony Lindgren * register available. 603163152cbSTony Lindgren */ 604163152cbSTony Lindgren for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) { 605163152cbSTony Lindgren const char *output_name; 606163152cbSTony Lindgren void __iomem *freq, *div; 607163152cbSTony Lindgren struct clk *synth_clk; 608163152cbSTony Lindgren int output_instance; 609163152cbSTony Lindgren u32 v; 610163152cbSTony Lindgren 611163152cbSTony Lindgren if (of_property_read_string_index(node, "clock-output-names", 612163152cbSTony Lindgren i, &output_name)) 613163152cbSTony Lindgren continue; 614163152cbSTony Lindgren 615163152cbSTony Lindgren if (of_property_read_u32_index(node, "clock-indices", i, 616163152cbSTony Lindgren &output_instance)) 617163152cbSTony Lindgren output_instance = i; 618163152cbSTony Lindgren 619163152cbSTony Lindgren freq = fd->base + (output_instance * 8); 620163152cbSTony Lindgren div = freq + 4; 621163152cbSTony Lindgren 622163152cbSTony Lindgren /* Check for hardwired audio_pll_clk1 */ 623163152cbSTony Lindgren if (is_audio_pll_clk1(freq)) { 624412d6b47SStephen Boyd freq = NULL; 625412d6b47SStephen Boyd div = NULL; 626163152cbSTony Lindgren } else { 627163152cbSTony Lindgren /* Does the synthesizer have a FREQ register? */ 628163152cbSTony Lindgren v = readl_relaxed(freq); 629163152cbSTony Lindgren if (!v) 630412d6b47SStephen Boyd freq = NULL; 631163152cbSTony Lindgren } 632163152cbSTony Lindgren synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, 633163152cbSTony Lindgren output_name, node->name, 634163152cbSTony Lindgren pll_clk); 635163152cbSTony Lindgren if (IS_ERR(synth_clk)) 636163152cbSTony Lindgren continue; 637163152cbSTony Lindgren 638163152cbSTony Lindgren fd->outputs.clks[output_instance] = synth_clk; 639163152cbSTony Lindgren fd->outputs.clk_num++; 640163152cbSTony Lindgren 641163152cbSTony Lindgren clk_register_clkdev(synth_clk, output_name, NULL); 642163152cbSTony Lindgren } 643163152cbSTony Lindgren 644163152cbSTony Lindgren /* Register the child synthesizers as the FAPLL outputs */ 645163152cbSTony Lindgren of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs); 646163152cbSTony Lindgren /* Add clock alias for the outputs */ 647163152cbSTony Lindgren 648163152cbSTony Lindgren kfree(init); 649163152cbSTony Lindgren 650163152cbSTony Lindgren return; 651163152cbSTony Lindgren 652163152cbSTony Lindgren unmap: 653163152cbSTony Lindgren iounmap(fd->base); 654163152cbSTony Lindgren free: 655163152cbSTony Lindgren if (fd->clk_bypass) 656163152cbSTony Lindgren clk_put(fd->clk_bypass); 657163152cbSTony Lindgren if (fd->clk_ref) 658163152cbSTony Lindgren clk_put(fd->clk_ref); 659163152cbSTony Lindgren kfree(fd->outputs.clks); 660163152cbSTony Lindgren kfree(fd); 661163152cbSTony Lindgren kfree(init); 662163152cbSTony Lindgren } 663163152cbSTony Lindgren 664163152cbSTony Lindgren CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup); 665