1163152cbSTony Lindgren /* 2163152cbSTony Lindgren * This program is free software; you can redistribute it and/or 3163152cbSTony Lindgren * modify it under the terms of the GNU General Public License as 4163152cbSTony Lindgren * published by the Free Software Foundation version 2. 5163152cbSTony Lindgren * 6163152cbSTony Lindgren * This program is distributed "as is" WITHOUT ANY WARRANTY of any 7163152cbSTony Lindgren * kind, whether express or implied; without even the implied warranty 8163152cbSTony Lindgren * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9163152cbSTony Lindgren * GNU General Public License for more details. 10163152cbSTony Lindgren */ 11163152cbSTony Lindgren 12163152cbSTony Lindgren #include <linux/clk-provider.h> 13163152cbSTony Lindgren #include <linux/delay.h> 14163152cbSTony Lindgren #include <linux/slab.h> 15163152cbSTony Lindgren #include <linux/err.h> 16163152cbSTony Lindgren #include <linux/of.h> 17163152cbSTony Lindgren #include <linux/of_address.h> 18163152cbSTony Lindgren #include <linux/clk/ti.h> 19163152cbSTony Lindgren #include <asm/div64.h> 20163152cbSTony Lindgren 21163152cbSTony Lindgren /* FAPLL Control Register PLL_CTRL */ 22163152cbSTony Lindgren #define FAPLL_MAIN_LOCK BIT(7) 23163152cbSTony Lindgren #define FAPLL_MAIN_PLLEN BIT(3) 24163152cbSTony Lindgren #define FAPLL_MAIN_BP BIT(2) 25163152cbSTony Lindgren #define FAPLL_MAIN_LOC_CTL BIT(0) 26163152cbSTony Lindgren 27163152cbSTony Lindgren /* FAPLL powerdown register PWD */ 28163152cbSTony Lindgren #define FAPLL_PWD_OFFSET 4 29163152cbSTony Lindgren 30163152cbSTony Lindgren #define MAX_FAPLL_OUTPUTS 7 31163152cbSTony Lindgren #define FAPLL_MAX_RETRIES 1000 32163152cbSTony Lindgren 33163152cbSTony Lindgren #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw) 34163152cbSTony Lindgren #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw) 35163152cbSTony Lindgren 36163152cbSTony Lindgren /* The bypass bit is inverted on the ddr_pll.. */ 37163152cbSTony Lindgren #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440) 38163152cbSTony Lindgren 39163152cbSTony Lindgren /* 40163152cbSTony Lindgren * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 41163152cbSTony Lindgren * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output. 42163152cbSTony Lindgren */ 43163152cbSTony Lindgren #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c) 44163152cbSTony Lindgren #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8) 45163152cbSTony Lindgren 46163152cbSTony Lindgren /* Synthesizer divider register */ 47163152cbSTony Lindgren #define SYNTH_LDMDIV1 BIT(8) 48163152cbSTony Lindgren 49163152cbSTony Lindgren /* Synthesizer frequency register */ 50163152cbSTony Lindgren #define SYNTH_LDFREQ BIT(31) 51163152cbSTony Lindgren 52163152cbSTony Lindgren struct fapll_data { 53163152cbSTony Lindgren struct clk_hw hw; 54163152cbSTony Lindgren void __iomem *base; 55163152cbSTony Lindgren const char *name; 56163152cbSTony Lindgren struct clk *clk_ref; 57163152cbSTony Lindgren struct clk *clk_bypass; 58163152cbSTony Lindgren struct clk_onecell_data outputs; 59163152cbSTony Lindgren bool bypass_bit_inverted; 60163152cbSTony Lindgren }; 61163152cbSTony Lindgren 62163152cbSTony Lindgren struct fapll_synth { 63163152cbSTony Lindgren struct clk_hw hw; 64163152cbSTony Lindgren struct fapll_data *fd; 65163152cbSTony Lindgren int index; 66163152cbSTony Lindgren void __iomem *freq; 67163152cbSTony Lindgren void __iomem *div; 68163152cbSTony Lindgren const char *name; 69163152cbSTony Lindgren struct clk *clk_pll; 70163152cbSTony Lindgren }; 71163152cbSTony Lindgren 72163152cbSTony Lindgren static bool ti_fapll_clock_is_bypass(struct fapll_data *fd) 73163152cbSTony Lindgren { 74163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 75163152cbSTony Lindgren 76163152cbSTony Lindgren if (fd->bypass_bit_inverted) 77163152cbSTony Lindgren return !(v & FAPLL_MAIN_BP); 78163152cbSTony Lindgren else 79163152cbSTony Lindgren return !!(v & FAPLL_MAIN_BP); 80163152cbSTony Lindgren } 81163152cbSTony Lindgren 82163152cbSTony Lindgren static int ti_fapll_enable(struct clk_hw *hw) 83163152cbSTony Lindgren { 84163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 85163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 86163152cbSTony Lindgren 8703208cc6STony Lindgren v |= FAPLL_MAIN_PLLEN; 88163152cbSTony Lindgren writel_relaxed(v, fd->base); 89163152cbSTony Lindgren 90163152cbSTony Lindgren return 0; 91163152cbSTony Lindgren } 92163152cbSTony Lindgren 93163152cbSTony Lindgren static void ti_fapll_disable(struct clk_hw *hw) 94163152cbSTony Lindgren { 95163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 96163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 97163152cbSTony Lindgren 9803208cc6STony Lindgren v &= ~FAPLL_MAIN_PLLEN; 99163152cbSTony Lindgren writel_relaxed(v, fd->base); 100163152cbSTony Lindgren } 101163152cbSTony Lindgren 102163152cbSTony Lindgren static int ti_fapll_is_enabled(struct clk_hw *hw) 103163152cbSTony Lindgren { 104163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 105163152cbSTony Lindgren u32 v = readl_relaxed(fd->base); 106163152cbSTony Lindgren 10703208cc6STony Lindgren return v & FAPLL_MAIN_PLLEN; 108163152cbSTony Lindgren } 109163152cbSTony Lindgren 110163152cbSTony Lindgren static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 111163152cbSTony Lindgren unsigned long parent_rate) 112163152cbSTony Lindgren { 113163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 114163152cbSTony Lindgren u32 fapll_n, fapll_p, v; 115163152cbSTony Lindgren long long rate; 116163152cbSTony Lindgren 117163152cbSTony Lindgren if (ti_fapll_clock_is_bypass(fd)) 118163152cbSTony Lindgren return parent_rate; 119163152cbSTony Lindgren 120163152cbSTony Lindgren rate = parent_rate; 121163152cbSTony Lindgren 122163152cbSTony Lindgren /* PLL pre-divider is P and multiplier is N */ 123163152cbSTony Lindgren v = readl_relaxed(fd->base); 124163152cbSTony Lindgren fapll_p = (v >> 8) & 0xff; 125163152cbSTony Lindgren if (fapll_p) 126163152cbSTony Lindgren do_div(rate, fapll_p); 127163152cbSTony Lindgren fapll_n = v >> 16; 128163152cbSTony Lindgren if (fapll_n) 129163152cbSTony Lindgren rate *= fapll_n; 130163152cbSTony Lindgren 131163152cbSTony Lindgren return rate; 132163152cbSTony Lindgren } 133163152cbSTony Lindgren 134163152cbSTony Lindgren static u8 ti_fapll_get_parent(struct clk_hw *hw) 135163152cbSTony Lindgren { 136163152cbSTony Lindgren struct fapll_data *fd = to_fapll(hw); 137163152cbSTony Lindgren 138163152cbSTony Lindgren if (ti_fapll_clock_is_bypass(fd)) 139163152cbSTony Lindgren return 1; 140163152cbSTony Lindgren 141163152cbSTony Lindgren return 0; 142163152cbSTony Lindgren } 143163152cbSTony Lindgren 144163152cbSTony Lindgren static struct clk_ops ti_fapll_ops = { 145163152cbSTony Lindgren .enable = ti_fapll_enable, 146163152cbSTony Lindgren .disable = ti_fapll_disable, 147163152cbSTony Lindgren .is_enabled = ti_fapll_is_enabled, 148163152cbSTony Lindgren .recalc_rate = ti_fapll_recalc_rate, 149163152cbSTony Lindgren .get_parent = ti_fapll_get_parent, 150163152cbSTony Lindgren }; 151163152cbSTony Lindgren 152163152cbSTony Lindgren static int ti_fapll_synth_enable(struct clk_hw *hw) 153163152cbSTony Lindgren { 154163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 155163152cbSTony Lindgren u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 156163152cbSTony Lindgren 157163152cbSTony Lindgren v &= ~(1 << synth->index); 158163152cbSTony Lindgren writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 159163152cbSTony Lindgren 160163152cbSTony Lindgren return 0; 161163152cbSTony Lindgren } 162163152cbSTony Lindgren 163163152cbSTony Lindgren static void ti_fapll_synth_disable(struct clk_hw *hw) 164163152cbSTony Lindgren { 165163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 166163152cbSTony Lindgren u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 167163152cbSTony Lindgren 168163152cbSTony Lindgren v |= 1 << synth->index; 169163152cbSTony Lindgren writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 170163152cbSTony Lindgren } 171163152cbSTony Lindgren 172163152cbSTony Lindgren static int ti_fapll_synth_is_enabled(struct clk_hw *hw) 173163152cbSTony Lindgren { 174163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 175163152cbSTony Lindgren u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 176163152cbSTony Lindgren 177163152cbSTony Lindgren return !(v & (1 << synth->index)); 178163152cbSTony Lindgren } 179163152cbSTony Lindgren 180163152cbSTony Lindgren /* 181163152cbSTony Lindgren * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info 182163152cbSTony Lindgren */ 183163152cbSTony Lindgren static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, 184163152cbSTony Lindgren unsigned long parent_rate) 185163152cbSTony Lindgren { 186163152cbSTony Lindgren struct fapll_synth *synth = to_synth(hw); 187163152cbSTony Lindgren u32 synth_div_m; 188163152cbSTony Lindgren long long rate; 189163152cbSTony Lindgren 190163152cbSTony Lindgren /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ 191163152cbSTony Lindgren if (!synth->div) 192163152cbSTony Lindgren return 32768; 193163152cbSTony Lindgren 194163152cbSTony Lindgren /* 195163152cbSTony Lindgren * PLL in bypass sets the synths in bypass mode too. The PLL rate 196163152cbSTony Lindgren * can be also be set to 27MHz, so we can't use parent_rate to 197163152cbSTony Lindgren * check for bypass mode. 198163152cbSTony Lindgren */ 199163152cbSTony Lindgren if (ti_fapll_clock_is_bypass(synth->fd)) 200163152cbSTony Lindgren return parent_rate; 201163152cbSTony Lindgren 202163152cbSTony Lindgren rate = parent_rate; 203163152cbSTony Lindgren 204163152cbSTony Lindgren /* 205163152cbSTony Lindgren * Synth frequency integer and fractional divider. 206163152cbSTony Lindgren * Note that the phase output K is 8, so the result needs 207163152cbSTony Lindgren * to be multiplied by 8. 208163152cbSTony Lindgren */ 209163152cbSTony Lindgren if (synth->freq) { 210163152cbSTony Lindgren u32 v, synth_int_div, synth_frac_div, synth_div_freq; 211163152cbSTony Lindgren 212163152cbSTony Lindgren v = readl_relaxed(synth->freq); 213163152cbSTony Lindgren synth_int_div = (v >> 24) & 0xf; 214163152cbSTony Lindgren synth_frac_div = v & 0xffffff; 215163152cbSTony Lindgren synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; 216163152cbSTony Lindgren rate *= 10000000; 217163152cbSTony Lindgren do_div(rate, synth_div_freq); 218163152cbSTony Lindgren rate *= 8; 219163152cbSTony Lindgren } 220163152cbSTony Lindgren 221163152cbSTony Lindgren /* Synth ost-divider M */ 222163152cbSTony Lindgren synth_div_m = readl_relaxed(synth->div) & 0xff; 223163152cbSTony Lindgren do_div(rate, synth_div_m); 224163152cbSTony Lindgren 225163152cbSTony Lindgren return rate; 226163152cbSTony Lindgren } 227163152cbSTony Lindgren 228163152cbSTony Lindgren static struct clk_ops ti_fapll_synt_ops = { 229163152cbSTony Lindgren .enable = ti_fapll_synth_enable, 230163152cbSTony Lindgren .disable = ti_fapll_synth_disable, 231163152cbSTony Lindgren .is_enabled = ti_fapll_synth_is_enabled, 232163152cbSTony Lindgren .recalc_rate = ti_fapll_synth_recalc_rate, 233163152cbSTony Lindgren }; 234163152cbSTony Lindgren 235163152cbSTony Lindgren static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd, 236163152cbSTony Lindgren void __iomem *freq, 237163152cbSTony Lindgren void __iomem *div, 238163152cbSTony Lindgren int index, 239163152cbSTony Lindgren const char *name, 240163152cbSTony Lindgren const char *parent, 241163152cbSTony Lindgren struct clk *pll_clk) 242163152cbSTony Lindgren { 243163152cbSTony Lindgren struct clk_init_data *init; 244163152cbSTony Lindgren struct fapll_synth *synth; 245163152cbSTony Lindgren 246163152cbSTony Lindgren init = kzalloc(sizeof(*init), GFP_KERNEL); 247163152cbSTony Lindgren if (!init) 248163152cbSTony Lindgren return ERR_PTR(-ENOMEM); 249163152cbSTony Lindgren 250163152cbSTony Lindgren init->ops = &ti_fapll_synt_ops; 251163152cbSTony Lindgren init->name = name; 252163152cbSTony Lindgren init->parent_names = &parent; 253163152cbSTony Lindgren init->num_parents = 1; 254163152cbSTony Lindgren 255163152cbSTony Lindgren synth = kzalloc(sizeof(*synth), GFP_KERNEL); 256163152cbSTony Lindgren if (!synth) 257163152cbSTony Lindgren goto free; 258163152cbSTony Lindgren 259163152cbSTony Lindgren synth->fd = fd; 260163152cbSTony Lindgren synth->index = index; 261163152cbSTony Lindgren synth->freq = freq; 262163152cbSTony Lindgren synth->div = div; 263163152cbSTony Lindgren synth->name = name; 264163152cbSTony Lindgren synth->hw.init = init; 265163152cbSTony Lindgren synth->clk_pll = pll_clk; 266163152cbSTony Lindgren 267163152cbSTony Lindgren return clk_register(NULL, &synth->hw); 268163152cbSTony Lindgren 269163152cbSTony Lindgren free: 270163152cbSTony Lindgren kfree(synth); 271163152cbSTony Lindgren kfree(init); 272163152cbSTony Lindgren 273163152cbSTony Lindgren return ERR_PTR(-ENOMEM); 274163152cbSTony Lindgren } 275163152cbSTony Lindgren 276163152cbSTony Lindgren static void __init ti_fapll_setup(struct device_node *node) 277163152cbSTony Lindgren { 278163152cbSTony Lindgren struct fapll_data *fd; 279163152cbSTony Lindgren struct clk_init_data *init = NULL; 280163152cbSTony Lindgren const char *parent_name[2]; 281163152cbSTony Lindgren struct clk *pll_clk; 282163152cbSTony Lindgren int i; 283163152cbSTony Lindgren 284163152cbSTony Lindgren fd = kzalloc(sizeof(*fd), GFP_KERNEL); 285163152cbSTony Lindgren if (!fd) 286163152cbSTony Lindgren return; 287163152cbSTony Lindgren 288163152cbSTony Lindgren fd->outputs.clks = kzalloc(sizeof(struct clk *) * 289163152cbSTony Lindgren MAX_FAPLL_OUTPUTS + 1, 290163152cbSTony Lindgren GFP_KERNEL); 291163152cbSTony Lindgren if (!fd->outputs.clks) 292163152cbSTony Lindgren goto free; 293163152cbSTony Lindgren 294163152cbSTony Lindgren init = kzalloc(sizeof(*init), GFP_KERNEL); 295163152cbSTony Lindgren if (!init) 296163152cbSTony Lindgren goto free; 297163152cbSTony Lindgren 298163152cbSTony Lindgren init->ops = &ti_fapll_ops; 299163152cbSTony Lindgren init->name = node->name; 300163152cbSTony Lindgren 301163152cbSTony Lindgren init->num_parents = of_clk_get_parent_count(node); 302163152cbSTony Lindgren if (init->num_parents != 2) { 303163152cbSTony Lindgren pr_err("%s must have two parents\n", node->name); 304163152cbSTony Lindgren goto free; 305163152cbSTony Lindgren } 306163152cbSTony Lindgren 307163152cbSTony Lindgren parent_name[0] = of_clk_get_parent_name(node, 0); 308163152cbSTony Lindgren parent_name[1] = of_clk_get_parent_name(node, 1); 309163152cbSTony Lindgren init->parent_names = parent_name; 310163152cbSTony Lindgren 311163152cbSTony Lindgren fd->clk_ref = of_clk_get(node, 0); 312163152cbSTony Lindgren if (IS_ERR(fd->clk_ref)) { 313163152cbSTony Lindgren pr_err("%s could not get clk_ref\n", node->name); 314163152cbSTony Lindgren goto free; 315163152cbSTony Lindgren } 316163152cbSTony Lindgren 317163152cbSTony Lindgren fd->clk_bypass = of_clk_get(node, 1); 318163152cbSTony Lindgren if (IS_ERR(fd->clk_bypass)) { 319163152cbSTony Lindgren pr_err("%s could not get clk_bypass\n", node->name); 320163152cbSTony Lindgren goto free; 321163152cbSTony Lindgren } 322163152cbSTony Lindgren 323163152cbSTony Lindgren fd->base = of_iomap(node, 0); 324163152cbSTony Lindgren if (!fd->base) { 325163152cbSTony Lindgren pr_err("%s could not get IO base\n", node->name); 326163152cbSTony Lindgren goto free; 327163152cbSTony Lindgren } 328163152cbSTony Lindgren 329163152cbSTony Lindgren if (fapll_is_ddr_pll(fd->base)) 330163152cbSTony Lindgren fd->bypass_bit_inverted = true; 331163152cbSTony Lindgren 332163152cbSTony Lindgren fd->name = node->name; 333163152cbSTony Lindgren fd->hw.init = init; 334163152cbSTony Lindgren 335163152cbSTony Lindgren /* Register the parent PLL */ 336163152cbSTony Lindgren pll_clk = clk_register(NULL, &fd->hw); 337163152cbSTony Lindgren if (IS_ERR(pll_clk)) 338163152cbSTony Lindgren goto unmap; 339163152cbSTony Lindgren 340163152cbSTony Lindgren fd->outputs.clks[0] = pll_clk; 341163152cbSTony Lindgren fd->outputs.clk_num++; 342163152cbSTony Lindgren 343163152cbSTony Lindgren /* 344163152cbSTony Lindgren * Set up the child synthesizers starting at index 1 as the 345163152cbSTony Lindgren * PLL output is at index 0. We need to check the clock-indices 346163152cbSTony Lindgren * for numbering in case there are holes in the synth mapping, 347163152cbSTony Lindgren * and then probe the synth register to see if it has a FREQ 348163152cbSTony Lindgren * register available. 349163152cbSTony Lindgren */ 350163152cbSTony Lindgren for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) { 351163152cbSTony Lindgren const char *output_name; 352163152cbSTony Lindgren void __iomem *freq, *div; 353163152cbSTony Lindgren struct clk *synth_clk; 354163152cbSTony Lindgren int output_instance; 355163152cbSTony Lindgren u32 v; 356163152cbSTony Lindgren 357163152cbSTony Lindgren if (of_property_read_string_index(node, "clock-output-names", 358163152cbSTony Lindgren i, &output_name)) 359163152cbSTony Lindgren continue; 360163152cbSTony Lindgren 361163152cbSTony Lindgren if (of_property_read_u32_index(node, "clock-indices", i, 362163152cbSTony Lindgren &output_instance)) 363163152cbSTony Lindgren output_instance = i; 364163152cbSTony Lindgren 365163152cbSTony Lindgren freq = fd->base + (output_instance * 8); 366163152cbSTony Lindgren div = freq + 4; 367163152cbSTony Lindgren 368163152cbSTony Lindgren /* Check for hardwired audio_pll_clk1 */ 369163152cbSTony Lindgren if (is_audio_pll_clk1(freq)) { 370163152cbSTony Lindgren freq = 0; 371163152cbSTony Lindgren div = 0; 372163152cbSTony Lindgren } else { 373163152cbSTony Lindgren /* Does the synthesizer have a FREQ register? */ 374163152cbSTony Lindgren v = readl_relaxed(freq); 375163152cbSTony Lindgren if (!v) 376163152cbSTony Lindgren freq = 0; 377163152cbSTony Lindgren } 378163152cbSTony Lindgren synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, 379163152cbSTony Lindgren output_name, node->name, 380163152cbSTony Lindgren pll_clk); 381163152cbSTony Lindgren if (IS_ERR(synth_clk)) 382163152cbSTony Lindgren continue; 383163152cbSTony Lindgren 384163152cbSTony Lindgren fd->outputs.clks[output_instance] = synth_clk; 385163152cbSTony Lindgren fd->outputs.clk_num++; 386163152cbSTony Lindgren 387163152cbSTony Lindgren clk_register_clkdev(synth_clk, output_name, NULL); 388163152cbSTony Lindgren } 389163152cbSTony Lindgren 390163152cbSTony Lindgren /* Register the child synthesizers as the FAPLL outputs */ 391163152cbSTony Lindgren of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs); 392163152cbSTony Lindgren /* Add clock alias for the outputs */ 393163152cbSTony Lindgren 394163152cbSTony Lindgren kfree(init); 395163152cbSTony Lindgren 396163152cbSTony Lindgren return; 397163152cbSTony Lindgren 398163152cbSTony Lindgren unmap: 399163152cbSTony Lindgren iounmap(fd->base); 400163152cbSTony Lindgren free: 401163152cbSTony Lindgren if (fd->clk_bypass) 402163152cbSTony Lindgren clk_put(fd->clk_bypass); 403163152cbSTony Lindgren if (fd->clk_ref) 404163152cbSTony Lindgren clk_put(fd->clk_ref); 405163152cbSTony Lindgren kfree(fd->outputs.clks); 406163152cbSTony Lindgren kfree(fd); 407163152cbSTony Lindgren kfree(init); 408163152cbSTony Lindgren } 409163152cbSTony Lindgren 410163152cbSTony Lindgren CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup); 411