1 /* 2 * OMAP DPLL clock support 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo <t-kristo@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/slab.h> 21 #include <linux/err.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/clk/ti.h> 25 #include "clock.h" 26 27 #undef pr_fmt 28 #define pr_fmt(fmt) "%s: " fmt, __func__ 29 30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 31 defined(CONFIG_SOC_DRA7XX) 32 static const struct clk_ops dpll_m4xen_ck_ops = { 33 .enable = &omap3_noncore_dpll_enable, 34 .disable = &omap3_noncore_dpll_disable, 35 .recalc_rate = &omap4_dpll_regm4xen_recalc, 36 .round_rate = &omap4_dpll_regm4xen_round_rate, 37 .set_rate = &omap3_noncore_dpll_set_rate, 38 .set_parent = &omap3_noncore_dpll_set_parent, 39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 40 .determine_rate = &omap4_dpll_regm4xen_determine_rate, 41 .get_parent = &omap2_init_dpll_parent, 42 .save_context = &omap3_core_dpll_save_context, 43 .restore_context = &omap3_core_dpll_restore_context, 44 }; 45 #else 46 static const struct clk_ops dpll_m4xen_ck_ops = {}; 47 #endif 48 49 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \ 50 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \ 51 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 52 static const struct clk_ops dpll_core_ck_ops = { 53 .recalc_rate = &omap3_dpll_recalc, 54 .get_parent = &omap2_init_dpll_parent, 55 }; 56 57 static const struct clk_ops dpll_ck_ops = { 58 .enable = &omap3_noncore_dpll_enable, 59 .disable = &omap3_noncore_dpll_disable, 60 .recalc_rate = &omap3_dpll_recalc, 61 .round_rate = &omap2_dpll_round_rate, 62 .set_rate = &omap3_noncore_dpll_set_rate, 63 .set_parent = &omap3_noncore_dpll_set_parent, 64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 65 .determine_rate = &omap3_noncore_dpll_determine_rate, 66 .get_parent = &omap2_init_dpll_parent, 67 .save_context = &omap3_noncore_dpll_save_context, 68 .restore_context = &omap3_noncore_dpll_restore_context, 69 }; 70 71 static const struct clk_ops dpll_no_gate_ck_ops = { 72 .recalc_rate = &omap3_dpll_recalc, 73 .get_parent = &omap2_init_dpll_parent, 74 .round_rate = &omap2_dpll_round_rate, 75 .set_rate = &omap3_noncore_dpll_set_rate, 76 .set_parent = &omap3_noncore_dpll_set_parent, 77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 78 .determine_rate = &omap3_noncore_dpll_determine_rate, 79 .save_context = &omap3_noncore_dpll_save_context, 80 .restore_context = &omap3_noncore_dpll_restore_context 81 }; 82 #else 83 static const struct clk_ops dpll_core_ck_ops = {}; 84 static const struct clk_ops dpll_ck_ops = {}; 85 static const struct clk_ops dpll_no_gate_ck_ops = {}; 86 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {}; 87 #endif 88 89 #ifdef CONFIG_ARCH_OMAP2 90 static const struct clk_ops omap2_dpll_core_ck_ops = { 91 .get_parent = &omap2_init_dpll_parent, 92 .recalc_rate = &omap2_dpllcore_recalc, 93 .round_rate = &omap2_dpll_round_rate, 94 .set_rate = &omap2_reprogram_dpllcore, 95 }; 96 #else 97 static const struct clk_ops omap2_dpll_core_ck_ops = {}; 98 #endif 99 100 #ifdef CONFIG_ARCH_OMAP3 101 static const struct clk_ops omap3_dpll_core_ck_ops = { 102 .get_parent = &omap2_init_dpll_parent, 103 .recalc_rate = &omap3_dpll_recalc, 104 .round_rate = &omap2_dpll_round_rate, 105 }; 106 #else 107 static const struct clk_ops omap3_dpll_core_ck_ops = {}; 108 #endif 109 110 #ifdef CONFIG_ARCH_OMAP3 111 static const struct clk_ops omap3_dpll_ck_ops = { 112 .enable = &omap3_noncore_dpll_enable, 113 .disable = &omap3_noncore_dpll_disable, 114 .get_parent = &omap2_init_dpll_parent, 115 .recalc_rate = &omap3_dpll_recalc, 116 .set_rate = &omap3_noncore_dpll_set_rate, 117 .set_parent = &omap3_noncore_dpll_set_parent, 118 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 119 .determine_rate = &omap3_noncore_dpll_determine_rate, 120 .round_rate = &omap2_dpll_round_rate, 121 }; 122 123 static const struct clk_ops omap3_dpll5_ck_ops = { 124 .enable = &omap3_noncore_dpll_enable, 125 .disable = &omap3_noncore_dpll_disable, 126 .get_parent = &omap2_init_dpll_parent, 127 .recalc_rate = &omap3_dpll_recalc, 128 .set_rate = &omap3_dpll5_set_rate, 129 .set_parent = &omap3_noncore_dpll_set_parent, 130 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 131 .determine_rate = &omap3_noncore_dpll_determine_rate, 132 .round_rate = &omap2_dpll_round_rate, 133 }; 134 135 static const struct clk_ops omap3_dpll_per_ck_ops = { 136 .enable = &omap3_noncore_dpll_enable, 137 .disable = &omap3_noncore_dpll_disable, 138 .get_parent = &omap2_init_dpll_parent, 139 .recalc_rate = &omap3_dpll_recalc, 140 .set_rate = &omap3_dpll4_set_rate, 141 .set_parent = &omap3_noncore_dpll_set_parent, 142 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, 143 .determine_rate = &omap3_noncore_dpll_determine_rate, 144 .round_rate = &omap2_dpll_round_rate, 145 }; 146 #endif 147 148 static const struct clk_ops dpll_x2_ck_ops = { 149 .recalc_rate = &omap3_clkoutx2_recalc, 150 }; 151 152 /** 153 * _register_dpll - low level registration of a DPLL clock 154 * @hw: hardware clock definition for the clock 155 * @node: device node for the clock 156 * 157 * Finalizes DPLL registration process. In case a failure (clk-ref or 158 * clk-bypass is missing), the clock is added to retry list and 159 * the initialization is retried on later stage. 160 */ 161 static void __init _register_dpll(void *user, 162 struct device_node *node) 163 { 164 struct clk_hw *hw = user; 165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 166 struct dpll_data *dd = clk_hw->dpll_data; 167 struct clk *clk; 168 169 clk = of_clk_get(node, 0); 170 if (IS_ERR(clk)) { 171 pr_debug("clk-ref missing for %pOFn, retry later\n", 172 node); 173 if (!ti_clk_retry_init(node, hw, _register_dpll)) 174 return; 175 176 goto cleanup; 177 } 178 179 dd->clk_ref = __clk_get_hw(clk); 180 181 clk = of_clk_get(node, 1); 182 183 if (IS_ERR(clk)) { 184 pr_debug("clk-bypass missing for %pOFn, retry later\n", 185 node); 186 if (!ti_clk_retry_init(node, hw, _register_dpll)) 187 return; 188 189 goto cleanup; 190 } 191 192 dd->clk_bypass = __clk_get_hw(clk); 193 194 /* register the clock */ 195 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 196 197 if (!IS_ERR(clk)) { 198 of_clk_add_provider(node, of_clk_src_simple_get, clk); 199 kfree(clk_hw->hw.init->parent_names); 200 kfree(clk_hw->hw.init); 201 return; 202 } 203 204 cleanup: 205 kfree(clk_hw->dpll_data); 206 kfree(clk_hw->hw.init->parent_names); 207 kfree(clk_hw->hw.init); 208 kfree(clk_hw); 209 } 210 211 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 212 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 213 defined(CONFIG_SOC_AM43XX) 214 /** 215 * _register_dpll_x2 - Registers a DPLLx2 clock 216 * @node: device node for this clock 217 * @ops: clk_ops for this clock 218 * @hw_ops: clk_hw_ops for this clock 219 * 220 * Initializes a DPLL x 2 clock from device tree data. 221 */ 222 static void _register_dpll_x2(struct device_node *node, 223 const struct clk_ops *ops, 224 const struct clk_hw_omap_ops *hw_ops) 225 { 226 struct clk *clk; 227 struct clk_init_data init = { NULL }; 228 struct clk_hw_omap *clk_hw; 229 const char *name = node->name; 230 const char *parent_name; 231 232 parent_name = of_clk_get_parent_name(node, 0); 233 if (!parent_name) { 234 pr_err("%pOFn must have parent\n", node); 235 return; 236 } 237 238 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 239 if (!clk_hw) 240 return; 241 242 clk_hw->ops = hw_ops; 243 clk_hw->hw.init = &init; 244 245 init.name = name; 246 init.ops = ops; 247 init.parent_names = &parent_name; 248 init.num_parents = 1; 249 250 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 251 defined(CONFIG_SOC_DRA7XX) 252 if (hw_ops == &clkhwops_omap4_dpllmx) { 253 int ret; 254 255 /* Check if register defined, if not, drop hw-ops */ 256 ret = of_property_count_elems_of_size(node, "reg", 1); 257 if (ret <= 0) { 258 clk_hw->ops = NULL; 259 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { 260 kfree(clk_hw); 261 return; 262 } 263 } 264 #endif 265 266 /* register the clock */ 267 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); 268 269 if (IS_ERR(clk)) 270 kfree(clk_hw); 271 else 272 of_clk_add_provider(node, of_clk_src_simple_get, clk); 273 } 274 #endif 275 276 /** 277 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks 278 * @node: device node containing the DPLL info 279 * @ops: ops for the DPLL 280 * @ddt: DPLL data template to use 281 * 282 * Initializes a DPLL clock from device tree data. 283 */ 284 static void __init of_ti_dpll_setup(struct device_node *node, 285 const struct clk_ops *ops, 286 const struct dpll_data *ddt) 287 { 288 struct clk_hw_omap *clk_hw = NULL; 289 struct clk_init_data *init = NULL; 290 const char **parent_names = NULL; 291 struct dpll_data *dd = NULL; 292 u8 dpll_mode = 0; 293 294 dd = kzalloc(sizeof(*dd), GFP_KERNEL); 295 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 296 init = kzalloc(sizeof(*init), GFP_KERNEL); 297 if (!dd || !clk_hw || !init) 298 goto cleanup; 299 300 memcpy(dd, ddt, sizeof(*dd)); 301 302 clk_hw->dpll_data = dd; 303 clk_hw->ops = &clkhwops_omap3_dpll; 304 clk_hw->hw.init = init; 305 306 init->name = node->name; 307 init->ops = ops; 308 309 init->num_parents = of_clk_get_parent_count(node); 310 if (!init->num_parents) { 311 pr_err("%pOFn must have parent(s)\n", node); 312 goto cleanup; 313 } 314 315 parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); 316 if (!parent_names) 317 goto cleanup; 318 319 of_clk_parent_fill(node, parent_names, init->num_parents); 320 321 init->parent_names = parent_names; 322 323 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) 324 goto cleanup; 325 326 /* 327 * Special case for OMAP2 DPLL, register order is different due to 328 * missing idlest_reg, also clkhwops is different. Detected from 329 * missing idlest_mask. 330 */ 331 if (!dd->idlest_mask) { 332 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) 333 goto cleanup; 334 #ifdef CONFIG_ARCH_OMAP2 335 clk_hw->ops = &clkhwops_omap2xxx_dpll; 336 omap2xxx_clkt_dpllcore_init(&clk_hw->hw); 337 #endif 338 } else { 339 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) 340 goto cleanup; 341 342 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) 343 goto cleanup; 344 } 345 346 if (dd->autoidle_mask) { 347 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) 348 goto cleanup; 349 } 350 351 if (of_property_read_bool(node, "ti,low-power-stop")) 352 dpll_mode |= 1 << DPLL_LOW_POWER_STOP; 353 354 if (of_property_read_bool(node, "ti,low-power-bypass")) 355 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; 356 357 if (of_property_read_bool(node, "ti,lock")) 358 dpll_mode |= 1 << DPLL_LOCKED; 359 360 if (dpll_mode) 361 dd->modes = dpll_mode; 362 363 _register_dpll(&clk_hw->hw, node); 364 return; 365 366 cleanup: 367 kfree(dd); 368 kfree(parent_names); 369 kfree(init); 370 kfree(clk_hw); 371 } 372 373 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 374 defined(CONFIG_SOC_DRA7XX) 375 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 376 { 377 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 378 } 379 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 380 of_ti_omap4_dpll_x2_setup); 381 #endif 382 383 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 384 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 385 { 386 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 387 } 388 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 389 of_ti_am3_dpll_x2_setup); 390 #endif 391 392 #ifdef CONFIG_ARCH_OMAP3 393 static void __init of_ti_omap3_dpll_setup(struct device_node *node) 394 { 395 const struct dpll_data dd = { 396 .idlest_mask = 0x1, 397 .enable_mask = 0x7, 398 .autoidle_mask = 0x7, 399 .mult_mask = 0x7ff << 8, 400 .div1_mask = 0x7f, 401 .max_multiplier = 2047, 402 .max_divider = 128, 403 .min_divider = 1, 404 .freqsel_mask = 0xf0, 405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 406 }; 407 408 if ((of_machine_is_compatible("ti,omap3630") || 409 of_machine_is_compatible("ti,omap36xx")) && 410 of_node_name_eq(node, "dpll5_ck")) 411 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd); 412 else 413 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd); 414 } 415 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", 416 of_ti_omap3_dpll_setup); 417 418 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) 419 { 420 const struct dpll_data dd = { 421 .idlest_mask = 0x1, 422 .enable_mask = 0x7, 423 .autoidle_mask = 0x7, 424 .mult_mask = 0x7ff << 16, 425 .div1_mask = 0x7f << 8, 426 .max_multiplier = 2047, 427 .max_divider = 128, 428 .min_divider = 1, 429 .freqsel_mask = 0xf0, 430 }; 431 432 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd); 433 } 434 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", 435 of_ti_omap3_core_dpll_setup); 436 437 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) 438 { 439 const struct dpll_data dd = { 440 .idlest_mask = 0x1 << 1, 441 .enable_mask = 0x7 << 16, 442 .autoidle_mask = 0x7 << 3, 443 .mult_mask = 0x7ff << 8, 444 .div1_mask = 0x7f, 445 .max_multiplier = 2047, 446 .max_divider = 128, 447 .min_divider = 1, 448 .freqsel_mask = 0xf00000, 449 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 450 }; 451 452 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 453 } 454 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", 455 of_ti_omap3_per_dpll_setup); 456 457 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) 458 { 459 const struct dpll_data dd = { 460 .idlest_mask = 0x1 << 1, 461 .enable_mask = 0x7 << 16, 462 .autoidle_mask = 0x7 << 3, 463 .mult_mask = 0xfff << 8, 464 .div1_mask = 0x7f, 465 .max_multiplier = 4095, 466 .max_divider = 128, 467 .min_divider = 1, 468 .sddiv_mask = 0xff << 24, 469 .dco_mask = 0xe << 20, 470 .flags = DPLL_J_TYPE, 471 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 472 }; 473 474 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 475 } 476 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", 477 of_ti_omap3_per_jtype_dpll_setup); 478 #endif 479 480 static void __init of_ti_omap4_dpll_setup(struct device_node *node) 481 { 482 const struct dpll_data dd = { 483 .idlest_mask = 0x1, 484 .enable_mask = 0x7, 485 .autoidle_mask = 0x7, 486 .mult_mask = 0x7ff << 8, 487 .div1_mask = 0x7f, 488 .max_multiplier = 2047, 489 .max_divider = 128, 490 .min_divider = 1, 491 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 492 }; 493 494 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 495 } 496 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", 497 of_ti_omap4_dpll_setup); 498 499 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) 500 { 501 const struct dpll_data dd = { 502 .idlest_mask = 0x1, 503 .enable_mask = 0x7, 504 .autoidle_mask = 0x7, 505 .mult_mask = 0x7ff << 8, 506 .div1_mask = 0x7f, 507 .max_multiplier = 2047, 508 .max_divider = 128, 509 .dcc_mask = BIT(22), 510 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ 511 .min_divider = 1, 512 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 513 }; 514 515 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 516 } 517 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", 518 of_ti_omap5_mpu_dpll_setup); 519 520 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) 521 { 522 const struct dpll_data dd = { 523 .idlest_mask = 0x1, 524 .enable_mask = 0x7, 525 .autoidle_mask = 0x7, 526 .mult_mask = 0x7ff << 8, 527 .div1_mask = 0x7f, 528 .max_multiplier = 2047, 529 .max_divider = 128, 530 .min_divider = 1, 531 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 532 }; 533 534 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 535 } 536 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", 537 of_ti_omap4_core_dpll_setup); 538 539 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 540 defined(CONFIG_SOC_DRA7XX) 541 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) 542 { 543 const struct dpll_data dd = { 544 .idlest_mask = 0x1, 545 .enable_mask = 0x7, 546 .autoidle_mask = 0x7, 547 .mult_mask = 0x7ff << 8, 548 .div1_mask = 0x7f, 549 .max_multiplier = 2047, 550 .max_divider = 128, 551 .min_divider = 1, 552 .m4xen_mask = 0x800, 553 .lpmode_mask = 1 << 10, 554 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 555 }; 556 557 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 558 } 559 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", 560 of_ti_omap4_m4xen_dpll_setup); 561 562 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) 563 { 564 const struct dpll_data dd = { 565 .idlest_mask = 0x1, 566 .enable_mask = 0x7, 567 .autoidle_mask = 0x7, 568 .mult_mask = 0xfff << 8, 569 .div1_mask = 0xff, 570 .max_multiplier = 4095, 571 .max_divider = 256, 572 .min_divider = 1, 573 .sddiv_mask = 0xff << 24, 574 .flags = DPLL_J_TYPE, 575 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 576 }; 577 578 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 579 } 580 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", 581 of_ti_omap4_jtype_dpll_setup); 582 #endif 583 584 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) 585 { 586 const struct dpll_data dd = { 587 .idlest_mask = 0x1, 588 .enable_mask = 0x7, 589 .mult_mask = 0x7ff << 8, 590 .div1_mask = 0x7f, 591 .max_multiplier = 2047, 592 .max_divider = 128, 593 .min_divider = 1, 594 .max_rate = 1000000000, 595 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 596 }; 597 598 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 599 } 600 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", 601 of_ti_am3_no_gate_dpll_setup); 602 603 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) 604 { 605 const struct dpll_data dd = { 606 .idlest_mask = 0x1, 607 .enable_mask = 0x7, 608 .mult_mask = 0x7ff << 8, 609 .div1_mask = 0x7f, 610 .max_multiplier = 4095, 611 .max_divider = 256, 612 .min_divider = 2, 613 .flags = DPLL_J_TYPE, 614 .max_rate = 2000000000, 615 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 616 }; 617 618 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 619 } 620 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", 621 of_ti_am3_jtype_dpll_setup); 622 623 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) 624 { 625 const struct dpll_data dd = { 626 .idlest_mask = 0x1, 627 .enable_mask = 0x7, 628 .mult_mask = 0x7ff << 8, 629 .div1_mask = 0x7f, 630 .max_multiplier = 2047, 631 .max_divider = 128, 632 .min_divider = 1, 633 .max_rate = 2000000000, 634 .flags = DPLL_J_TYPE, 635 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 636 }; 637 638 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 639 } 640 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, 641 "ti,am3-dpll-no-gate-j-type-clock", 642 of_ti_am3_no_gate_jtype_dpll_setup); 643 644 static void __init of_ti_am3_dpll_setup(struct device_node *node) 645 { 646 const struct dpll_data dd = { 647 .idlest_mask = 0x1, 648 .enable_mask = 0x7, 649 .mult_mask = 0x7ff << 8, 650 .div1_mask = 0x7f, 651 .max_multiplier = 2047, 652 .max_divider = 128, 653 .min_divider = 1, 654 .max_rate = 1000000000, 655 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 656 }; 657 658 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 659 } 660 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); 661 662 static void __init of_ti_am3_core_dpll_setup(struct device_node *node) 663 { 664 const struct dpll_data dd = { 665 .idlest_mask = 0x1, 666 .enable_mask = 0x7, 667 .mult_mask = 0x7ff << 8, 668 .div1_mask = 0x7f, 669 .max_multiplier = 2047, 670 .max_divider = 128, 671 .min_divider = 1, 672 .max_rate = 1000000000, 673 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 674 }; 675 676 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 677 } 678 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", 679 of_ti_am3_core_dpll_setup); 680 681 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node) 682 { 683 const struct dpll_data dd = { 684 .enable_mask = 0x3, 685 .mult_mask = 0x3ff << 12, 686 .div1_mask = 0xf << 8, 687 .max_divider = 16, 688 .min_divider = 1, 689 }; 690 691 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd); 692 } 693 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock", 694 of_ti_omap2_core_dpll_setup); 695