1 /* 2 * OMAP DPLL clock support 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo <t-kristo@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/slab.h> 21 #include <linux/err.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/clk/ti.h> 25 #include "clock.h" 26 27 #undef pr_fmt 28 #define pr_fmt(fmt) "%s: " fmt, __func__ 29 30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 31 defined(CONFIG_SOC_DRA7XX) 32 static const struct clk_ops dpll_m4xen_ck_ops = { 33 .enable = &omap3_noncore_dpll_enable, 34 .disable = &omap3_noncore_dpll_disable, 35 .recalc_rate = &omap4_dpll_regm4xen_recalc, 36 .round_rate = &omap4_dpll_regm4xen_round_rate, 37 .set_rate = &omap3_noncore_dpll_set_rate, 38 .set_parent = &omap3_noncore_dpll_set_parent, 39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 40 .determine_rate = &omap4_dpll_regm4xen_determine_rate, 41 .get_parent = &omap2_init_dpll_parent, 42 .save_context = &omap3_core_dpll_save_context, 43 .restore_context = &omap3_core_dpll_restore_context, 44 }; 45 #else 46 static const struct clk_ops dpll_m4xen_ck_ops = {}; 47 #endif 48 49 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \ 50 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \ 51 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 52 static const struct clk_ops dpll_core_ck_ops = { 53 .recalc_rate = &omap3_dpll_recalc, 54 .get_parent = &omap2_init_dpll_parent, 55 }; 56 57 static const struct clk_ops dpll_ck_ops = { 58 .enable = &omap3_noncore_dpll_enable, 59 .disable = &omap3_noncore_dpll_disable, 60 .recalc_rate = &omap3_dpll_recalc, 61 .round_rate = &omap2_dpll_round_rate, 62 .set_rate = &omap3_noncore_dpll_set_rate, 63 .set_parent = &omap3_noncore_dpll_set_parent, 64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 65 .determine_rate = &omap3_noncore_dpll_determine_rate, 66 .get_parent = &omap2_init_dpll_parent, 67 .save_context = &omap3_noncore_dpll_save_context, 68 .restore_context = &omap3_noncore_dpll_restore_context, 69 }; 70 71 static const struct clk_ops dpll_no_gate_ck_ops = { 72 .recalc_rate = &omap3_dpll_recalc, 73 .get_parent = &omap2_init_dpll_parent, 74 .round_rate = &omap2_dpll_round_rate, 75 .set_rate = &omap3_noncore_dpll_set_rate, 76 .set_parent = &omap3_noncore_dpll_set_parent, 77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 78 .determine_rate = &omap3_noncore_dpll_determine_rate, 79 .save_context = &omap3_noncore_dpll_save_context, 80 .restore_context = &omap3_noncore_dpll_restore_context 81 }; 82 #else 83 static const struct clk_ops dpll_core_ck_ops = {}; 84 static const struct clk_ops dpll_ck_ops = {}; 85 static const struct clk_ops dpll_no_gate_ck_ops = {}; 86 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {}; 87 #endif 88 89 #ifdef CONFIG_ARCH_OMAP2 90 static const struct clk_ops omap2_dpll_core_ck_ops = { 91 .get_parent = &omap2_init_dpll_parent, 92 .recalc_rate = &omap2_dpllcore_recalc, 93 .round_rate = &omap2_dpll_round_rate, 94 .set_rate = &omap2_reprogram_dpllcore, 95 }; 96 #else 97 static const struct clk_ops omap2_dpll_core_ck_ops = {}; 98 #endif 99 100 #ifdef CONFIG_ARCH_OMAP3 101 static const struct clk_ops omap3_dpll_core_ck_ops = { 102 .get_parent = &omap2_init_dpll_parent, 103 .recalc_rate = &omap3_dpll_recalc, 104 .round_rate = &omap2_dpll_round_rate, 105 }; 106 #else 107 static const struct clk_ops omap3_dpll_core_ck_ops = {}; 108 #endif 109 110 #ifdef CONFIG_ARCH_OMAP3 111 static const struct clk_ops omap3_dpll_ck_ops = { 112 .enable = &omap3_noncore_dpll_enable, 113 .disable = &omap3_noncore_dpll_disable, 114 .get_parent = &omap2_init_dpll_parent, 115 .recalc_rate = &omap3_dpll_recalc, 116 .set_rate = &omap3_noncore_dpll_set_rate, 117 .set_parent = &omap3_noncore_dpll_set_parent, 118 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 119 .determine_rate = &omap3_noncore_dpll_determine_rate, 120 .round_rate = &omap2_dpll_round_rate, 121 }; 122 123 static const struct clk_ops omap3_dpll5_ck_ops = { 124 .enable = &omap3_noncore_dpll_enable, 125 .disable = &omap3_noncore_dpll_disable, 126 .get_parent = &omap2_init_dpll_parent, 127 .recalc_rate = &omap3_dpll_recalc, 128 .set_rate = &omap3_dpll5_set_rate, 129 .set_parent = &omap3_noncore_dpll_set_parent, 130 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 131 .determine_rate = &omap3_noncore_dpll_determine_rate, 132 .round_rate = &omap2_dpll_round_rate, 133 }; 134 135 static const struct clk_ops omap3_dpll_per_ck_ops = { 136 .enable = &omap3_noncore_dpll_enable, 137 .disable = &omap3_noncore_dpll_disable, 138 .get_parent = &omap2_init_dpll_parent, 139 .recalc_rate = &omap3_dpll_recalc, 140 .set_rate = &omap3_dpll4_set_rate, 141 .set_parent = &omap3_noncore_dpll_set_parent, 142 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, 143 .determine_rate = &omap3_noncore_dpll_determine_rate, 144 .round_rate = &omap2_dpll_round_rate, 145 }; 146 #endif 147 148 static const struct clk_ops dpll_x2_ck_ops = { 149 .recalc_rate = &omap3_clkoutx2_recalc, 150 }; 151 152 /** 153 * _register_dpll - low level registration of a DPLL clock 154 * @user: pointer to the hardware clock definition for the clock 155 * @node: device node for the clock 156 * 157 * Finalizes DPLL registration process. In case a failure (clk-ref or 158 * clk-bypass is missing), the clock is added to retry list and 159 * the initialization is retried on later stage. 160 */ 161 static void __init _register_dpll(void *user, 162 struct device_node *node) 163 { 164 struct clk_hw *hw = user; 165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 166 struct dpll_data *dd = clk_hw->dpll_data; 167 struct clk *clk; 168 const struct clk_init_data *init = hw->init; 169 170 clk = of_clk_get(node, 0); 171 if (IS_ERR(clk)) { 172 pr_debug("clk-ref missing for %pOFn, retry later\n", 173 node); 174 if (!ti_clk_retry_init(node, hw, _register_dpll)) 175 return; 176 177 goto cleanup; 178 } 179 180 dd->clk_ref = __clk_get_hw(clk); 181 182 clk = of_clk_get(node, 1); 183 184 if (IS_ERR(clk)) { 185 pr_debug("clk-bypass missing for %pOFn, retry later\n", 186 node); 187 if (!ti_clk_retry_init(node, hw, _register_dpll)) 188 return; 189 190 goto cleanup; 191 } 192 193 dd->clk_bypass = __clk_get_hw(clk); 194 195 /* register the clock */ 196 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 197 198 if (!IS_ERR(clk)) { 199 of_clk_add_provider(node, of_clk_src_simple_get, clk); 200 kfree(init->parent_names); 201 kfree(init); 202 return; 203 } 204 205 cleanup: 206 kfree(clk_hw->dpll_data); 207 kfree(init->parent_names); 208 kfree(init); 209 kfree(clk_hw); 210 } 211 212 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 213 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 214 defined(CONFIG_SOC_AM43XX) 215 /** 216 * _register_dpll_x2 - Registers a DPLLx2 clock 217 * @node: device node for this clock 218 * @ops: clk_ops for this clock 219 * @hw_ops: clk_hw_ops for this clock 220 * 221 * Initializes a DPLL x 2 clock from device tree data. 222 */ 223 static void _register_dpll_x2(struct device_node *node, 224 const struct clk_ops *ops, 225 const struct clk_hw_omap_ops *hw_ops) 226 { 227 struct clk *clk; 228 struct clk_init_data init = { NULL }; 229 struct clk_hw_omap *clk_hw; 230 const char *name = node->name; 231 const char *parent_name; 232 233 parent_name = of_clk_get_parent_name(node, 0); 234 if (!parent_name) { 235 pr_err("%pOFn must have parent\n", node); 236 return; 237 } 238 239 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 240 if (!clk_hw) 241 return; 242 243 clk_hw->ops = hw_ops; 244 clk_hw->hw.init = &init; 245 246 init.name = name; 247 init.ops = ops; 248 init.parent_names = &parent_name; 249 init.num_parents = 1; 250 251 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 252 defined(CONFIG_SOC_DRA7XX) 253 if (hw_ops == &clkhwops_omap4_dpllmx) { 254 int ret; 255 256 /* Check if register defined, if not, drop hw-ops */ 257 ret = of_property_count_elems_of_size(node, "reg", 1); 258 if (ret <= 0) { 259 clk_hw->ops = NULL; 260 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { 261 kfree(clk_hw); 262 return; 263 } 264 } 265 #endif 266 267 /* register the clock */ 268 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); 269 270 if (IS_ERR(clk)) 271 kfree(clk_hw); 272 else 273 of_clk_add_provider(node, of_clk_src_simple_get, clk); 274 } 275 #endif 276 277 /** 278 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks 279 * @node: device node containing the DPLL info 280 * @ops: ops for the DPLL 281 * @ddt: DPLL data template to use 282 * 283 * Initializes a DPLL clock from device tree data. 284 */ 285 static void __init of_ti_dpll_setup(struct device_node *node, 286 const struct clk_ops *ops, 287 const struct dpll_data *ddt) 288 { 289 struct clk_hw_omap *clk_hw = NULL; 290 struct clk_init_data *init = NULL; 291 const char **parent_names = NULL; 292 struct dpll_data *dd = NULL; 293 int ssc_clk_index; 294 u8 dpll_mode = 0; 295 u32 min_div; 296 297 dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL); 298 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 299 init = kzalloc(sizeof(*init), GFP_KERNEL); 300 if (!dd || !clk_hw || !init) 301 goto cleanup; 302 303 clk_hw->dpll_data = dd; 304 clk_hw->ops = &clkhwops_omap3_dpll; 305 clk_hw->hw.init = init; 306 307 init->name = node->name; 308 init->ops = ops; 309 310 init->num_parents = of_clk_get_parent_count(node); 311 if (!init->num_parents) { 312 pr_err("%pOFn must have parent(s)\n", node); 313 goto cleanup; 314 } 315 316 parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); 317 if (!parent_names) 318 goto cleanup; 319 320 of_clk_parent_fill(node, parent_names, init->num_parents); 321 322 init->parent_names = parent_names; 323 324 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) 325 goto cleanup; 326 327 /* 328 * Special case for OMAP2 DPLL, register order is different due to 329 * missing idlest_reg, also clkhwops is different. Detected from 330 * missing idlest_mask. 331 */ 332 if (!dd->idlest_mask) { 333 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) 334 goto cleanup; 335 #ifdef CONFIG_ARCH_OMAP2 336 clk_hw->ops = &clkhwops_omap2xxx_dpll; 337 omap2xxx_clkt_dpllcore_init(&clk_hw->hw); 338 #endif 339 } else { 340 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) 341 goto cleanup; 342 343 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) 344 goto cleanup; 345 } 346 347 if (dd->autoidle_mask) { 348 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) 349 goto cleanup; 350 351 ssc_clk_index = 4; 352 } else { 353 ssc_clk_index = 3; 354 } 355 356 if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask && 357 dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) { 358 if (ti_clk_get_reg_addr(node, ssc_clk_index++, 359 &dd->ssc_deltam_reg)) 360 goto cleanup; 361 362 if (ti_clk_get_reg_addr(node, ssc_clk_index++, 363 &dd->ssc_modfreq_reg)) 364 goto cleanup; 365 366 of_property_read_u32(node, "ti,ssc-modfreq-hz", 367 &dd->ssc_modfreq); 368 of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam); 369 dd->ssc_downspread = 370 of_property_read_bool(node, "ti,ssc-downspread"); 371 } 372 373 if (of_property_read_bool(node, "ti,low-power-stop")) 374 dpll_mode |= 1 << DPLL_LOW_POWER_STOP; 375 376 if (of_property_read_bool(node, "ti,low-power-bypass")) 377 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; 378 379 if (of_property_read_bool(node, "ti,lock")) 380 dpll_mode |= 1 << DPLL_LOCKED; 381 382 if (!of_property_read_u32(node, "ti,min-div", &min_div) && 383 min_div > dd->min_divider) 384 dd->min_divider = min_div; 385 386 if (dpll_mode) 387 dd->modes = dpll_mode; 388 389 _register_dpll(&clk_hw->hw, node); 390 return; 391 392 cleanup: 393 kfree(dd); 394 kfree(parent_names); 395 kfree(init); 396 kfree(clk_hw); 397 } 398 399 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 400 defined(CONFIG_SOC_DRA7XX) 401 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 402 { 403 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 404 } 405 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 406 of_ti_omap4_dpll_x2_setup); 407 #endif 408 409 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 410 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 411 { 412 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 413 } 414 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 415 of_ti_am3_dpll_x2_setup); 416 #endif 417 418 #ifdef CONFIG_ARCH_OMAP3 419 static void __init of_ti_omap3_dpll_setup(struct device_node *node) 420 { 421 const struct dpll_data dd = { 422 .idlest_mask = 0x1, 423 .enable_mask = 0x7, 424 .autoidle_mask = 0x7, 425 .mult_mask = 0x7ff << 8, 426 .div1_mask = 0x7f, 427 .max_multiplier = 2047, 428 .max_divider = 128, 429 .min_divider = 1, 430 .freqsel_mask = 0xf0, 431 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 432 }; 433 434 if ((of_machine_is_compatible("ti,omap3630") || 435 of_machine_is_compatible("ti,omap36xx")) && 436 of_node_name_eq(node, "dpll5_ck")) 437 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd); 438 else 439 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd); 440 } 441 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", 442 of_ti_omap3_dpll_setup); 443 444 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) 445 { 446 const struct dpll_data dd = { 447 .idlest_mask = 0x1, 448 .enable_mask = 0x7, 449 .autoidle_mask = 0x7, 450 .mult_mask = 0x7ff << 16, 451 .div1_mask = 0x7f << 8, 452 .max_multiplier = 2047, 453 .max_divider = 128, 454 .min_divider = 1, 455 .freqsel_mask = 0xf0, 456 }; 457 458 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd); 459 } 460 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", 461 of_ti_omap3_core_dpll_setup); 462 463 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) 464 { 465 const struct dpll_data dd = { 466 .idlest_mask = 0x1 << 1, 467 .enable_mask = 0x7 << 16, 468 .autoidle_mask = 0x7 << 3, 469 .mult_mask = 0x7ff << 8, 470 .div1_mask = 0x7f, 471 .max_multiplier = 2047, 472 .max_divider = 128, 473 .min_divider = 1, 474 .freqsel_mask = 0xf00000, 475 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 476 }; 477 478 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 479 } 480 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", 481 of_ti_omap3_per_dpll_setup); 482 483 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) 484 { 485 const struct dpll_data dd = { 486 .idlest_mask = 0x1 << 1, 487 .enable_mask = 0x7 << 16, 488 .autoidle_mask = 0x7 << 3, 489 .mult_mask = 0xfff << 8, 490 .div1_mask = 0x7f, 491 .max_multiplier = 4095, 492 .max_divider = 128, 493 .min_divider = 1, 494 .sddiv_mask = 0xff << 24, 495 .dco_mask = 0xe << 20, 496 .flags = DPLL_J_TYPE, 497 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 498 }; 499 500 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 501 } 502 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", 503 of_ti_omap3_per_jtype_dpll_setup); 504 #endif 505 506 static void __init of_ti_omap4_dpll_setup(struct device_node *node) 507 { 508 const struct dpll_data dd = { 509 .idlest_mask = 0x1, 510 .enable_mask = 0x7, 511 .autoidle_mask = 0x7, 512 .mult_mask = 0x7ff << 8, 513 .div1_mask = 0x7f, 514 .max_multiplier = 2047, 515 .max_divider = 128, 516 .min_divider = 1, 517 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 518 }; 519 520 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 521 } 522 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", 523 of_ti_omap4_dpll_setup); 524 525 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) 526 { 527 const struct dpll_data dd = { 528 .idlest_mask = 0x1, 529 .enable_mask = 0x7, 530 .autoidle_mask = 0x7, 531 .mult_mask = 0x7ff << 8, 532 .div1_mask = 0x7f, 533 .max_multiplier = 2047, 534 .max_divider = 128, 535 .dcc_mask = BIT(22), 536 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ 537 .min_divider = 1, 538 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 539 }; 540 541 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 542 } 543 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", 544 of_ti_omap5_mpu_dpll_setup); 545 546 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) 547 { 548 const struct dpll_data dd = { 549 .idlest_mask = 0x1, 550 .enable_mask = 0x7, 551 .autoidle_mask = 0x7, 552 .mult_mask = 0x7ff << 8, 553 .div1_mask = 0x7f, 554 .max_multiplier = 2047, 555 .max_divider = 128, 556 .min_divider = 1, 557 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 558 }; 559 560 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 561 } 562 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", 563 of_ti_omap4_core_dpll_setup); 564 565 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 566 defined(CONFIG_SOC_DRA7XX) 567 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) 568 { 569 const struct dpll_data dd = { 570 .idlest_mask = 0x1, 571 .enable_mask = 0x7, 572 .autoidle_mask = 0x7, 573 .mult_mask = 0x7ff << 8, 574 .div1_mask = 0x7f, 575 .max_multiplier = 2047, 576 .max_divider = 128, 577 .min_divider = 1, 578 .m4xen_mask = 0x800, 579 .lpmode_mask = 1 << 10, 580 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 581 }; 582 583 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 584 } 585 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", 586 of_ti_omap4_m4xen_dpll_setup); 587 588 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) 589 { 590 const struct dpll_data dd = { 591 .idlest_mask = 0x1, 592 .enable_mask = 0x7, 593 .autoidle_mask = 0x7, 594 .mult_mask = 0xfff << 8, 595 .div1_mask = 0xff, 596 .max_multiplier = 4095, 597 .max_divider = 256, 598 .min_divider = 1, 599 .sddiv_mask = 0xff << 24, 600 .flags = DPLL_J_TYPE, 601 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 602 }; 603 604 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 605 } 606 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", 607 of_ti_omap4_jtype_dpll_setup); 608 #endif 609 610 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) 611 { 612 const struct dpll_data dd = { 613 .idlest_mask = 0x1, 614 .enable_mask = 0x7, 615 .ssc_enable_mask = 0x1 << 12, 616 .ssc_downspread_mask = 0x1 << 14, 617 .mult_mask = 0x7ff << 8, 618 .div1_mask = 0x7f, 619 .ssc_deltam_int_mask = 0x3 << 18, 620 .ssc_deltam_frac_mask = 0x3ffff, 621 .ssc_modfreq_mant_mask = 0x7f, 622 .ssc_modfreq_exp_mask = 0x7 << 8, 623 .max_multiplier = 2047, 624 .max_divider = 128, 625 .min_divider = 1, 626 .max_rate = 1000000000, 627 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 628 }; 629 630 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 631 } 632 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", 633 of_ti_am3_no_gate_dpll_setup); 634 635 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) 636 { 637 const struct dpll_data dd = { 638 .idlest_mask = 0x1, 639 .enable_mask = 0x7, 640 .mult_mask = 0x7ff << 8, 641 .div1_mask = 0x7f, 642 .max_multiplier = 4095, 643 .max_divider = 256, 644 .min_divider = 2, 645 .flags = DPLL_J_TYPE, 646 .max_rate = 2000000000, 647 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 648 }; 649 650 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 651 } 652 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", 653 of_ti_am3_jtype_dpll_setup); 654 655 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) 656 { 657 const struct dpll_data dd = { 658 .idlest_mask = 0x1, 659 .enable_mask = 0x7, 660 .mult_mask = 0x7ff << 8, 661 .div1_mask = 0x7f, 662 .max_multiplier = 2047, 663 .max_divider = 128, 664 .min_divider = 1, 665 .max_rate = 2000000000, 666 .flags = DPLL_J_TYPE, 667 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 668 }; 669 670 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 671 } 672 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, 673 "ti,am3-dpll-no-gate-j-type-clock", 674 of_ti_am3_no_gate_jtype_dpll_setup); 675 676 static void __init of_ti_am3_dpll_setup(struct device_node *node) 677 { 678 const struct dpll_data dd = { 679 .idlest_mask = 0x1, 680 .enable_mask = 0x7, 681 .ssc_enable_mask = 0x1 << 12, 682 .ssc_downspread_mask = 0x1 << 14, 683 .mult_mask = 0x7ff << 8, 684 .div1_mask = 0x7f, 685 .ssc_deltam_int_mask = 0x3 << 18, 686 .ssc_deltam_frac_mask = 0x3ffff, 687 .ssc_modfreq_mant_mask = 0x7f, 688 .ssc_modfreq_exp_mask = 0x7 << 8, 689 .max_multiplier = 2047, 690 .max_divider = 128, 691 .min_divider = 1, 692 .max_rate = 1000000000, 693 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 694 }; 695 696 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 697 } 698 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); 699 700 static void __init of_ti_am3_core_dpll_setup(struct device_node *node) 701 { 702 const struct dpll_data dd = { 703 .idlest_mask = 0x1, 704 .enable_mask = 0x7, 705 .mult_mask = 0x7ff << 8, 706 .div1_mask = 0x7f, 707 .max_multiplier = 2047, 708 .max_divider = 128, 709 .min_divider = 1, 710 .max_rate = 1000000000, 711 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 712 }; 713 714 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 715 } 716 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", 717 of_ti_am3_core_dpll_setup); 718 719 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node) 720 { 721 const struct dpll_data dd = { 722 .enable_mask = 0x3, 723 .mult_mask = 0x3ff << 12, 724 .div1_mask = 0xf << 8, 725 .max_divider = 16, 726 .min_divider = 1, 727 }; 728 729 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd); 730 } 731 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock", 732 of_ti_omap2_core_dpll_setup); 733