1 /* 2 * TI Divider Clock 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo <t-kristo@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk-provider.h> 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/clk/ti.h> 24 #include "clock.h" 25 26 #undef pr_fmt 27 #define pr_fmt(fmt) "%s: " fmt, __func__ 28 29 #define div_mask(d) ((1 << ((d)->width)) - 1) 30 31 static unsigned int _get_table_maxdiv(const struct clk_div_table *table) 32 { 33 unsigned int maxdiv = 0; 34 const struct clk_div_table *clkt; 35 36 for (clkt = table; clkt->div; clkt++) 37 if (clkt->div > maxdiv) 38 maxdiv = clkt->div; 39 return maxdiv; 40 } 41 42 static unsigned int _get_maxdiv(struct clk_divider *divider) 43 { 44 if (divider->flags & CLK_DIVIDER_ONE_BASED) 45 return div_mask(divider); 46 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 47 return 1 << div_mask(divider); 48 if (divider->table) 49 return _get_table_maxdiv(divider->table); 50 return div_mask(divider) + 1; 51 } 52 53 static unsigned int _get_table_div(const struct clk_div_table *table, 54 unsigned int val) 55 { 56 const struct clk_div_table *clkt; 57 58 for (clkt = table; clkt->div; clkt++) 59 if (clkt->val == val) 60 return clkt->div; 61 return 0; 62 } 63 64 static unsigned int _get_div(struct clk_divider *divider, unsigned int val) 65 { 66 if (divider->flags & CLK_DIVIDER_ONE_BASED) 67 return val; 68 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 69 return 1 << val; 70 if (divider->table) 71 return _get_table_div(divider->table, val); 72 return val + 1; 73 } 74 75 static unsigned int _get_table_val(const struct clk_div_table *table, 76 unsigned int div) 77 { 78 const struct clk_div_table *clkt; 79 80 for (clkt = table; clkt->div; clkt++) 81 if (clkt->div == div) 82 return clkt->val; 83 return 0; 84 } 85 86 static unsigned int _get_val(struct clk_divider *divider, u8 div) 87 { 88 if (divider->flags & CLK_DIVIDER_ONE_BASED) 89 return div; 90 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 91 return __ffs(div); 92 if (divider->table) 93 return _get_table_val(divider->table, div); 94 return div - 1; 95 } 96 97 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw, 98 unsigned long parent_rate) 99 { 100 struct clk_divider *divider = to_clk_divider(hw); 101 unsigned int div, val; 102 103 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; 104 val &= div_mask(divider); 105 106 div = _get_div(divider, val); 107 if (!div) { 108 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 109 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 110 clk_hw_get_name(hw)); 111 return parent_rate; 112 } 113 114 return DIV_ROUND_UP(parent_rate, div); 115 } 116 117 /* 118 * The reverse of DIV_ROUND_UP: The maximum number which 119 * divided by m is r 120 */ 121 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) 122 123 static bool _is_valid_table_div(const struct clk_div_table *table, 124 unsigned int div) 125 { 126 const struct clk_div_table *clkt; 127 128 for (clkt = table; clkt->div; clkt++) 129 if (clkt->div == div) 130 return true; 131 return false; 132 } 133 134 static bool _is_valid_div(struct clk_divider *divider, unsigned int div) 135 { 136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 137 return is_power_of_2(div); 138 if (divider->table) 139 return _is_valid_table_div(divider->table, div); 140 return true; 141 } 142 143 static int _div_round_up(const struct clk_div_table *table, 144 unsigned long parent_rate, unsigned long rate) 145 { 146 const struct clk_div_table *clkt; 147 int up = INT_MAX; 148 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 149 150 for (clkt = table; clkt->div; clkt++) { 151 if (clkt->div == div) 152 return clkt->div; 153 else if (clkt->div < div) 154 continue; 155 156 if ((clkt->div - div) < (up - div)) 157 up = clkt->div; 158 } 159 160 return up; 161 } 162 163 static int _div_round(const struct clk_div_table *table, 164 unsigned long parent_rate, unsigned long rate) 165 { 166 if (!table) 167 return DIV_ROUND_UP(parent_rate, rate); 168 169 return _div_round_up(table, parent_rate, rate); 170 } 171 172 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 173 unsigned long *best_parent_rate) 174 { 175 struct clk_divider *divider = to_clk_divider(hw); 176 int i, bestdiv = 0; 177 unsigned long parent_rate, best = 0, now, maxdiv; 178 unsigned long parent_rate_saved = *best_parent_rate; 179 180 if (!rate) 181 rate = 1; 182 183 maxdiv = _get_maxdiv(divider); 184 185 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { 186 parent_rate = *best_parent_rate; 187 bestdiv = _div_round(divider->table, parent_rate, rate); 188 bestdiv = bestdiv == 0 ? 1 : bestdiv; 189 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; 190 return bestdiv; 191 } 192 193 /* 194 * The maximum divider we can use without overflowing 195 * unsigned long in rate * i below 196 */ 197 maxdiv = min(ULONG_MAX / rate, maxdiv); 198 199 for (i = 1; i <= maxdiv; i++) { 200 if (!_is_valid_div(divider, i)) 201 continue; 202 if (rate * i == parent_rate_saved) { 203 /* 204 * It's the most ideal case if the requested rate can be 205 * divided from parent clock without needing to change 206 * parent rate, so return the divider immediately. 207 */ 208 *best_parent_rate = parent_rate_saved; 209 return i; 210 } 211 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 212 MULT_ROUND_UP(rate, i)); 213 now = DIV_ROUND_UP(parent_rate, i); 214 if (now <= rate && now > best) { 215 bestdiv = i; 216 best = now; 217 *best_parent_rate = parent_rate; 218 } 219 } 220 221 if (!bestdiv) { 222 bestdiv = _get_maxdiv(divider); 223 *best_parent_rate = 224 clk_hw_round_rate(clk_hw_get_parent(hw), 1); 225 } 226 227 return bestdiv; 228 } 229 230 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 231 unsigned long *prate) 232 { 233 int div; 234 div = ti_clk_divider_bestdiv(hw, rate, prate); 235 236 return DIV_ROUND_UP(*prate, div); 237 } 238 239 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 240 unsigned long parent_rate) 241 { 242 struct clk_divider *divider; 243 unsigned int div, value; 244 u32 val; 245 246 if (!hw || !rate) 247 return -EINVAL; 248 249 divider = to_clk_divider(hw); 250 251 div = DIV_ROUND_UP(parent_rate, rate); 252 value = _get_val(divider, div); 253 254 if (value > div_mask(divider)) 255 value = div_mask(divider); 256 257 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { 258 val = div_mask(divider) << (divider->shift + 16); 259 } else { 260 val = ti_clk_ll_ops->clk_readl(divider->reg); 261 val &= ~(div_mask(divider) << divider->shift); 262 } 263 val |= value << divider->shift; 264 ti_clk_ll_ops->clk_writel(val, divider->reg); 265 266 return 0; 267 } 268 269 const struct clk_ops ti_clk_divider_ops = { 270 .recalc_rate = ti_clk_divider_recalc_rate, 271 .round_rate = ti_clk_divider_round_rate, 272 .set_rate = ti_clk_divider_set_rate, 273 }; 274 275 static struct clk *_register_divider(struct device *dev, const char *name, 276 const char *parent_name, 277 unsigned long flags, void __iomem *reg, 278 u8 shift, u8 width, u8 clk_divider_flags, 279 const struct clk_div_table *table) 280 { 281 struct clk_divider *div; 282 struct clk *clk; 283 struct clk_init_data init; 284 285 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { 286 if (width + shift > 16) { 287 pr_warn("divider value exceeds LOWORD field\n"); 288 return ERR_PTR(-EINVAL); 289 } 290 } 291 292 /* allocate the divider */ 293 div = kzalloc(sizeof(*div), GFP_KERNEL); 294 if (!div) { 295 pr_err("%s: could not allocate divider clk\n", __func__); 296 return ERR_PTR(-ENOMEM); 297 } 298 299 init.name = name; 300 init.ops = &ti_clk_divider_ops; 301 init.flags = flags | CLK_IS_BASIC; 302 init.parent_names = (parent_name ? &parent_name : NULL); 303 init.num_parents = (parent_name ? 1 : 0); 304 305 /* struct clk_divider assignments */ 306 div->reg = reg; 307 div->shift = shift; 308 div->width = width; 309 div->flags = clk_divider_flags; 310 div->hw.init = &init; 311 div->table = table; 312 313 /* register the clock */ 314 clk = clk_register(dev, &div->hw); 315 316 if (IS_ERR(clk)) 317 kfree(div); 318 319 return clk; 320 } 321 322 static struct clk_div_table * 323 _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width) 324 { 325 int valid_div = 0; 326 struct clk_div_table *table; 327 int i; 328 int div; 329 u32 val; 330 u8 flags; 331 332 if (!setup->num_dividers) { 333 /* Clk divider table not provided, determine min/max divs */ 334 flags = setup->flags; 335 336 if (flags & CLKF_INDEX_STARTS_AT_ONE) 337 val = 1; 338 else 339 val = 0; 340 341 div = 1; 342 343 while (div < setup->max_div) { 344 if (flags & CLKF_INDEX_POWER_OF_TWO) 345 div <<= 1; 346 else 347 div++; 348 val++; 349 } 350 351 *width = fls(val); 352 353 return NULL; 354 } 355 356 for (i = 0; i < setup->num_dividers; i++) 357 if (setup->dividers[i]) 358 valid_div++; 359 360 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL); 361 if (!table) 362 return ERR_PTR(-ENOMEM); 363 364 valid_div = 0; 365 *width = 0; 366 367 for (i = 0; i < setup->num_dividers; i++) 368 if (setup->dividers[i]) { 369 table[valid_div].div = setup->dividers[i]; 370 table[valid_div].val = i; 371 valid_div++; 372 *width = i; 373 } 374 375 *width = fls(*width); 376 377 return table; 378 } 379 380 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup) 381 { 382 struct clk_divider *div; 383 struct clk_omap_reg *reg; 384 385 if (!setup) 386 return NULL; 387 388 div = kzalloc(sizeof(*div), GFP_KERNEL); 389 if (!div) 390 return ERR_PTR(-ENOMEM); 391 392 reg = (struct clk_omap_reg *)&div->reg; 393 reg->index = setup->module; 394 reg->offset = setup->reg; 395 396 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE) 397 div->flags |= CLK_DIVIDER_ONE_BASED; 398 399 if (setup->flags & CLKF_INDEX_POWER_OF_TWO) 400 div->flags |= CLK_DIVIDER_POWER_OF_TWO; 401 402 div->table = _get_div_table_from_setup(setup, &div->width); 403 404 div->shift = setup->bit_shift; 405 406 return &div->hw; 407 } 408 409 struct clk *ti_clk_register_divider(struct ti_clk *setup) 410 { 411 struct ti_clk_divider *div; 412 struct clk_omap_reg *reg_setup; 413 u32 reg; 414 u8 width; 415 u32 flags = 0; 416 u8 div_flags = 0; 417 struct clk_div_table *table; 418 struct clk *clk; 419 420 div = setup->data; 421 422 reg_setup = (struct clk_omap_reg *)® 423 424 reg_setup->index = div->module; 425 reg_setup->offset = div->reg; 426 427 if (div->flags & CLKF_INDEX_STARTS_AT_ONE) 428 div_flags |= CLK_DIVIDER_ONE_BASED; 429 430 if (div->flags & CLKF_INDEX_POWER_OF_TWO) 431 div_flags |= CLK_DIVIDER_POWER_OF_TWO; 432 433 if (div->flags & CLKF_SET_RATE_PARENT) 434 flags |= CLK_SET_RATE_PARENT; 435 436 table = _get_div_table_from_setup(div, &width); 437 if (IS_ERR(table)) 438 return (struct clk *)table; 439 440 clk = _register_divider(NULL, setup->name, div->parent, 441 flags, (void __iomem *)reg, div->bit_shift, 442 width, div_flags, table); 443 444 if (IS_ERR(clk)) 445 kfree(table); 446 447 return clk; 448 } 449 450 static struct clk_div_table * 451 __init ti_clk_get_div_table(struct device_node *node) 452 { 453 struct clk_div_table *table; 454 const __be32 *divspec; 455 u32 val; 456 u32 num_div; 457 u32 valid_div; 458 int i; 459 460 divspec = of_get_property(node, "ti,dividers", &num_div); 461 462 if (!divspec) 463 return NULL; 464 465 num_div /= 4; 466 467 valid_div = 0; 468 469 /* Determine required size for divider table */ 470 for (i = 0; i < num_div; i++) { 471 of_property_read_u32_index(node, "ti,dividers", i, &val); 472 if (val) 473 valid_div++; 474 } 475 476 if (!valid_div) { 477 pr_err("no valid dividers for %s table\n", node->name); 478 return ERR_PTR(-EINVAL); 479 } 480 481 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL); 482 483 if (!table) 484 return ERR_PTR(-ENOMEM); 485 486 valid_div = 0; 487 488 for (i = 0; i < num_div; i++) { 489 of_property_read_u32_index(node, "ti,dividers", i, &val); 490 if (val) { 491 table[valid_div].div = val; 492 table[valid_div].val = i; 493 valid_div++; 494 } 495 } 496 497 return table; 498 } 499 500 static int _get_divider_width(struct device_node *node, 501 const struct clk_div_table *table, 502 u8 flags) 503 { 504 u32 min_div; 505 u32 max_div; 506 u32 val = 0; 507 u32 div; 508 509 if (!table) { 510 /* Clk divider table not provided, determine min/max divs */ 511 if (of_property_read_u32(node, "ti,min-div", &min_div)) 512 min_div = 1; 513 514 if (of_property_read_u32(node, "ti,max-div", &max_div)) { 515 pr_err("no max-div for %s!\n", node->name); 516 return -EINVAL; 517 } 518 519 /* Determine bit width for the field */ 520 if (flags & CLK_DIVIDER_ONE_BASED) 521 val = 1; 522 523 div = min_div; 524 525 while (div < max_div) { 526 if (flags & CLK_DIVIDER_POWER_OF_TWO) 527 div <<= 1; 528 else 529 div++; 530 val++; 531 } 532 } else { 533 div = 0; 534 535 while (table[div].div) { 536 val = table[div].val; 537 div++; 538 } 539 } 540 541 return fls(val); 542 } 543 544 static int __init ti_clk_divider_populate(struct device_node *node, 545 void __iomem **reg, const struct clk_div_table **table, 546 u32 *flags, u8 *div_flags, u8 *width, u8 *shift) 547 { 548 u32 val; 549 550 *reg = ti_clk_get_reg_addr(node, 0); 551 if (IS_ERR(*reg)) 552 return PTR_ERR(*reg); 553 554 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 555 *shift = val; 556 else 557 *shift = 0; 558 559 *flags = 0; 560 *div_flags = 0; 561 562 if (of_property_read_bool(node, "ti,index-starts-at-one")) 563 *div_flags |= CLK_DIVIDER_ONE_BASED; 564 565 if (of_property_read_bool(node, "ti,index-power-of-two")) 566 *div_flags |= CLK_DIVIDER_POWER_OF_TWO; 567 568 if (of_property_read_bool(node, "ti,set-rate-parent")) 569 *flags |= CLK_SET_RATE_PARENT; 570 571 *table = ti_clk_get_div_table(node); 572 573 if (IS_ERR(*table)) 574 return PTR_ERR(*table); 575 576 *width = _get_divider_width(node, *table, *div_flags); 577 578 return 0; 579 } 580 581 /** 582 * of_ti_divider_clk_setup - Setup function for simple div rate clock 583 * @node: device node for this clock 584 * 585 * Sets up a basic divider clock. 586 */ 587 static void __init of_ti_divider_clk_setup(struct device_node *node) 588 { 589 struct clk *clk; 590 const char *parent_name; 591 void __iomem *reg; 592 u8 clk_divider_flags = 0; 593 u8 width = 0; 594 u8 shift = 0; 595 const struct clk_div_table *table = NULL; 596 u32 flags = 0; 597 598 parent_name = of_clk_get_parent_name(node, 0); 599 600 if (ti_clk_divider_populate(node, ®, &table, &flags, 601 &clk_divider_flags, &width, &shift)) 602 goto cleanup; 603 604 clk = _register_divider(NULL, node->name, parent_name, flags, reg, 605 shift, width, clk_divider_flags, table); 606 607 if (!IS_ERR(clk)) { 608 of_clk_add_provider(node, of_clk_src_simple_get, clk); 609 of_ti_clk_autoidle_setup(node); 610 return; 611 } 612 613 cleanup: 614 kfree(table); 615 } 616 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup); 617 618 static void __init of_ti_composite_divider_clk_setup(struct device_node *node) 619 { 620 struct clk_divider *div; 621 u32 val; 622 623 div = kzalloc(sizeof(*div), GFP_KERNEL); 624 if (!div) 625 return; 626 627 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, 628 &div->flags, &div->width, &div->shift) < 0) 629 goto cleanup; 630 631 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER)) 632 return; 633 634 cleanup: 635 kfree(div->table); 636 kfree(div); 637 } 638 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock", 639 of_ti_composite_divider_clk_setup); 640