1 /* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 #ifndef __DRIVERS_CLK_TI_CLOCK__ 17 #define __DRIVERS_CLK_TI_CLOCK__ 18 19 struct clk_omap_divider { 20 struct clk_hw hw; 21 struct clk_omap_reg reg; 22 u8 shift; 23 u8 width; 24 u8 flags; 25 s8 latch; 26 const struct clk_div_table *table; 27 u32 context; 28 }; 29 30 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 31 32 struct clk_omap_mux { 33 struct clk_hw hw; 34 struct clk_omap_reg reg; 35 u32 *table; 36 u32 mask; 37 u8 shift; 38 s8 latch; 39 u8 flags; 40 u8 saved_parent; 41 }; 42 43 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 44 45 enum { 46 TI_CLK_FIXED, 47 TI_CLK_MUX, 48 TI_CLK_DIVIDER, 49 TI_CLK_COMPOSITE, 50 TI_CLK_FIXED_FACTOR, 51 TI_CLK_GATE, 52 TI_CLK_DPLL, 53 }; 54 55 /* Global flags */ 56 #define CLKF_INDEX_POWER_OF_TWO (1 << 0) 57 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) 58 #define CLKF_SET_RATE_PARENT (1 << 2) 59 #define CLKF_OMAP3 (1 << 3) 60 #define CLKF_AM35XX (1 << 4) 61 62 /* Gate flags */ 63 #define CLKF_SET_BIT_TO_DISABLE (1 << 5) 64 #define CLKF_INTERFACE (1 << 6) 65 #define CLKF_SSI (1 << 7) 66 #define CLKF_DSS (1 << 8) 67 #define CLKF_HSOTGUSB (1 << 9) 68 #define CLKF_WAIT (1 << 10) 69 #define CLKF_NO_WAIT (1 << 11) 70 #define CLKF_HSDIV (1 << 12) 71 #define CLKF_CLKDM (1 << 13) 72 73 /* DPLL flags */ 74 #define CLKF_LOW_POWER_STOP (1 << 5) 75 #define CLKF_LOCK (1 << 6) 76 #define CLKF_LOW_POWER_BYPASS (1 << 7) 77 #define CLKF_PER (1 << 8) 78 #define CLKF_CORE (1 << 9) 79 #define CLKF_J_TYPE (1 << 10) 80 81 /* CLKCTRL flags */ 82 #define CLKF_SW_SUP BIT(5) 83 #define CLKF_HW_SUP BIT(6) 84 #define CLKF_NO_IDLEST BIT(7) 85 86 #define CLK(dev, con, ck) \ 87 { \ 88 .lk = { \ 89 .dev_id = dev, \ 90 .con_id = con, \ 91 }, \ 92 .clk = ck, \ 93 } 94 95 struct ti_clk { 96 const char *name; 97 const char *clkdm_name; 98 int type; 99 void *data; 100 struct ti_clk *patch; 101 struct clk *clk; 102 }; 103 104 struct ti_clk_mux { 105 u8 bit_shift; 106 int num_parents; 107 u16 reg; 108 u8 module; 109 const char * const *parents; 110 u16 flags; 111 }; 112 113 struct ti_clk_divider { 114 const char *parent; 115 u8 bit_shift; 116 u16 max_div; 117 u16 reg; 118 u8 module; 119 int *dividers; 120 int num_dividers; 121 u16 flags; 122 }; 123 124 struct ti_clk_gate { 125 const char *parent; 126 u8 bit_shift; 127 u16 reg; 128 u8 module; 129 u16 flags; 130 }; 131 132 /* Composite clock component types */ 133 enum { 134 CLK_COMPONENT_TYPE_GATE = 0, 135 CLK_COMPONENT_TYPE_DIVIDER, 136 CLK_COMPONENT_TYPE_MUX, 137 CLK_COMPONENT_TYPE_MAX, 138 }; 139 140 /** 141 * struct ti_dt_clk - OMAP DT clock alias declarations 142 * @lk: clock lookup definition 143 * @node_name: clock DT node to map to 144 */ 145 struct ti_dt_clk { 146 struct clk_lookup lk; 147 char *node_name; 148 }; 149 150 #define DT_CLK(dev, con, name) \ 151 { \ 152 .lk = { \ 153 .dev_id = dev, \ 154 .con_id = con, \ 155 }, \ 156 .node_name = name, \ 157 } 158 159 /* CLKCTRL type definitions */ 160 struct omap_clkctrl_div_data { 161 const int *dividers; 162 int max_div; 163 u32 flags; 164 }; 165 166 struct omap_clkctrl_bit_data { 167 u8 bit; 168 u8 type; 169 const char * const *parents; 170 const void *data; 171 }; 172 173 struct omap_clkctrl_reg_data { 174 u16 offset; 175 const struct omap_clkctrl_bit_data *bit_data; 176 u16 flags; 177 const char *parent; 178 const char *clkdm_name; 179 }; 180 181 struct omap_clkctrl_data { 182 u32 addr; 183 const struct omap_clkctrl_reg_data *regs; 184 }; 185 186 extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 187 extern const struct omap_clkctrl_data omap5_clkctrl_data[]; 188 extern const struct omap_clkctrl_data dra7_clkctrl_data[]; 189 extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[]; 190 extern struct ti_dt_clk dra7xx_compat_clks[]; 191 extern const struct omap_clkctrl_data am3_clkctrl_data[]; 192 extern const struct omap_clkctrl_data am3_clkctrl_compat_data[]; 193 extern struct ti_dt_clk am33xx_compat_clks[]; 194 extern const struct omap_clkctrl_data am4_clkctrl_data[]; 195 extern const struct omap_clkctrl_data am4_clkctrl_compat_data[]; 196 extern struct ti_dt_clk am43xx_compat_clks[]; 197 extern const struct omap_clkctrl_data am438x_clkctrl_data[]; 198 extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[]; 199 extern const struct omap_clkctrl_data dm814_clkctrl_data[]; 200 extern const struct omap_clkctrl_data dm816_clkctrl_data[]; 201 202 typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); 203 204 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, 205 const char *con); 206 int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); 207 void ti_clk_add_aliases(void); 208 209 void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); 210 211 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 212 213 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, 214 u8 flags, u8 *width, 215 const struct clk_div_table **table); 216 217 int ti_clk_get_reg_addr(struct device_node *node, int index, 218 struct clk_omap_reg *reg); 219 void ti_dt_clocks_register(struct ti_dt_clk *oclks); 220 int ti_clk_retry_init(struct device_node *node, void *user, 221 ti_of_clk_init_cb_t func); 222 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 223 224 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw); 225 int of_ti_clk_autoidle_setup(struct device_node *node); 226 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 227 228 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 229 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 230 extern const struct clk_hw_omap_ops clkhwops_wait; 231 extern const struct clk_hw_omap_ops clkhwops_iclk; 232 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 233 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 234 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 235 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 236 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 237 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 238 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 239 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 240 241 extern const struct clk_ops ti_clk_divider_ops; 242 extern const struct clk_ops ti_clk_mux_ops; 243 extern const struct clk_ops omap_gate_clk_ops; 244 245 extern struct ti_clk_features ti_clk_features; 246 247 void omap2_init_clk_clkdm(struct clk_hw *hw); 248 int omap2_clkops_enable_clkdm(struct clk_hw *hw); 249 void omap2_clkops_disable_clkdm(struct clk_hw *hw); 250 251 int omap2_dflt_clk_enable(struct clk_hw *hw); 252 void omap2_dflt_clk_disable(struct clk_hw *hw); 253 int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 254 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 255 struct clk_omap_reg *other_reg, 256 u8 *other_bit); 257 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 258 struct clk_omap_reg *idlest_reg, 259 u8 *idlest_bit, u8 *idlest_val); 260 261 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 262 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 263 264 u8 omap2_init_dpll_parent(struct clk_hw *hw); 265 int omap3_noncore_dpll_enable(struct clk_hw *hw); 266 void omap3_noncore_dpll_disable(struct clk_hw *hw); 267 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); 268 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 269 unsigned long parent_rate); 270 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, 271 unsigned long rate, 272 unsigned long parent_rate, 273 u8 index); 274 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 275 struct clk_rate_request *req); 276 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 277 unsigned long *parent_rate); 278 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 279 unsigned long parent_rate); 280 281 /* 282 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks 283 * that are sourced by DPLL5, and both of these require this clock 284 * to be at 120 MHz for proper operation. 285 */ 286 #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 287 288 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 289 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, 290 unsigned long parent_rate); 291 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 292 unsigned long parent_rate, u8 index); 293 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, 294 unsigned long parent_rate); 295 void omap3_clk_lock_dpll5(void); 296 297 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 298 unsigned long parent_rate); 299 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 300 unsigned long target_rate, 301 unsigned long *parent_rate); 302 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 303 struct clk_rate_request *req); 304 305 extern struct ti_clk_ll_ops *ti_clk_ll_ops; 306 307 #endif 308