1 /* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 #ifndef __DRIVERS_CLK_TI_CLOCK__ 17 #define __DRIVERS_CLK_TI_CLOCK__ 18 19 struct clk_omap_divider { 20 struct clk_hw hw; 21 struct clk_omap_reg reg; 22 u8 shift; 23 u8 width; 24 u8 flags; 25 s8 latch; 26 const struct clk_div_table *table; 27 u32 context; 28 }; 29 30 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 31 32 struct clk_omap_mux { 33 struct clk_hw hw; 34 struct clk_omap_reg reg; 35 u32 *table; 36 u32 mask; 37 u8 shift; 38 s8 latch; 39 u8 flags; 40 u8 saved_parent; 41 }; 42 43 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 44 45 enum { 46 TI_CLK_FIXED, 47 TI_CLK_MUX, 48 TI_CLK_DIVIDER, 49 TI_CLK_COMPOSITE, 50 TI_CLK_FIXED_FACTOR, 51 TI_CLK_GATE, 52 TI_CLK_DPLL, 53 }; 54 55 /* Global flags */ 56 #define CLKF_INDEX_POWER_OF_TWO (1 << 0) 57 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) 58 #define CLKF_SET_RATE_PARENT (1 << 2) 59 #define CLKF_OMAP3 (1 << 3) 60 #define CLKF_AM35XX (1 << 4) 61 62 /* Gate flags */ 63 #define CLKF_SET_BIT_TO_DISABLE (1 << 5) 64 #define CLKF_INTERFACE (1 << 6) 65 #define CLKF_SSI (1 << 7) 66 #define CLKF_DSS (1 << 8) 67 #define CLKF_HSOTGUSB (1 << 9) 68 #define CLKF_WAIT (1 << 10) 69 #define CLKF_NO_WAIT (1 << 11) 70 #define CLKF_HSDIV (1 << 12) 71 #define CLKF_CLKDM (1 << 13) 72 73 /* DPLL flags */ 74 #define CLKF_LOW_POWER_STOP (1 << 5) 75 #define CLKF_LOCK (1 << 6) 76 #define CLKF_LOW_POWER_BYPASS (1 << 7) 77 #define CLKF_PER (1 << 8) 78 #define CLKF_CORE (1 << 9) 79 #define CLKF_J_TYPE (1 << 10) 80 81 /* CLKCTRL flags */ 82 #define CLKF_SW_SUP BIT(5) 83 #define CLKF_HW_SUP BIT(6) 84 #define CLKF_NO_IDLEST BIT(7) 85 86 #define CLKF_SOC_MASK GENMASK(11, 8) 87 88 #define CLKF_SOC_NONSEC BIT(8) 89 #define CLKF_SOC_DRA72 BIT(9) 90 #define CLKF_SOC_DRA74 BIT(10) 91 #define CLKF_SOC_DRA76 BIT(11) 92 93 #define CLK(dev, con, ck) \ 94 { \ 95 .lk = { \ 96 .dev_id = dev, \ 97 .con_id = con, \ 98 }, \ 99 .clk = ck, \ 100 } 101 102 struct ti_clk { 103 const char *name; 104 const char *clkdm_name; 105 int type; 106 void *data; 107 struct ti_clk *patch; 108 struct clk *clk; 109 }; 110 111 struct ti_clk_mux { 112 u8 bit_shift; 113 int num_parents; 114 u16 reg; 115 u8 module; 116 const char * const *parents; 117 u16 flags; 118 }; 119 120 struct ti_clk_divider { 121 const char *parent; 122 u8 bit_shift; 123 u16 max_div; 124 u16 reg; 125 u8 module; 126 int *dividers; 127 int num_dividers; 128 u16 flags; 129 }; 130 131 struct ti_clk_gate { 132 const char *parent; 133 u8 bit_shift; 134 u16 reg; 135 u8 module; 136 u16 flags; 137 }; 138 139 /* Composite clock component types */ 140 enum { 141 CLK_COMPONENT_TYPE_GATE = 0, 142 CLK_COMPONENT_TYPE_DIVIDER, 143 CLK_COMPONENT_TYPE_MUX, 144 CLK_COMPONENT_TYPE_MAX, 145 }; 146 147 /** 148 * struct ti_dt_clk - OMAP DT clock alias declarations 149 * @lk: clock lookup definition 150 * @node_name: clock DT node to map to 151 */ 152 struct ti_dt_clk { 153 struct clk_lookup lk; 154 char *node_name; 155 }; 156 157 #define DT_CLK(dev, con, name) \ 158 { \ 159 .lk = { \ 160 .dev_id = dev, \ 161 .con_id = con, \ 162 }, \ 163 .node_name = name, \ 164 } 165 166 /* CLKCTRL type definitions */ 167 struct omap_clkctrl_div_data { 168 const int *dividers; 169 int max_div; 170 u32 flags; 171 }; 172 173 struct omap_clkctrl_bit_data { 174 u8 bit; 175 u8 type; 176 const char * const *parents; 177 const void *data; 178 }; 179 180 struct omap_clkctrl_reg_data { 181 u16 offset; 182 const struct omap_clkctrl_bit_data *bit_data; 183 u16 flags; 184 const char *parent; 185 const char *clkdm_name; 186 }; 187 188 struct omap_clkctrl_data { 189 u32 addr; 190 const struct omap_clkctrl_reg_data *regs; 191 }; 192 193 extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 194 extern const struct omap_clkctrl_data omap5_clkctrl_data[]; 195 extern const struct omap_clkctrl_data dra7_clkctrl_data[]; 196 extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[]; 197 extern struct ti_dt_clk dra7xx_compat_clks[]; 198 extern const struct omap_clkctrl_data am3_clkctrl_data[]; 199 extern const struct omap_clkctrl_data am3_clkctrl_compat_data[]; 200 extern struct ti_dt_clk am33xx_compat_clks[]; 201 extern const struct omap_clkctrl_data am4_clkctrl_data[]; 202 extern const struct omap_clkctrl_data am4_clkctrl_compat_data[]; 203 extern struct ti_dt_clk am43xx_compat_clks[]; 204 extern const struct omap_clkctrl_data am438x_clkctrl_data[]; 205 extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[]; 206 extern const struct omap_clkctrl_data dm814_clkctrl_data[]; 207 extern const struct omap_clkctrl_data dm816_clkctrl_data[]; 208 209 typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); 210 211 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, 212 const char *con); 213 struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, 214 const char *con); 215 int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); 216 void ti_clk_add_aliases(void); 217 218 void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); 219 220 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 221 222 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, 223 u8 flags, u8 *width, 224 const struct clk_div_table **table); 225 226 int ti_clk_get_reg_addr(struct device_node *node, int index, 227 struct clk_omap_reg *reg); 228 void ti_dt_clocks_register(struct ti_dt_clk *oclks); 229 int ti_clk_retry_init(struct device_node *node, void *user, 230 ti_of_clk_init_cb_t func); 231 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 232 233 int of_ti_clk_autoidle_setup(struct device_node *node); 234 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 235 236 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 237 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 238 extern const struct clk_hw_omap_ops clkhwops_wait; 239 extern const struct clk_hw_omap_ops clkhwops_iclk; 240 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 241 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 242 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 243 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 244 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 245 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 246 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 247 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 248 249 extern const struct clk_ops ti_clk_divider_ops; 250 extern const struct clk_ops ti_clk_mux_ops; 251 extern const struct clk_ops omap_gate_clk_ops; 252 253 extern struct ti_clk_features ti_clk_features; 254 255 void omap2_init_clk_clkdm(struct clk_hw *hw); 256 int omap2_clkops_enable_clkdm(struct clk_hw *hw); 257 void omap2_clkops_disable_clkdm(struct clk_hw *hw); 258 259 int omap2_dflt_clk_enable(struct clk_hw *hw); 260 void omap2_dflt_clk_disable(struct clk_hw *hw); 261 int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 262 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 263 struct clk_omap_reg *other_reg, 264 u8 *other_bit); 265 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 266 struct clk_omap_reg *idlest_reg, 267 u8 *idlest_bit, u8 *idlest_val); 268 269 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 270 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 271 272 u8 omap2_init_dpll_parent(struct clk_hw *hw); 273 int omap3_noncore_dpll_enable(struct clk_hw *hw); 274 void omap3_noncore_dpll_disable(struct clk_hw *hw); 275 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); 276 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 277 unsigned long parent_rate); 278 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, 279 unsigned long rate, 280 unsigned long parent_rate, 281 u8 index); 282 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 283 struct clk_rate_request *req); 284 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 285 unsigned long *parent_rate); 286 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 287 unsigned long parent_rate); 288 289 /* 290 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks 291 * that are sourced by DPLL5, and both of these require this clock 292 * to be at 120 MHz for proper operation. 293 */ 294 #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 295 296 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 297 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, 298 unsigned long parent_rate); 299 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 300 unsigned long parent_rate, u8 index); 301 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, 302 unsigned long parent_rate); 303 void omap3_clk_lock_dpll5(void); 304 305 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 306 unsigned long parent_rate); 307 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 308 unsigned long target_rate, 309 unsigned long *parent_rate); 310 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 311 struct clk_rate_request *req); 312 int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw)); 313 314 extern struct ti_clk_ll_ops *ti_clk_ll_ops; 315 316 #endif 317