1 /* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 #ifndef __DRIVERS_CLK_TI_CLOCK__ 17 #define __DRIVERS_CLK_TI_CLOCK__ 18 19 struct clk_omap_divider { 20 struct clk_hw hw; 21 struct clk_omap_reg reg; 22 u8 shift; 23 u8 width; 24 u8 flags; 25 const struct clk_div_table *table; 26 }; 27 28 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 29 30 struct clk_omap_mux { 31 struct clk_hw hw; 32 struct clk_omap_reg reg; 33 u32 *table; 34 u32 mask; 35 u8 shift; 36 u8 flags; 37 }; 38 39 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 40 41 enum { 42 TI_CLK_FIXED, 43 TI_CLK_MUX, 44 TI_CLK_DIVIDER, 45 TI_CLK_COMPOSITE, 46 TI_CLK_FIXED_FACTOR, 47 TI_CLK_GATE, 48 TI_CLK_DPLL, 49 }; 50 51 /* Global flags */ 52 #define CLKF_INDEX_POWER_OF_TWO (1 << 0) 53 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) 54 #define CLKF_SET_RATE_PARENT (1 << 2) 55 #define CLKF_OMAP3 (1 << 3) 56 #define CLKF_AM35XX (1 << 4) 57 58 /* Gate flags */ 59 #define CLKF_SET_BIT_TO_DISABLE (1 << 5) 60 #define CLKF_INTERFACE (1 << 6) 61 #define CLKF_SSI (1 << 7) 62 #define CLKF_DSS (1 << 8) 63 #define CLKF_HSOTGUSB (1 << 9) 64 #define CLKF_WAIT (1 << 10) 65 #define CLKF_NO_WAIT (1 << 11) 66 #define CLKF_HSDIV (1 << 12) 67 #define CLKF_CLKDM (1 << 13) 68 69 /* DPLL flags */ 70 #define CLKF_LOW_POWER_STOP (1 << 5) 71 #define CLKF_LOCK (1 << 6) 72 #define CLKF_LOW_POWER_BYPASS (1 << 7) 73 #define CLKF_PER (1 << 8) 74 #define CLKF_CORE (1 << 9) 75 #define CLKF_J_TYPE (1 << 10) 76 77 #define CLK(dev, con, ck) \ 78 { \ 79 .lk = { \ 80 .dev_id = dev, \ 81 .con_id = con, \ 82 }, \ 83 .clk = ck, \ 84 } 85 86 struct ti_clk { 87 const char *name; 88 const char *clkdm_name; 89 int type; 90 void *data; 91 struct ti_clk *patch; 92 struct clk *clk; 93 }; 94 95 struct ti_clk_mux { 96 u8 bit_shift; 97 int num_parents; 98 u16 reg; 99 u8 module; 100 const char * const *parents; 101 u16 flags; 102 }; 103 104 struct ti_clk_divider { 105 const char *parent; 106 u8 bit_shift; 107 u16 max_div; 108 u16 reg; 109 u8 module; 110 int *dividers; 111 int num_dividers; 112 u16 flags; 113 }; 114 115 struct ti_clk_gate { 116 const char *parent; 117 u8 bit_shift; 118 u16 reg; 119 u8 module; 120 u16 flags; 121 }; 122 123 /* Composite clock component types */ 124 enum { 125 CLK_COMPONENT_TYPE_GATE = 0, 126 CLK_COMPONENT_TYPE_DIVIDER, 127 CLK_COMPONENT_TYPE_MUX, 128 CLK_COMPONENT_TYPE_MAX, 129 }; 130 131 /** 132 * struct ti_dt_clk - OMAP DT clock alias declarations 133 * @lk: clock lookup definition 134 * @node_name: clock DT node to map to 135 */ 136 struct ti_dt_clk { 137 struct clk_lookup lk; 138 char *node_name; 139 }; 140 141 #define DT_CLK(dev, con, name) \ 142 { \ 143 .lk = { \ 144 .dev_id = dev, \ 145 .con_id = con, \ 146 }, \ 147 .node_name = name, \ 148 } 149 150 /* CLKCTRL type definitions */ 151 struct omap_clkctrl_div_data { 152 const int *dividers; 153 int max_div; 154 u32 flags; 155 }; 156 157 struct omap_clkctrl_bit_data { 158 u8 bit; 159 u8 type; 160 const char * const *parents; 161 const void *data; 162 }; 163 164 struct omap_clkctrl_reg_data { 165 u16 offset; 166 const struct omap_clkctrl_bit_data *bit_data; 167 u16 flags; 168 const char *parent; 169 const char *clkdm_name; 170 }; 171 172 struct omap_clkctrl_data { 173 u32 addr; 174 const struct omap_clkctrl_reg_data *regs; 175 }; 176 177 extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 178 extern const struct omap_clkctrl_data omap5_clkctrl_data[]; 179 extern const struct omap_clkctrl_data dra7_clkctrl_data[]; 180 extern const struct omap_clkctrl_data am3_clkctrl_data[]; 181 extern const struct omap_clkctrl_data am4_clkctrl_data[]; 182 extern const struct omap_clkctrl_data am438x_clkctrl_data[]; 183 extern const struct omap_clkctrl_data dm814_clkctrl_data[]; 184 extern const struct omap_clkctrl_data dm816_clkctrl_data[]; 185 186 #define CLKF_SW_SUP BIT(0) 187 #define CLKF_HW_SUP BIT(1) 188 #define CLKF_NO_IDLEST BIT(2) 189 190 typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); 191 192 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, 193 const char *con); 194 int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); 195 void ti_clk_add_aliases(void); 196 197 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 198 199 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, 200 u8 flags, u8 *width, 201 const struct clk_div_table **table); 202 203 int ti_clk_get_reg_addr(struct device_node *node, int index, 204 struct clk_omap_reg *reg); 205 void ti_dt_clocks_register(struct ti_dt_clk *oclks); 206 int ti_clk_retry_init(struct device_node *node, void *user, 207 ti_of_clk_init_cb_t func); 208 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 209 210 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw); 211 int of_ti_clk_autoidle_setup(struct device_node *node); 212 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 213 214 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 215 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 216 extern const struct clk_hw_omap_ops clkhwops_wait; 217 extern const struct clk_hw_omap_ops clkhwops_iclk; 218 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 219 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 220 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 221 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 222 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 223 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 224 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 225 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 226 227 extern const struct clk_ops ti_clk_divider_ops; 228 extern const struct clk_ops ti_clk_mux_ops; 229 extern const struct clk_ops omap_gate_clk_ops; 230 231 void omap2_init_clk_clkdm(struct clk_hw *hw); 232 int omap2_clkops_enable_clkdm(struct clk_hw *hw); 233 void omap2_clkops_disable_clkdm(struct clk_hw *hw); 234 235 int omap2_dflt_clk_enable(struct clk_hw *hw); 236 void omap2_dflt_clk_disable(struct clk_hw *hw); 237 int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 238 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 239 struct clk_omap_reg *other_reg, 240 u8 *other_bit); 241 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 242 struct clk_omap_reg *idlest_reg, 243 u8 *idlest_bit, u8 *idlest_val); 244 245 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 246 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 247 248 u8 omap2_init_dpll_parent(struct clk_hw *hw); 249 int omap3_noncore_dpll_enable(struct clk_hw *hw); 250 void omap3_noncore_dpll_disable(struct clk_hw *hw); 251 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); 252 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 253 unsigned long parent_rate); 254 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, 255 unsigned long rate, 256 unsigned long parent_rate, 257 u8 index); 258 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 259 struct clk_rate_request *req); 260 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 261 unsigned long *parent_rate); 262 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 263 unsigned long parent_rate); 264 265 /* 266 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks 267 * that are sourced by DPLL5, and both of these require this clock 268 * to be at 120 MHz for proper operation. 269 */ 270 #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 271 272 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 273 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, 274 unsigned long parent_rate); 275 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 276 unsigned long parent_rate, u8 index); 277 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, 278 unsigned long parent_rate); 279 void omap3_clk_lock_dpll5(void); 280 281 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 282 unsigned long parent_rate); 283 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 284 unsigned long target_rate, 285 unsigned long *parent_rate); 286 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 287 struct clk_rate_request *req); 288 289 extern struct ti_clk_ll_ops *ti_clk_ll_ops; 290 291 #endif 292