xref: /openbmc/linux/drivers/clk/ti/clkctrl.c (revision 465191d6)
1 /*
2  * OMAP clkctrl clock support
3  *
4  * Copyright (C) 2017 Texas Instruments, Inc.
5  *
6  * Tero Kristo <t-kristo@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17 
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/clk/ti.h>
23 #include <linux/delay.h>
24 #include <linux/timekeeping.h>
25 #include "clock.h"
26 
27 #define NO_IDLEST			0
28 
29 #define OMAP4_MODULEMODE_MASK		0x3
30 
31 #define MODULEMODE_HWCTRL		0x1
32 #define MODULEMODE_SWCTRL		0x2
33 
34 #define OMAP4_IDLEST_MASK		(0x3 << 16)
35 #define OMAP4_IDLEST_SHIFT		16
36 
37 #define OMAP4_STBYST_MASK		BIT(18)
38 #define OMAP4_STBYST_SHIFT		18
39 
40 #define CLKCTRL_IDLEST_FUNCTIONAL	0x0
41 #define CLKCTRL_IDLEST_INTERFACE_IDLE	0x2
42 #define CLKCTRL_IDLEST_DISABLED		0x3
43 
44 /* These timeouts are in us */
45 #define OMAP4_MAX_MODULE_READY_TIME	2000
46 #define OMAP4_MAX_MODULE_DISABLE_TIME	5000
47 
48 static bool _early_timeout = true;
49 
50 struct omap_clkctrl_provider {
51 	void __iomem *base;
52 	struct list_head clocks;
53 	char *clkdm_name;
54 };
55 
56 struct omap_clkctrl_clk {
57 	struct clk_hw *clk;
58 	u16 reg_offset;
59 	int bit_offset;
60 	struct list_head node;
61 };
62 
63 union omap4_timeout {
64 	u32 cycles;
65 	ktime_t start;
66 };
67 
68 static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
69 	{ 0 },
70 };
71 
72 static u32 _omap4_idlest(u32 val)
73 {
74 	val &= OMAP4_IDLEST_MASK;
75 	val >>= OMAP4_IDLEST_SHIFT;
76 
77 	return val;
78 }
79 
80 static bool _omap4_is_idle(u32 val)
81 {
82 	val = _omap4_idlest(val);
83 
84 	return val == CLKCTRL_IDLEST_DISABLED;
85 }
86 
87 static bool _omap4_is_ready(u32 val)
88 {
89 	val = _omap4_idlest(val);
90 
91 	return val == CLKCTRL_IDLEST_FUNCTIONAL ||
92 	       val == CLKCTRL_IDLEST_INTERFACE_IDLE;
93 }
94 
95 static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
96 {
97 	/*
98 	 * There are two special cases where ktime_to_ns() can't be
99 	 * used to track the timeouts. First one is during early boot
100 	 * when the timers haven't been initialized yet. The second
101 	 * one is during suspend-resume cycle while timekeeping is
102 	 * being suspended / resumed. Clocksource for the system
103 	 * can be from a timer that requires pm_runtime access, which
104 	 * will eventually bring us here with timekeeping_suspended,
105 	 * during both suspend entry and resume paths. This happens
106 	 * at least on am43xx platform. Account for flakeyness
107 	 * with udelay() by multiplying the timeout value by 2.
108 	 */
109 	if (unlikely(_early_timeout || timekeeping_suspended)) {
110 		if (time->cycles++ < timeout) {
111 			udelay(1 * 2);
112 			return false;
113 		}
114 	} else {
115 		if (!ktime_to_ns(time->start)) {
116 			time->start = ktime_get();
117 			return false;
118 		}
119 
120 		if (ktime_us_delta(ktime_get(), time->start) < timeout) {
121 			cpu_relax();
122 			return false;
123 		}
124 	}
125 
126 	return true;
127 }
128 
129 static int __init _omap4_disable_early_timeout(void)
130 {
131 	_early_timeout = false;
132 
133 	return 0;
134 }
135 arch_initcall(_omap4_disable_early_timeout);
136 
137 static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
138 {
139 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
140 	u32 val;
141 	int ret;
142 	union omap4_timeout timeout = { 0 };
143 
144 	if (clk->clkdm) {
145 		ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
146 		if (ret) {
147 			WARN(1,
148 			     "%s: could not enable %s's clockdomain %s: %d\n",
149 			     __func__, clk_hw_get_name(hw),
150 			     clk->clkdm_name, ret);
151 			return ret;
152 		}
153 	}
154 
155 	if (!clk->enable_bit)
156 		return 0;
157 
158 	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
159 
160 	val &= ~OMAP4_MODULEMODE_MASK;
161 	val |= clk->enable_bit;
162 
163 	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
164 
165 	if (test_bit(NO_IDLEST, &clk->flags))
166 		return 0;
167 
168 	/* Wait until module is enabled */
169 	while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
170 		if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
171 			pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
172 			return -EBUSY;
173 		}
174 	}
175 
176 	return 0;
177 }
178 
179 static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
180 {
181 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
182 	u32 val;
183 	union omap4_timeout timeout = { 0 };
184 
185 	if (!clk->enable_bit)
186 		goto exit;
187 
188 	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
189 
190 	val &= ~OMAP4_MODULEMODE_MASK;
191 
192 	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
193 
194 	if (test_bit(NO_IDLEST, &clk->flags))
195 		goto exit;
196 
197 	/* Wait until module is disabled */
198 	while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
199 		if (_omap4_is_timeout(&timeout,
200 				      OMAP4_MAX_MODULE_DISABLE_TIME)) {
201 			pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
202 			break;
203 		}
204 	}
205 
206 exit:
207 	if (clk->clkdm)
208 		ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
209 }
210 
211 static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
212 {
213 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
214 	u32 val;
215 
216 	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
217 
218 	if (val & clk->enable_bit)
219 		return 1;
220 
221 	return 0;
222 }
223 
224 static const struct clk_ops omap4_clkctrl_clk_ops = {
225 	.enable		= _omap4_clkctrl_clk_enable,
226 	.disable	= _omap4_clkctrl_clk_disable,
227 	.is_enabled	= _omap4_clkctrl_clk_is_enabled,
228 	.init		= omap2_init_clk_clkdm,
229 };
230 
231 static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
232 					      void *data)
233 {
234 	struct omap_clkctrl_provider *provider = data;
235 	struct omap_clkctrl_clk *entry = NULL, *iter;
236 
237 	if (clkspec->args_count != 2)
238 		return ERR_PTR(-EINVAL);
239 
240 	pr_debug("%s: looking for %x:%x\n", __func__,
241 		 clkspec->args[0], clkspec->args[1]);
242 
243 	list_for_each_entry(iter, &provider->clocks, node) {
244 		if (iter->reg_offset == clkspec->args[0] &&
245 		    iter->bit_offset == clkspec->args[1]) {
246 			entry = iter;
247 			break;
248 		}
249 	}
250 
251 	if (!entry)
252 		return ERR_PTR(-EINVAL);
253 
254 	return entry->clk;
255 }
256 
257 /* Get clkctrl clock base name based on clkctrl_name or dts node */
258 static const char * __init clkctrl_get_clock_name(struct device_node *np,
259 						  const char *clkctrl_name,
260 						  int offset, int index,
261 						  bool legacy_naming)
262 {
263 	char *clock_name;
264 
265 	/* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
266 	if (clkctrl_name && !legacy_naming) {
267 		clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d",
268 				       clkctrl_name, offset, index);
269 		strreplace(clock_name, '_', '-');
270 
271 		return clock_name;
272 	}
273 
274 	/* l4per:1234:0 old style naming based on clkctrl_name */
275 	if (clkctrl_name)
276 		return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d",
277 				 clkctrl_name, offset, index);
278 
279 	/* l4per_cm:1234:0 old style naming based on parent node name */
280 	if (legacy_naming)
281 		return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d",
282 				 np->parent, offset, index);
283 
284 	/* l4per-clkctrl:1234:0 style naming based on node name */
285 	return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index);
286 }
287 
288 static int __init
289 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
290 			 struct device_node *node, struct clk_hw *clk_hw,
291 			 u16 offset, u8 bit, const char * const *parents,
292 			 int num_parents, const struct clk_ops *ops,
293 			 const char *clkctrl_name)
294 {
295 	struct clk_init_data init = { NULL };
296 	struct clk *clk;
297 	struct omap_clkctrl_clk *clkctrl_clk;
298 	int ret = 0;
299 
300 	init.name = clkctrl_get_clock_name(node, clkctrl_name, offset, bit,
301 					   ti_clk_get_features()->flags &
302 					   TI_CLK_CLKCTRL_COMPAT);
303 
304 	clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
305 	if (!init.name || !clkctrl_clk) {
306 		ret = -ENOMEM;
307 		goto cleanup;
308 	}
309 
310 	clk_hw->init = &init;
311 	init.parent_names = parents;
312 	init.num_parents = num_parents;
313 	init.ops = ops;
314 	init.flags = 0;
315 
316 	clk = ti_clk_register(NULL, clk_hw, init.name);
317 	if (IS_ERR_OR_NULL(clk)) {
318 		ret = -EINVAL;
319 		goto cleanup;
320 	}
321 
322 	clkctrl_clk->reg_offset = offset;
323 	clkctrl_clk->bit_offset = bit;
324 	clkctrl_clk->clk = clk_hw;
325 
326 	list_add(&clkctrl_clk->node, &provider->clocks);
327 
328 	return 0;
329 
330 cleanup:
331 	kfree(init.name);
332 	kfree(clkctrl_clk);
333 	return ret;
334 }
335 
336 static void __init
337 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
338 		       struct device_node *node, u16 offset,
339 		       const struct omap_clkctrl_bit_data *data,
340 		       void __iomem *reg, const char *clkctrl_name)
341 {
342 	struct clk_hw_omap *clk_hw;
343 
344 	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
345 	if (!clk_hw)
346 		return;
347 
348 	clk_hw->enable_bit = data->bit;
349 	clk_hw->enable_reg.ptr = reg;
350 
351 	if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
352 				     data->bit, data->parents, 1,
353 				     &omap_gate_clk_ops, clkctrl_name))
354 		kfree(clk_hw);
355 }
356 
357 static void __init
358 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
359 		      struct device_node *node, u16 offset,
360 		      const struct omap_clkctrl_bit_data *data,
361 		      void __iomem *reg, const char *clkctrl_name)
362 {
363 	struct clk_omap_mux *mux;
364 	int num_parents = 0;
365 	const char * const *pname;
366 
367 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
368 	if (!mux)
369 		return;
370 
371 	pname = data->parents;
372 	while (*pname) {
373 		num_parents++;
374 		pname++;
375 	}
376 
377 	mux->mask = num_parents;
378 	if (!(mux->flags & CLK_MUX_INDEX_ONE))
379 		mux->mask--;
380 
381 	mux->mask = (1 << fls(mux->mask)) - 1;
382 
383 	mux->shift = data->bit;
384 	mux->reg.ptr = reg;
385 
386 	if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
387 				     data->bit, data->parents, num_parents,
388 				     &ti_clk_mux_ops, clkctrl_name))
389 		kfree(mux);
390 }
391 
392 static void __init
393 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
394 		      struct device_node *node, u16 offset,
395 		      const struct omap_clkctrl_bit_data *data,
396 		      void __iomem *reg, const char *clkctrl_name)
397 {
398 	struct clk_omap_divider *div;
399 	const struct omap_clkctrl_div_data *div_data = data->data;
400 	u8 div_flags = 0;
401 
402 	div = kzalloc(sizeof(*div), GFP_KERNEL);
403 	if (!div)
404 		return;
405 
406 	div->reg.ptr = reg;
407 	div->shift = data->bit;
408 	div->flags = div_data->flags;
409 
410 	if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
411 		div_flags |= CLKF_INDEX_POWER_OF_TWO;
412 
413 	if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
414 				      div_data->max_div, div_flags,
415 				      div)) {
416 		pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
417 		       node, offset, data->bit);
418 		kfree(div);
419 		return;
420 	}
421 
422 	if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
423 				     data->bit, data->parents, 1,
424 				     &ti_clk_divider_ops, clkctrl_name))
425 		kfree(div);
426 }
427 
428 static void __init
429 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
430 			  struct device_node *node,
431 			  const struct omap_clkctrl_reg_data *data,
432 			  void __iomem *reg, const char *clkctrl_name)
433 {
434 	const struct omap_clkctrl_bit_data *bits = data->bit_data;
435 
436 	if (!bits)
437 		return;
438 
439 	while (bits->bit) {
440 		switch (bits->type) {
441 		case TI_CLK_GATE:
442 			_ti_clkctrl_setup_gate(provider, node, data->offset,
443 					       bits, reg, clkctrl_name);
444 			break;
445 
446 		case TI_CLK_DIVIDER:
447 			_ti_clkctrl_setup_div(provider, node, data->offset,
448 					      bits, reg, clkctrl_name);
449 			break;
450 
451 		case TI_CLK_MUX:
452 			_ti_clkctrl_setup_mux(provider, node, data->offset,
453 					      bits, reg, clkctrl_name);
454 			break;
455 
456 		default:
457 			pr_err("%s: bad subclk type: %d\n", __func__,
458 			       bits->type);
459 			return;
460 		}
461 		bits++;
462 	}
463 }
464 
465 static void __init _clkctrl_add_provider(void *data,
466 					 struct device_node *np)
467 {
468 	of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
469 }
470 
471 /*
472  * Get clock name based on "clock-output-names" property or the
473  * compatible property for clkctrl.
474  */
475 static const char * __init clkctrl_get_name(struct device_node *np)
476 {
477 	struct property *prop;
478 	const int prefix_len = 11;
479 	const char *compat;
480 	const char *output;
481 	char *name;
482 
483 	if (!of_property_read_string_index(np, "clock-output-names", 0,
484 					   &output)) {
485 		const char *end;
486 		int len;
487 
488 		len = strlen(output);
489 		end = strstr(output, "_clkctrl");
490 		if (end)
491 			len -= strlen(end);
492 		name = kstrndup(output, len, GFP_KERNEL);
493 
494 		return name;
495 	}
496 
497 	of_property_for_each_string(np, "compatible", prop, compat) {
498 		if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
499 			/* Two letter minimum name length for l3, l4 etc */
500 			if (strnlen(compat + prefix_len, 16) < 2)
501 				continue;
502 			name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len);
503 			if (!name)
504 				continue;
505 			strreplace(name, '-', '_');
506 
507 			return name;
508 		}
509 	}
510 
511 	return NULL;
512 }
513 
514 static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
515 {
516 	struct omap_clkctrl_provider *provider;
517 	const struct omap_clkctrl_data *data = default_clkctrl_data;
518 	const struct omap_clkctrl_reg_data *reg_data;
519 	struct clk_init_data init = { NULL };
520 	struct clk_hw_omap *hw;
521 	struct clk *clk;
522 	struct omap_clkctrl_clk *clkctrl_clk = NULL;
523 	const __be32 *addrp;
524 	bool legacy_naming;
525 	const char *clkctrl_name;
526 	u32 addr;
527 	int ret;
528 	char *c;
529 	u16 soc_mask = 0;
530 
531 	if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
532 	    of_node_name_eq(node, "clk"))
533 		ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
534 
535 	addrp = of_get_address(node, 0, NULL, NULL);
536 	addr = (u32)of_translate_address(node, addrp);
537 
538 #ifdef CONFIG_ARCH_OMAP4
539 	if (of_machine_is_compatible("ti,omap4"))
540 		data = omap4_clkctrl_data;
541 #endif
542 #ifdef CONFIG_SOC_OMAP5
543 	if (of_machine_is_compatible("ti,omap5"))
544 		data = omap5_clkctrl_data;
545 #endif
546 #ifdef CONFIG_SOC_DRA7XX
547 	if (of_machine_is_compatible("ti,dra7"))
548 		data = dra7_clkctrl_data;
549 	if (of_machine_is_compatible("ti,dra72"))
550 		soc_mask = CLKF_SOC_DRA72;
551 	if (of_machine_is_compatible("ti,dra74"))
552 		soc_mask = CLKF_SOC_DRA74;
553 	if (of_machine_is_compatible("ti,dra76"))
554 		soc_mask = CLKF_SOC_DRA76;
555 #endif
556 #ifdef CONFIG_SOC_AM33XX
557 	if (of_machine_is_compatible("ti,am33xx"))
558 		data = am3_clkctrl_data;
559 #endif
560 #ifdef CONFIG_SOC_AM43XX
561 	if (of_machine_is_compatible("ti,am4372"))
562 		data = am4_clkctrl_data;
563 
564 	if (of_machine_is_compatible("ti,am438x"))
565 		data = am438x_clkctrl_data;
566 #endif
567 #ifdef CONFIG_SOC_TI81XX
568 	if (of_machine_is_compatible("ti,dm814"))
569 		data = dm814_clkctrl_data;
570 
571 	if (of_machine_is_compatible("ti,dm816"))
572 		data = dm816_clkctrl_data;
573 #endif
574 
575 	if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
576 		soc_mask |= CLKF_SOC_NONSEC;
577 
578 	while (data->addr) {
579 		if (addr == data->addr)
580 			break;
581 
582 		data++;
583 	}
584 
585 	if (!data->addr) {
586 		pr_err("%pOF not found from clkctrl data.\n", node);
587 		return;
588 	}
589 
590 	provider = kzalloc(sizeof(*provider), GFP_KERNEL);
591 	if (!provider)
592 		return;
593 
594 	provider->base = of_iomap(node, 0);
595 
596 	legacy_naming = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
597 	clkctrl_name = clkctrl_get_name(node);
598 	if (clkctrl_name) {
599 		provider->clkdm_name = kasprintf(GFP_KERNEL,
600 						 "%s_clkdm", clkctrl_name);
601 		goto clkdm_found;
602 	}
603 
604 	/*
605 	 * The code below can be removed when all clkctrl nodes use domain
606 	 * specific compatible property and standard clock node naming
607 	 */
608 	if (legacy_naming) {
609 		provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
610 		if (!provider->clkdm_name) {
611 			kfree(provider);
612 			return;
613 		}
614 
615 		/*
616 		 * Create default clkdm name, replace _cm from end of parent
617 		 * node name with _clkdm
618 		 */
619 		provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
620 	} else {
621 		provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
622 		if (!provider->clkdm_name) {
623 			kfree(provider);
624 			return;
625 		}
626 
627 		/*
628 		 * Create default clkdm name, replace _clkctrl from end of
629 		 * node name with _clkdm
630 		 */
631 		provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
632 	}
633 
634 	strcat(provider->clkdm_name, "clkdm");
635 
636 	/* Replace any dash from the clkdm name with underscore */
637 	c = provider->clkdm_name;
638 
639 	while (*c) {
640 		if (*c == '-')
641 			*c = '_';
642 		c++;
643 	}
644 clkdm_found:
645 	INIT_LIST_HEAD(&provider->clocks);
646 
647 	/* Generate clocks */
648 	reg_data = data->regs;
649 
650 	while (reg_data->parent) {
651 		if ((reg_data->flags & CLKF_SOC_MASK) &&
652 		    (reg_data->flags & soc_mask) == 0) {
653 			reg_data++;
654 			continue;
655 		}
656 
657 		hw = kzalloc(sizeof(*hw), GFP_KERNEL);
658 		if (!hw)
659 			return;
660 
661 		hw->enable_reg.ptr = provider->base + reg_data->offset;
662 
663 		_ti_clkctrl_setup_subclks(provider, node, reg_data,
664 					  hw->enable_reg.ptr, clkctrl_name);
665 
666 		if (reg_data->flags & CLKF_SW_SUP)
667 			hw->enable_bit = MODULEMODE_SWCTRL;
668 		if (reg_data->flags & CLKF_HW_SUP)
669 			hw->enable_bit = MODULEMODE_HWCTRL;
670 		if (reg_data->flags & CLKF_NO_IDLEST)
671 			set_bit(NO_IDLEST, &hw->flags);
672 
673 		if (reg_data->clkdm_name)
674 			hw->clkdm_name = reg_data->clkdm_name;
675 		else
676 			hw->clkdm_name = provider->clkdm_name;
677 
678 		init.parent_names = &reg_data->parent;
679 		init.num_parents = 1;
680 		init.flags = 0;
681 		if (reg_data->flags & CLKF_SET_RATE_PARENT)
682 			init.flags |= CLK_SET_RATE_PARENT;
683 
684 		init.name = clkctrl_get_clock_name(node, clkctrl_name,
685 						   reg_data->offset, 0,
686 						   legacy_naming);
687 		if (!init.name)
688 			goto cleanup;
689 
690 		clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
691 		if (!clkctrl_clk)
692 			goto cleanup;
693 
694 		init.ops = &omap4_clkctrl_clk_ops;
695 		hw->hw.init = &init;
696 
697 		clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name);
698 		if (IS_ERR_OR_NULL(clk))
699 			goto cleanup;
700 
701 		clkctrl_clk->reg_offset = reg_data->offset;
702 		clkctrl_clk->clk = &hw->hw;
703 
704 		list_add(&clkctrl_clk->node, &provider->clocks);
705 
706 		reg_data++;
707 	}
708 
709 	ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
710 	if (ret == -EPROBE_DEFER)
711 		ti_clk_retry_init(node, provider, _clkctrl_add_provider);
712 
713 	kfree(clkctrl_name);
714 
715 	return;
716 
717 cleanup:
718 	kfree(hw);
719 	kfree(init.name);
720 	kfree(clkctrl_name);
721 	kfree(clkctrl_clk);
722 }
723 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
724 	       _ti_omap4_clkctrl_setup);
725 
726 /**
727  * ti_clk_is_in_standby - Check if clkctrl clock is in standby or not
728  * @clk: clock to check standby status for
729  *
730  * Finds whether the provided clock is in standby mode or not. Returns
731  * true if the provided clock is a clkctrl type clock and it is in standby,
732  * false otherwise.
733  */
734 bool ti_clk_is_in_standby(struct clk *clk)
735 {
736 	struct clk_hw *hw;
737 	struct clk_hw_omap *hwclk;
738 	u32 val;
739 
740 	hw = __clk_get_hw(clk);
741 
742 	if (!omap2_clk_is_hw_omap(hw))
743 		return false;
744 
745 	hwclk = to_clk_hw_omap(hw);
746 
747 	val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg);
748 
749 	if (val & OMAP4_STBYST_MASK)
750 		return true;
751 
752 	return false;
753 }
754 EXPORT_SYMBOL_GPL(ti_clk_is_in_standby);
755