15a729246SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
29ac33b0cSPeter Ujfalusi /*
39ac33b0cSPeter Ujfalusi * DRA7 ATL (Audio Tracking Logic) clock driver
49ac33b0cSPeter Ujfalusi *
59ac33b0cSPeter Ujfalusi * Copyright (C) 2013 Texas Instruments, Inc.
69ac33b0cSPeter Ujfalusi *
79ac33b0cSPeter Ujfalusi * Peter Ujfalusi <peter.ujfalusi@ti.com>
89ac33b0cSPeter Ujfalusi */
99ac33b0cSPeter Ujfalusi
10172ff5a2SPaul Gortmaker #include <linux/init.h>
111b29e601SStephen Boyd #include <linux/clk.h>
129ac33b0cSPeter Ujfalusi #include <linux/clk-provider.h>
139ac33b0cSPeter Ujfalusi #include <linux/slab.h>
149ac33b0cSPeter Ujfalusi #include <linux/io.h>
159ac33b0cSPeter Ujfalusi #include <linux/of.h>
169ac33b0cSPeter Ujfalusi #include <linux/of_address.h>
179ac33b0cSPeter Ujfalusi #include <linux/platform_device.h>
189ac33b0cSPeter Ujfalusi #include <linux/pm_runtime.h>
191ae79c46STero Kristo #include <linux/clk/ti.h>
201ae79c46STero Kristo
211ae79c46STero Kristo #include "clock.h"
229ac33b0cSPeter Ujfalusi
239ac33b0cSPeter Ujfalusi #define DRA7_ATL_INSTANCES 4
249ac33b0cSPeter Ujfalusi
259ac33b0cSPeter Ujfalusi #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
269ac33b0cSPeter Ujfalusi #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
279ac33b0cSPeter Ujfalusi #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
289ac33b0cSPeter Ujfalusi #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
299ac33b0cSPeter Ujfalusi #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
309ac33b0cSPeter Ujfalusi #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
319ac33b0cSPeter Ujfalusi #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
329ac33b0cSPeter Ujfalusi
339ac33b0cSPeter Ujfalusi #define DRA7_ATL_SWEN BIT(0)
349ac33b0cSPeter Ujfalusi #define DRA7_ATL_DIVIDER_MASK (0x1f)
359ac33b0cSPeter Ujfalusi #define DRA7_ATL_PCLKMUX BIT(0)
369ac33b0cSPeter Ujfalusi struct dra7_atl_clock_info;
379ac33b0cSPeter Ujfalusi
389ac33b0cSPeter Ujfalusi struct dra7_atl_desc {
399ac33b0cSPeter Ujfalusi struct clk *clk;
409ac33b0cSPeter Ujfalusi struct clk_hw hw;
419ac33b0cSPeter Ujfalusi struct dra7_atl_clock_info *cinfo;
429ac33b0cSPeter Ujfalusi int id;
439ac33b0cSPeter Ujfalusi
449ac33b0cSPeter Ujfalusi bool probed; /* the driver for the IP has been loaded */
459ac33b0cSPeter Ujfalusi bool valid; /* configured */
469ac33b0cSPeter Ujfalusi bool enabled;
479ac33b0cSPeter Ujfalusi u32 bws; /* Baseband Word Select Mux */
489ac33b0cSPeter Ujfalusi u32 aws; /* Audio Word Select Mux */
499ac33b0cSPeter Ujfalusi u32 divider; /* Cached divider value */
509ac33b0cSPeter Ujfalusi };
519ac33b0cSPeter Ujfalusi
529ac33b0cSPeter Ujfalusi struct dra7_atl_clock_info {
539ac33b0cSPeter Ujfalusi struct device *dev;
549ac33b0cSPeter Ujfalusi void __iomem *iobase;
559ac33b0cSPeter Ujfalusi
569ac33b0cSPeter Ujfalusi struct dra7_atl_desc *cdesc;
579ac33b0cSPeter Ujfalusi };
589ac33b0cSPeter Ujfalusi
599ac33b0cSPeter Ujfalusi #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
609ac33b0cSPeter Ujfalusi
atl_write(struct dra7_atl_clock_info * cinfo,u32 reg,u32 val)619ac33b0cSPeter Ujfalusi static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
629ac33b0cSPeter Ujfalusi u32 val)
639ac33b0cSPeter Ujfalusi {
649ac33b0cSPeter Ujfalusi __raw_writel(val, cinfo->iobase + reg);
659ac33b0cSPeter Ujfalusi }
669ac33b0cSPeter Ujfalusi
atl_read(struct dra7_atl_clock_info * cinfo,u32 reg)679ac33b0cSPeter Ujfalusi static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
689ac33b0cSPeter Ujfalusi {
699ac33b0cSPeter Ujfalusi return __raw_readl(cinfo->iobase + reg);
709ac33b0cSPeter Ujfalusi }
719ac33b0cSPeter Ujfalusi
atl_clk_enable(struct clk_hw * hw)729ac33b0cSPeter Ujfalusi static int atl_clk_enable(struct clk_hw *hw)
739ac33b0cSPeter Ujfalusi {
749ac33b0cSPeter Ujfalusi struct dra7_atl_desc *cdesc = to_atl_desc(hw);
759ac33b0cSPeter Ujfalusi
769ac33b0cSPeter Ujfalusi if (!cdesc->probed)
779ac33b0cSPeter Ujfalusi goto out;
789ac33b0cSPeter Ujfalusi
799ac33b0cSPeter Ujfalusi if (unlikely(!cdesc->valid))
809ac33b0cSPeter Ujfalusi dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
819ac33b0cSPeter Ujfalusi cdesc->id);
829ac33b0cSPeter Ujfalusi pm_runtime_get_sync(cdesc->cinfo->dev);
839ac33b0cSPeter Ujfalusi
849ac33b0cSPeter Ujfalusi atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
859ac33b0cSPeter Ujfalusi cdesc->divider - 1);
869ac33b0cSPeter Ujfalusi atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
879ac33b0cSPeter Ujfalusi
889ac33b0cSPeter Ujfalusi out:
899ac33b0cSPeter Ujfalusi cdesc->enabled = true;
909ac33b0cSPeter Ujfalusi
919ac33b0cSPeter Ujfalusi return 0;
929ac33b0cSPeter Ujfalusi }
939ac33b0cSPeter Ujfalusi
atl_clk_disable(struct clk_hw * hw)949ac33b0cSPeter Ujfalusi static void atl_clk_disable(struct clk_hw *hw)
959ac33b0cSPeter Ujfalusi {
969ac33b0cSPeter Ujfalusi struct dra7_atl_desc *cdesc = to_atl_desc(hw);
979ac33b0cSPeter Ujfalusi
989ac33b0cSPeter Ujfalusi if (!cdesc->probed)
999ac33b0cSPeter Ujfalusi goto out;
1009ac33b0cSPeter Ujfalusi
1019ac33b0cSPeter Ujfalusi atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
1029ac33b0cSPeter Ujfalusi pm_runtime_put_sync(cdesc->cinfo->dev);
1039ac33b0cSPeter Ujfalusi
1049ac33b0cSPeter Ujfalusi out:
1059ac33b0cSPeter Ujfalusi cdesc->enabled = false;
1069ac33b0cSPeter Ujfalusi }
1079ac33b0cSPeter Ujfalusi
atl_clk_is_enabled(struct clk_hw * hw)1089ac33b0cSPeter Ujfalusi static int atl_clk_is_enabled(struct clk_hw *hw)
1099ac33b0cSPeter Ujfalusi {
1109ac33b0cSPeter Ujfalusi struct dra7_atl_desc *cdesc = to_atl_desc(hw);
1119ac33b0cSPeter Ujfalusi
1129ac33b0cSPeter Ujfalusi return cdesc->enabled;
1139ac33b0cSPeter Ujfalusi }
1149ac33b0cSPeter Ujfalusi
atl_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1159ac33b0cSPeter Ujfalusi static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
1169ac33b0cSPeter Ujfalusi unsigned long parent_rate)
1179ac33b0cSPeter Ujfalusi {
1189ac33b0cSPeter Ujfalusi struct dra7_atl_desc *cdesc = to_atl_desc(hw);
1199ac33b0cSPeter Ujfalusi
1209ac33b0cSPeter Ujfalusi return parent_rate / cdesc->divider;
1219ac33b0cSPeter Ujfalusi }
1229ac33b0cSPeter Ujfalusi
atl_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1239ac33b0cSPeter Ujfalusi static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1249ac33b0cSPeter Ujfalusi unsigned long *parent_rate)
1259ac33b0cSPeter Ujfalusi {
1269ac33b0cSPeter Ujfalusi unsigned divider;
1279ac33b0cSPeter Ujfalusi
1289ac33b0cSPeter Ujfalusi divider = (*parent_rate + rate / 2) / rate;
1299ac33b0cSPeter Ujfalusi if (divider > DRA7_ATL_DIVIDER_MASK + 1)
1309ac33b0cSPeter Ujfalusi divider = DRA7_ATL_DIVIDER_MASK + 1;
1319ac33b0cSPeter Ujfalusi
1329ac33b0cSPeter Ujfalusi return *parent_rate / divider;
1339ac33b0cSPeter Ujfalusi }
1349ac33b0cSPeter Ujfalusi
atl_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1359ac33b0cSPeter Ujfalusi static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1369ac33b0cSPeter Ujfalusi unsigned long parent_rate)
1379ac33b0cSPeter Ujfalusi {
13820411dadSNishanth Menon struct dra7_atl_desc *cdesc;
1399ac33b0cSPeter Ujfalusi u32 divider;
1409ac33b0cSPeter Ujfalusi
14120411dadSNishanth Menon if (!hw || !rate)
14220411dadSNishanth Menon return -EINVAL;
14320411dadSNishanth Menon
14420411dadSNishanth Menon cdesc = to_atl_desc(hw);
1459ac33b0cSPeter Ujfalusi divider = ((parent_rate + rate / 2) / rate) - 1;
1469ac33b0cSPeter Ujfalusi if (divider > DRA7_ATL_DIVIDER_MASK)
1479ac33b0cSPeter Ujfalusi divider = DRA7_ATL_DIVIDER_MASK;
1489ac33b0cSPeter Ujfalusi
1499ac33b0cSPeter Ujfalusi cdesc->divider = divider + 1;
1509ac33b0cSPeter Ujfalusi
1519ac33b0cSPeter Ujfalusi return 0;
1529ac33b0cSPeter Ujfalusi }
1539ac33b0cSPeter Ujfalusi
154412d6b47SStephen Boyd static const struct clk_ops atl_clk_ops = {
1559ac33b0cSPeter Ujfalusi .enable = atl_clk_enable,
1569ac33b0cSPeter Ujfalusi .disable = atl_clk_disable,
1579ac33b0cSPeter Ujfalusi .is_enabled = atl_clk_is_enabled,
1589ac33b0cSPeter Ujfalusi .recalc_rate = atl_clk_recalc_rate,
1599ac33b0cSPeter Ujfalusi .round_rate = atl_clk_round_rate,
1609ac33b0cSPeter Ujfalusi .set_rate = atl_clk_set_rate,
1619ac33b0cSPeter Ujfalusi };
1629ac33b0cSPeter Ujfalusi
of_dra7_atl_clock_setup(struct device_node * node)1639ac33b0cSPeter Ujfalusi static void __init of_dra7_atl_clock_setup(struct device_node *node)
1649ac33b0cSPeter Ujfalusi {
1659ac33b0cSPeter Ujfalusi struct dra7_atl_desc *clk_hw = NULL;
166*6e49aacaSDario Binacchi struct clk_parent_data pdata = { .index = 0 };
167412d6b47SStephen Boyd struct clk_init_data init = { NULL };
168ed06099cSTony Lindgren const char *name;
1699ac33b0cSPeter Ujfalusi struct clk *clk;
1709ac33b0cSPeter Ujfalusi
1719ac33b0cSPeter Ujfalusi clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
1729ac33b0cSPeter Ujfalusi if (!clk_hw) {
1739ac33b0cSPeter Ujfalusi pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
1749ac33b0cSPeter Ujfalusi return;
1759ac33b0cSPeter Ujfalusi }
1769ac33b0cSPeter Ujfalusi
1779ac33b0cSPeter Ujfalusi clk_hw->hw.init = &init;
1789ac33b0cSPeter Ujfalusi clk_hw->divider = 1;
179ed06099cSTony Lindgren name = ti_dt_clk_name(node);
180ed06099cSTony Lindgren init.name = name;
1819ac33b0cSPeter Ujfalusi init.ops = &atl_clk_ops;
1829ac33b0cSPeter Ujfalusi init.flags = CLK_IGNORE_UNUSED;
1839ac33b0cSPeter Ujfalusi init.num_parents = of_clk_get_parent_count(node);
1849ac33b0cSPeter Ujfalusi
1859ac33b0cSPeter Ujfalusi if (init.num_parents != 1) {
186e665f029SRob Herring pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
187e665f029SRob Herring node);
1889ac33b0cSPeter Ujfalusi goto cleanup;
1899ac33b0cSPeter Ujfalusi }
1909ac33b0cSPeter Ujfalusi
191*6e49aacaSDario Binacchi init.parent_data = &pdata;
1923400d546SDario Binacchi clk = of_ti_clk_register(node, &clk_hw->hw, name);
1939ac33b0cSPeter Ujfalusi
1949ac33b0cSPeter Ujfalusi if (!IS_ERR(clk)) {
1959ac33b0cSPeter Ujfalusi of_clk_add_provider(node, of_clk_src_simple_get, clk);
1969ac33b0cSPeter Ujfalusi return;
1979ac33b0cSPeter Ujfalusi }
1989ac33b0cSPeter Ujfalusi cleanup:
1999ac33b0cSPeter Ujfalusi kfree(clk_hw);
2009ac33b0cSPeter Ujfalusi }
2019ac33b0cSPeter Ujfalusi CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
2029ac33b0cSPeter Ujfalusi
of_dra7_atl_clk_probe(struct platform_device * pdev)2039ac33b0cSPeter Ujfalusi static int of_dra7_atl_clk_probe(struct platform_device *pdev)
2049ac33b0cSPeter Ujfalusi {
2059ac33b0cSPeter Ujfalusi struct device_node *node = pdev->dev.of_node;
2069ac33b0cSPeter Ujfalusi struct dra7_atl_clock_info *cinfo;
2079ac33b0cSPeter Ujfalusi int i;
2089ac33b0cSPeter Ujfalusi int ret = 0;
2099ac33b0cSPeter Ujfalusi
2109ac33b0cSPeter Ujfalusi if (!node)
2119ac33b0cSPeter Ujfalusi return -ENODEV;
2129ac33b0cSPeter Ujfalusi
2139ac33b0cSPeter Ujfalusi cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
2149ac33b0cSPeter Ujfalusi if (!cinfo)
2159ac33b0cSPeter Ujfalusi return -ENOMEM;
2169ac33b0cSPeter Ujfalusi
2179ac33b0cSPeter Ujfalusi cinfo->iobase = of_iomap(node, 0);
2189ac33b0cSPeter Ujfalusi cinfo->dev = &pdev->dev;
2199ac33b0cSPeter Ujfalusi pm_runtime_enable(cinfo->dev);
2209ac33b0cSPeter Ujfalusi
2219ac33b0cSPeter Ujfalusi pm_runtime_get_sync(cinfo->dev);
2229ac33b0cSPeter Ujfalusi atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
2239ac33b0cSPeter Ujfalusi
2249ac33b0cSPeter Ujfalusi for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
2259ac33b0cSPeter Ujfalusi struct device_node *cfg_node;
2269ac33b0cSPeter Ujfalusi char prop[5];
2279ac33b0cSPeter Ujfalusi struct dra7_atl_desc *cdesc;
2289ac33b0cSPeter Ujfalusi struct of_phandle_args clkspec;
2299ac33b0cSPeter Ujfalusi struct clk *clk;
2309ac33b0cSPeter Ujfalusi int rc;
2319ac33b0cSPeter Ujfalusi
2329ac33b0cSPeter Ujfalusi rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
2339ac33b0cSPeter Ujfalusi NULL, i, &clkspec);
2349ac33b0cSPeter Ujfalusi
2359ac33b0cSPeter Ujfalusi if (rc) {
2369ac33b0cSPeter Ujfalusi pr_err("%s: failed to lookup atl clock %d\n", __func__,
2379ac33b0cSPeter Ujfalusi i);
2389c59a01cSMiaoqian Lin ret = -EINVAL;
2399c59a01cSMiaoqian Lin goto pm_put;
2409ac33b0cSPeter Ujfalusi }
2419ac33b0cSPeter Ujfalusi
2429ac33b0cSPeter Ujfalusi clk = of_clk_get_from_provider(&clkspec);
243e0cdcda5SKrzysztof Kozlowski if (IS_ERR(clk)) {
244e0cdcda5SKrzysztof Kozlowski pr_err("%s: failed to get atl clock %d from provider\n",
245e0cdcda5SKrzysztof Kozlowski __func__, i);
2469c59a01cSMiaoqian Lin ret = PTR_ERR(clk);
2479c59a01cSMiaoqian Lin goto pm_put;
248e0cdcda5SKrzysztof Kozlowski }
2499ac33b0cSPeter Ujfalusi
2509ac33b0cSPeter Ujfalusi cdesc = to_atl_desc(__clk_get_hw(clk));
2519ac33b0cSPeter Ujfalusi cdesc->cinfo = cinfo;
2529ac33b0cSPeter Ujfalusi cdesc->id = i;
2539ac33b0cSPeter Ujfalusi
2549ac33b0cSPeter Ujfalusi /* Get configuration for the ATL instances */
2559ac33b0cSPeter Ujfalusi snprintf(prop, sizeof(prop), "atl%u", i);
25633ec6dbcSJohan Hovold cfg_node = of_get_child_by_name(node, prop);
2579ac33b0cSPeter Ujfalusi if (cfg_node) {
2589ac33b0cSPeter Ujfalusi ret = of_property_read_u32(cfg_node, "bws",
2599ac33b0cSPeter Ujfalusi &cdesc->bws);
2609ac33b0cSPeter Ujfalusi ret |= of_property_read_u32(cfg_node, "aws",
2619ac33b0cSPeter Ujfalusi &cdesc->aws);
2629ac33b0cSPeter Ujfalusi if (!ret) {
2639ac33b0cSPeter Ujfalusi cdesc->valid = true;
2649ac33b0cSPeter Ujfalusi atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
2659ac33b0cSPeter Ujfalusi cdesc->bws);
2669ac33b0cSPeter Ujfalusi atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
2679ac33b0cSPeter Ujfalusi cdesc->aws);
2689ac33b0cSPeter Ujfalusi }
269660e1551SPeter Ujfalusi of_node_put(cfg_node);
2709ac33b0cSPeter Ujfalusi }
2719ac33b0cSPeter Ujfalusi
2729ac33b0cSPeter Ujfalusi cdesc->probed = true;
2739ac33b0cSPeter Ujfalusi /*
2749ac33b0cSPeter Ujfalusi * Enable the clock if it has been asked prior to loading the
2759ac33b0cSPeter Ujfalusi * hw driver
2769ac33b0cSPeter Ujfalusi */
2779ac33b0cSPeter Ujfalusi if (cdesc->enabled)
2789ac33b0cSPeter Ujfalusi atl_clk_enable(__clk_get_hw(clk));
2799ac33b0cSPeter Ujfalusi }
2809ac33b0cSPeter Ujfalusi
2819c59a01cSMiaoqian Lin pm_put:
2829c59a01cSMiaoqian Lin pm_runtime_put_sync(cinfo->dev);
2839ac33b0cSPeter Ujfalusi return ret;
2849ac33b0cSPeter Ujfalusi }
2859ac33b0cSPeter Ujfalusi
286f375573cSFabian Frederick static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
2879ac33b0cSPeter Ujfalusi { .compatible = "ti,dra7-atl", },
2889ac33b0cSPeter Ujfalusi {},
2899ac33b0cSPeter Ujfalusi };
2909ac33b0cSPeter Ujfalusi
2919ac33b0cSPeter Ujfalusi static struct platform_driver dra7_atl_clk_driver = {
2929ac33b0cSPeter Ujfalusi .driver = {
2939ac33b0cSPeter Ujfalusi .name = "dra7-atl",
294172ff5a2SPaul Gortmaker .suppress_bind_attrs = true,
2959ac33b0cSPeter Ujfalusi .of_match_table = of_dra7_atl_clk_match_tbl,
2969ac33b0cSPeter Ujfalusi },
2979ac33b0cSPeter Ujfalusi .probe = of_dra7_atl_clk_probe,
2989ac33b0cSPeter Ujfalusi };
299172ff5a2SPaul Gortmaker builtin_platform_driver(dra7_atl_clk_driver);
300