11a34275dSTony Lindgren /* 21a34275dSTony Lindgren * This program is free software; you can redistribute it and/or 31a34275dSTony Lindgren * modify it under the terms of the GNU General Public License as 41a34275dSTony Lindgren * published by the Free Software Foundation version 2. 51a34275dSTony Lindgren * 61a34275dSTony Lindgren * This program is distributed "as is" WITHOUT ANY WARRANTY of any 71a34275dSTony Lindgren * kind, whether express or implied; without even the implied warranty 81a34275dSTony Lindgren * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 91a34275dSTony Lindgren * GNU General Public License for more details. 101a34275dSTony Lindgren */ 111a34275dSTony Lindgren 121a34275dSTony Lindgren #include <linux/kernel.h> 131a34275dSTony Lindgren #include <linux/list.h> 141a34275dSTony Lindgren #include <linux/clk-provider.h> 151a34275dSTony Lindgren #include <linux/clk/ti.h> 1650ef5089STero Kristo #include <dt-bindings/clock/dm816.h> 171a34275dSTony Lindgren 18a5aa8a60STero Kristo #include "clock.h" 19a5aa8a60STero Kristo 2050ef5089STero Kristo static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = { 2150ef5089STero Kristo { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, 2250ef5089STero Kristo { 0 }, 2350ef5089STero Kristo }; 2450ef5089STero Kristo 2550ef5089STero Kristo static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = { 2650ef5089STero Kristo { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 2750ef5089STero Kristo { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 2850ef5089STero Kristo { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 2950ef5089STero Kristo { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, 3050ef5089STero Kristo { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, 3150ef5089STero Kristo { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 3250ef5089STero Kristo { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 3350ef5089STero Kristo { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, 3450ef5089STero Kristo { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 3550ef5089STero Kristo { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 3650ef5089STero Kristo { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 3750ef5089STero Kristo { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 3850ef5089STero Kristo { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 3950ef5089STero Kristo { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 4050ef5089STero Kristo { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, 4150ef5089STero Kristo { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 4250ef5089STero Kristo { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, 4350ef5089STero Kristo { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, 4450ef5089STero Kristo { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, 4550ef5089STero Kristo { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, 4650ef5089STero Kristo { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" }, 4750ef5089STero Kristo { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" }, 4850ef5089STero Kristo { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" }, 4950ef5089STero Kristo { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, 5050ef5089STero Kristo { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, 5150ef5089STero Kristo { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, 5250ef5089STero Kristo { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, 5350ef5089STero Kristo { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, 5450ef5089STero Kristo { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, 5550ef5089STero Kristo { 0 }, 5650ef5089STero Kristo }; 5750ef5089STero Kristo 5850ef5089STero Kristo const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = { 5950ef5089STero Kristo { 0x48180500, dm816_default_clkctrl_regs }, 6050ef5089STero Kristo { 0x48181400, dm816_alwon_clkctrl_regs }, 6150ef5089STero Kristo { 0 }, 6250ef5089STero Kristo }; 6350ef5089STero Kristo 641a34275dSTony Lindgren static struct ti_dt_clk dm816x_clks[] = { 651a34275dSTony Lindgren DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), 661a34275dSTony Lindgren DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 673a5b1dc4SNeil Armstrong DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), 683a5b1dc4SNeil Armstrong DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), 691a34275dSTony Lindgren { .node_name = NULL }, 701a34275dSTony Lindgren }; 711a34275dSTony Lindgren 721a34275dSTony Lindgren static const char *enable_init_clks[] = { 731a34275dSTony Lindgren "ddr_pll_clk1", 741a34275dSTony Lindgren "ddr_pll_clk2", 751a34275dSTony Lindgren "ddr_pll_clk3", 7616aed29dSTony Lindgren "sysclk6_ck", 771a34275dSTony Lindgren }; 781a34275dSTony Lindgren 799cf705deSTony Lindgren int __init dm816x_dt_clk_init(void) 801a34275dSTony Lindgren { 811a34275dSTony Lindgren ti_dt_clocks_register(dm816x_clks); 821a34275dSTony Lindgren omap2_clk_disable_autoidle_all(); 83d935864aSTero Kristo ti_clk_add_aliases(); 841a34275dSTony Lindgren omap2_clk_enable_init_clocks(enable_init_clks, 851a34275dSTony Lindgren ARRAY_SIZE(enable_init_clks)); 861a34275dSTony Lindgren 871a34275dSTony Lindgren return 0; 881a34275dSTony Lindgren } 89