1251a449dSTero Kristo /* 2251a449dSTero Kristo * DRA7 Clock init 3251a449dSTero Kristo * 4251a449dSTero Kristo * Copyright (C) 2013 Texas Instruments, Inc. 5251a449dSTero Kristo * 6251a449dSTero Kristo * Tero Kristo (t-kristo@ti.com) 7251a449dSTero Kristo * 8251a449dSTero Kristo * This program is free software; you can redistribute it and/or modify 9251a449dSTero Kristo * it under the terms of the GNU General Public License version 2 as 10251a449dSTero Kristo * published by the Free Software Foundation. 11251a449dSTero Kristo */ 12251a449dSTero Kristo 13251a449dSTero Kristo #include <linux/kernel.h> 14251a449dSTero Kristo #include <linux/list.h> 15e387088aSStephen Boyd #include <linux/clk.h> 16251a449dSTero Kristo #include <linux/clkdev.h> 17251a449dSTero Kristo #include <linux/clk/ti.h> 1824d504a3STero Kristo #include <dt-bindings/clock/dra7.h> 19251a449dSTero Kristo 20a3314e9cSTero Kristo #include "clock.h" 21a3314e9cSTero Kristo 22251a449dSTero Kristo #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 2394e72ae5SRoger Quadros #define DRA7_DPLL_USB_DEFFREQ 960000000 24251a449dSTero Kristo 25dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { 26dffa9051STero Kristo { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 27dffa9051STero Kristo { 0 }, 28dffa9051STero Kristo }; 29dffa9051STero Kristo 30dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = { 31dffa9051STero Kristo { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" }, 32dffa9051STero Kristo { 0 }, 33dffa9051STero Kristo }; 34dffa9051STero Kristo 35dffa9051STero Kristo static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = { 36dffa9051STero Kristo "dpll_abe_m2x2_ck", 37dffa9051STero Kristo "dpll_core_h22x2_ck", 38dffa9051STero Kristo NULL, 39dffa9051STero Kristo }; 40dffa9051STero Kristo 41dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = { 42dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL }, 43dffa9051STero Kristo { 0 }, 44dffa9051STero Kristo }; 45dffa9051STero Kristo 46dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = { 47dffa9051STero Kristo { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" }, 48dffa9051STero Kristo { 0 }, 49dffa9051STero Kristo }; 50dffa9051STero Kristo 51dffa9051STero Kristo static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = { 52dffa9051STero Kristo "per_abe_x1_gfclk2_div", 53dffa9051STero Kristo "video1_clk2_div", 54dffa9051STero Kristo "video2_clk2_div", 55dffa9051STero Kristo "hdmi_clk2_div", 56dffa9051STero Kristo NULL, 57dffa9051STero Kristo }; 58dffa9051STero Kristo 59dffa9051STero Kristo static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = { 60dffa9051STero Kristo "abe_24m_fclk", 61dffa9051STero Kristo "abe_sys_clk_div", 62dffa9051STero Kristo "func_24m_clk", 63dffa9051STero Kristo "atl_clkin3_ck", 64dffa9051STero Kristo "atl_clkin2_ck", 65dffa9051STero Kristo "atl_clkin1_ck", 66dffa9051STero Kristo "atl_clkin0_ck", 67dffa9051STero Kristo "sys_clkin2", 68dffa9051STero Kristo "ref_clkin0_ck", 69dffa9051STero Kristo "ref_clkin1_ck", 70dffa9051STero Kristo "ref_clkin2_ck", 71dffa9051STero Kristo "ref_clkin3_ck", 72dffa9051STero Kristo "mlb_clk", 73dffa9051STero Kristo "mlbp_clk", 74dffa9051STero Kristo NULL, 75dffa9051STero Kristo }; 76dffa9051STero Kristo 77dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = { 78dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 79dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 80dffa9051STero Kristo { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 81dffa9051STero Kristo { 0 }, 82dffa9051STero Kristo }; 83dffa9051STero Kristo 84dffa9051STero Kristo static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = { 85dffa9051STero Kristo "timer_sys_clk_div", 86dffa9051STero Kristo "sys_32k_ck", 87dffa9051STero Kristo "sys_clkin2", 88dffa9051STero Kristo "ref_clkin0_ck", 89dffa9051STero Kristo "ref_clkin1_ck", 90dffa9051STero Kristo "ref_clkin2_ck", 91dffa9051STero Kristo "ref_clkin3_ck", 92dffa9051STero Kristo "abe_giclk_div", 93dffa9051STero Kristo "video1_div_clk", 94dffa9051STero Kristo "video2_div_clk", 95dffa9051STero Kristo "hdmi_div_clk", 96dffa9051STero Kristo "clkoutmux0_clk_mux", 97dffa9051STero Kristo NULL, 98dffa9051STero Kristo }; 99dffa9051STero Kristo 100dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = { 101dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 102dffa9051STero Kristo { 0 }, 103dffa9051STero Kristo }; 104dffa9051STero Kristo 105dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = { 106dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 107dffa9051STero Kristo { 0 }, 108dffa9051STero Kristo }; 109dffa9051STero Kristo 110dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = { 111dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 112dffa9051STero Kristo { 0 }, 113dffa9051STero Kristo }; 114dffa9051STero Kristo 115dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = { 116dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 117dffa9051STero Kristo { 0 }, 118dffa9051STero Kristo }; 119dffa9051STero Kristo 120dffa9051STero Kristo static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = { 121dffa9051STero Kristo "func_48m_fclk", 122dffa9051STero Kristo "dpll_per_m2x2_ck", 123dffa9051STero Kristo NULL, 124dffa9051STero Kristo }; 125dffa9051STero Kristo 126dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = { 127dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 128dffa9051STero Kristo { 0 }, 129dffa9051STero Kristo }; 130dffa9051STero Kristo 131dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { 132dffa9051STero Kristo { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" }, 133dffa9051STero Kristo { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" }, 134dffa9051STero Kristo { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" }, 135dffa9051STero Kristo { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" }, 136dffa9051STero Kristo { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" }, 137dffa9051STero Kristo { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 138dffa9051STero Kristo { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" }, 139dffa9051STero Kristo { 0 }, 140dffa9051STero Kristo }; 141dffa9051STero Kristo 142dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = { 143dffa9051STero Kristo { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" }, 144dffa9051STero Kristo { 0 }, 145dffa9051STero Kristo }; 146dffa9051STero Kristo 147dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { 148dffa9051STero Kristo { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 149dffa9051STero Kristo { 0 }, 150dffa9051STero Kristo }; 151dffa9051STero Kristo 152dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { 153dffa9051STero Kristo { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 154dffa9051STero Kristo { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 155dffa9051STero Kristo { 0 }, 156dffa9051STero Kristo }; 157dffa9051STero Kristo 158dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { 159dffa9051STero Kristo { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 160dffa9051STero Kristo { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 161dffa9051STero Kristo { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, 162dffa9051STero Kristo { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 163dffa9051STero Kristo { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 164dffa9051STero Kristo { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 165dffa9051STero Kristo { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 166dffa9051STero Kristo { 0 }, 167dffa9051STero Kristo }; 168dffa9051STero Kristo 169dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = { 170dffa9051STero Kristo { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, 171dffa9051STero Kristo { 0 }, 172dffa9051STero Kristo }; 173dffa9051STero Kristo 174dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { 175dffa9051STero Kristo { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 176dffa9051STero Kristo { 0 }, 177dffa9051STero Kristo }; 178dffa9051STero Kristo 179dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { 180dffa9051STero Kristo { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 181dffa9051STero Kristo { 0 }, 182dffa9051STero Kristo }; 183dffa9051STero Kristo 184dffa9051STero Kristo static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = { 185dffa9051STero Kristo "sys_32k_ck", 186dffa9051STero Kristo "video1_clkin_ck", 187dffa9051STero Kristo "video2_clkin_ck", 188dffa9051STero Kristo "hdmi_clkin_ck", 189dffa9051STero Kristo NULL, 190dffa9051STero Kristo }; 191dffa9051STero Kristo 192dffa9051STero Kristo static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { 193dffa9051STero Kristo "l3_iclk_div", 194dffa9051STero Kristo "dpll_abe_m2_ck", 195dffa9051STero Kristo "atl-clkctrl:0000:24", 196dffa9051STero Kristo NULL, 197dffa9051STero Kristo }; 198dffa9051STero Kristo 199dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = { 200dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL }, 201dffa9051STero Kristo { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL }, 202dffa9051STero Kristo { 0 }, 203dffa9051STero Kristo }; 204dffa9051STero Kristo 205dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { 206dffa9051STero Kristo { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" }, 207dffa9051STero Kristo { 0 }, 208dffa9051STero Kristo }; 209dffa9051STero Kristo 210dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { 211dffa9051STero Kristo { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, 212dffa9051STero Kristo { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, 213dffa9051STero Kristo { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 214dffa9051STero Kristo { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 215dffa9051STero Kristo { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 216dffa9051STero Kristo { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, 217dffa9051STero Kristo { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, 218dffa9051STero Kristo { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, 219dffa9051STero Kristo { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, 220dffa9051STero Kristo { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, 221dffa9051STero Kristo { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, 222dffa9051STero Kristo { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, 223dffa9051STero Kristo { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, 224dffa9051STero Kristo { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, 225dffa9051STero Kristo { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, 226dffa9051STero Kristo { 0 }, 227dffa9051STero Kristo }; 228dffa9051STero Kristo 229dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { 230dffa9051STero Kristo { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 231dffa9051STero Kristo { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 232dffa9051STero Kristo { 0 }, 233dffa9051STero Kristo }; 234dffa9051STero Kristo 235dffa9051STero Kristo static const char * const dra7_dss_dss_clk_parents[] __initconst = { 236dffa9051STero Kristo "dpll_per_h12x2_ck", 237dffa9051STero Kristo NULL, 238dffa9051STero Kristo }; 239dffa9051STero Kristo 240dffa9051STero Kristo static const char * const dra7_dss_48mhz_clk_parents[] __initconst = { 241dffa9051STero Kristo "func_48m_fclk", 242dffa9051STero Kristo NULL, 243dffa9051STero Kristo }; 244dffa9051STero Kristo 245dffa9051STero Kristo static const char * const dra7_dss_hdmi_clk_parents[] __initconst = { 246dffa9051STero Kristo "hdmi_dpll_clk_mux", 247dffa9051STero Kristo NULL, 248dffa9051STero Kristo }; 249dffa9051STero Kristo 250dffa9051STero Kristo static const char * const dra7_dss_32khz_clk_parents[] __initconst = { 251dffa9051STero Kristo "sys_32k_ck", 252dffa9051STero Kristo NULL, 253dffa9051STero Kristo }; 254dffa9051STero Kristo 255dffa9051STero Kristo static const char * const dra7_dss_video1_clk_parents[] __initconst = { 256dffa9051STero Kristo "video1_dpll_clk_mux", 257dffa9051STero Kristo NULL, 258dffa9051STero Kristo }; 259dffa9051STero Kristo 260dffa9051STero Kristo static const char * const dra7_dss_video2_clk_parents[] __initconst = { 261dffa9051STero Kristo "video2_dpll_clk_mux", 262dffa9051STero Kristo NULL, 263dffa9051STero Kristo }; 264dffa9051STero Kristo 265dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = { 266dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL }, 267dffa9051STero Kristo { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL }, 268dffa9051STero Kristo { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL }, 269dffa9051STero Kristo { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 270dffa9051STero Kristo { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL }, 271dffa9051STero Kristo { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL }, 272dffa9051STero Kristo { 0 }, 273dffa9051STero Kristo }; 274dffa9051STero Kristo 275dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { 276dffa9051STero Kristo { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" }, 277dffa9051STero Kristo { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, 278dffa9051STero Kristo { 0 }, 279dffa9051STero Kristo }; 280dffa9051STero Kristo 281dffa9051STero Kristo static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = { 282dffa9051STero Kristo "func_128m_clk", 283dffa9051STero Kristo "dpll_per_m2x2_ck", 284dffa9051STero Kristo NULL, 285dffa9051STero Kristo }; 286dffa9051STero Kristo 287dffa9051STero Kristo static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { 288dffa9051STero Kristo "l3init-clkctrl:0008:24", 289dffa9051STero Kristo NULL, 290dffa9051STero Kristo }; 291dffa9051STero Kristo 292dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = { 293dffa9051STero Kristo .max_div = 4, 294dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 295dffa9051STero Kristo }; 296dffa9051STero Kristo 297dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = { 298dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 299dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 300dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data }, 301dffa9051STero Kristo { 0 }, 302dffa9051STero Kristo }; 303dffa9051STero Kristo 304dffa9051STero Kristo static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { 305dffa9051STero Kristo "l3init-clkctrl:0010:24", 306dffa9051STero Kristo NULL, 307dffa9051STero Kristo }; 308dffa9051STero Kristo 309dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = { 310dffa9051STero Kristo .max_div = 4, 311dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 312dffa9051STero Kristo }; 313dffa9051STero Kristo 314dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = { 315dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 316dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 317dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data }, 318dffa9051STero Kristo { 0 }, 319dffa9051STero Kristo }; 320dffa9051STero Kristo 321dffa9051STero Kristo static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = { 322dffa9051STero Kristo "l3init_960m_gfclk", 323dffa9051STero Kristo NULL, 324dffa9051STero Kristo }; 325dffa9051STero Kristo 326dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = { 327dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 328dffa9051STero Kristo { 0 }, 329dffa9051STero Kristo }; 330dffa9051STero Kristo 331dffa9051STero Kristo static const char * const dra7_sata_ref_clk_parents[] __initconst = { 332dffa9051STero Kristo "sys_clkin1", 333dffa9051STero Kristo NULL, 334dffa9051STero Kristo }; 335dffa9051STero Kristo 336dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = { 337dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL }, 338dffa9051STero Kristo { 0 }, 339dffa9051STero Kristo }; 340dffa9051STero Kristo 341dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { 342dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 343dffa9051STero Kristo { 0 }, 344dffa9051STero Kristo }; 345dffa9051STero Kristo 346dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = { 347dffa9051STero Kristo { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" }, 348dffa9051STero Kristo { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, 349dffa9051STero Kristo { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 350dffa9051STero Kristo { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 3512b1202d7STero Kristo { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, 352dffa9051STero Kristo { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 353dffa9051STero Kristo { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 354dffa9051STero Kristo { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 355dffa9051STero Kristo { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 356dffa9051STero Kristo { 0 }, 357dffa9051STero Kristo }; 358dffa9051STero Kristo 359dffa9051STero Kristo static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { 360dffa9051STero Kristo "apll_pcie_ck", 361dffa9051STero Kristo NULL, 362dffa9051STero Kristo }; 363dffa9051STero Kristo 364dffa9051STero Kristo static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = { 365dffa9051STero Kristo "optfclk_pciephy_div", 366dffa9051STero Kristo NULL, 367dffa9051STero Kristo }; 368dffa9051STero Kristo 369dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = { 370dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 371dffa9051STero Kristo { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 372dffa9051STero Kristo { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 373dffa9051STero Kristo { 0 }, 374dffa9051STero Kristo }; 375dffa9051STero Kristo 376dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = { 377dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 378dffa9051STero Kristo { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 379dffa9051STero Kristo { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 380dffa9051STero Kristo { 0 }, 381dffa9051STero Kristo }; 382dffa9051STero Kristo 383dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = { 384dffa9051STero Kristo { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" }, 385dffa9051STero Kristo { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" }, 386dffa9051STero Kristo { 0 }, 387dffa9051STero Kristo }; 388dffa9051STero Kristo 389dffa9051STero Kristo static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { 390dffa9051STero Kristo "dpll_gmac_h11x2_ck", 391dffa9051STero Kristo "rmii_clk_ck", 392dffa9051STero Kristo NULL, 393dffa9051STero Kristo }; 394dffa9051STero Kristo 395dffa9051STero Kristo static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = { 396dffa9051STero Kristo "video1_clkin_ck", 397dffa9051STero Kristo "video2_clkin_ck", 398dffa9051STero Kristo "dpll_abe_m2_ck", 399dffa9051STero Kristo "hdmi_clkin_ck", 400dffa9051STero Kristo "l3_iclk_div", 401dffa9051STero Kristo NULL, 402dffa9051STero Kristo }; 403dffa9051STero Kristo 404dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { 405dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL }, 406dffa9051STero Kristo { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL }, 407dffa9051STero Kristo { 0 }, 408dffa9051STero Kristo }; 409dffa9051STero Kristo 410dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = { 411dffa9051STero Kristo { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" }, 412dffa9051STero Kristo { 0 }, 413dffa9051STero Kristo }; 414dffa9051STero Kristo 415dffa9051STero Kristo static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = { 416dffa9051STero Kristo "timer_sys_clk_div", 417dffa9051STero Kristo "sys_32k_ck", 418dffa9051STero Kristo "sys_clkin2", 419dffa9051STero Kristo "ref_clkin0_ck", 420dffa9051STero Kristo "ref_clkin1_ck", 421dffa9051STero Kristo "ref_clkin2_ck", 422dffa9051STero Kristo "ref_clkin3_ck", 423dffa9051STero Kristo "abe_giclk_div", 424dffa9051STero Kristo "video1_div_clk", 425dffa9051STero Kristo "video2_div_clk", 426dffa9051STero Kristo "hdmi_div_clk", 427dffa9051STero Kristo NULL, 428dffa9051STero Kristo }; 429dffa9051STero Kristo 430dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = { 431dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 432dffa9051STero Kristo { 0 }, 433dffa9051STero Kristo }; 434dffa9051STero Kristo 435dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = { 436dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 437dffa9051STero Kristo { 0 }, 438dffa9051STero Kristo }; 439dffa9051STero Kristo 440dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = { 441dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 442dffa9051STero Kristo { 0 }, 443dffa9051STero Kristo }; 444dffa9051STero Kristo 445dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = { 446dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 447dffa9051STero Kristo { 0 }, 448dffa9051STero Kristo }; 449dffa9051STero Kristo 450dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = { 451dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 452dffa9051STero Kristo { 0 }, 453dffa9051STero Kristo }; 454dffa9051STero Kristo 455dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = { 456dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 457dffa9051STero Kristo { 0 }, 458dffa9051STero Kristo }; 459dffa9051STero Kristo 460dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = { 461dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 462dffa9051STero Kristo { 0 }, 463dffa9051STero Kristo }; 464dffa9051STero Kristo 465dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = { 466dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 467dffa9051STero Kristo { 0 }, 468dffa9051STero Kristo }; 469dffa9051STero Kristo 470dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = { 471dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 472dffa9051STero Kristo { 0 }, 473dffa9051STero Kristo }; 474dffa9051STero Kristo 475dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = { 476dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 477dffa9051STero Kristo { 0 }, 478dffa9051STero Kristo }; 479dffa9051STero Kristo 480dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = { 481dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 482dffa9051STero Kristo { 0 }, 483dffa9051STero Kristo }; 484dffa9051STero Kristo 485dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { 486dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 487dffa9051STero Kristo { 0 }, 488dffa9051STero Kristo }; 489dffa9051STero Kristo 490dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = { 491dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 492dffa9051STero Kristo { 0 }, 493dffa9051STero Kristo }; 494dffa9051STero Kristo 495dffa9051STero Kristo static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { 496dffa9051STero Kristo "l4per-clkctrl:00f8:24", 497dffa9051STero Kristo NULL, 498dffa9051STero Kristo }; 499dffa9051STero Kristo 500dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = { 501dffa9051STero Kristo .max_div = 4, 502dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 503dffa9051STero Kristo }; 504dffa9051STero Kristo 505dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = { 506dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 507dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 508dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data }, 509dffa9051STero Kristo { 0 }, 510dffa9051STero Kristo }; 511dffa9051STero Kristo 512dffa9051STero Kristo static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { 513dffa9051STero Kristo "l4per-clkctrl:0100:24", 514dffa9051STero Kristo NULL, 515dffa9051STero Kristo }; 516dffa9051STero Kristo 517dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = { 518dffa9051STero Kristo .max_div = 4, 519dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 520dffa9051STero Kristo }; 521dffa9051STero Kristo 522dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = { 523dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 524dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 525dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data }, 526dffa9051STero Kristo { 0 }, 527dffa9051STero Kristo }; 528dffa9051STero Kristo 529dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = { 530dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 531dffa9051STero Kristo { 0 }, 532dffa9051STero Kristo }; 533dffa9051STero Kristo 534dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = { 535dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 536dffa9051STero Kristo { 0 }, 537dffa9051STero Kristo }; 538dffa9051STero Kristo 539dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = { 540dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 541dffa9051STero Kristo { 0 }, 542dffa9051STero Kristo }; 543dffa9051STero Kristo 544dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = { 545dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 546dffa9051STero Kristo { 0 }, 547dffa9051STero Kristo }; 548dffa9051STero Kristo 549dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = { 550dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 551dffa9051STero Kristo { 0 }, 552dffa9051STero Kristo }; 553dffa9051STero Kristo 554dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { 555dffa9051STero Kristo { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" }, 556dffa9051STero Kristo { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" }, 557dffa9051STero Kristo { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" }, 558dffa9051STero Kristo { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" }, 559dffa9051STero Kristo { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" }, 560dffa9051STero Kristo { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" }, 561dffa9051STero Kristo { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 562dffa9051STero Kristo { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 563dffa9051STero Kristo { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 564dffa9051STero Kristo { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 565dffa9051STero Kristo { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 566dffa9051STero Kristo { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 567dffa9051STero Kristo { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 568dffa9051STero Kristo { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 569dffa9051STero Kristo { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 570dffa9051STero Kristo { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 571dffa9051STero Kristo { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 572dffa9051STero Kristo { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 573dffa9051STero Kristo { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 574dffa9051STero Kristo { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 575dffa9051STero Kristo { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 576dffa9051STero Kristo { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 577dffa9051STero Kristo { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 578dffa9051STero Kristo { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 579dffa9051STero Kristo { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" }, 580dffa9051STero Kristo { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" }, 581dffa9051STero Kristo { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" }, 582dffa9051STero Kristo { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" }, 583dffa9051STero Kristo { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" }, 584dffa9051STero Kristo { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" }, 585dffa9051STero Kristo { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" }, 586dffa9051STero Kristo { 0 }, 587dffa9051STero Kristo }; 588dffa9051STero Kristo 589dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = { 590dffa9051STero Kristo { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 591dffa9051STero Kristo { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 592dffa9051STero Kristo { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 593869decd1STero Kristo { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, 594dffa9051STero Kristo { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 595dffa9051STero Kristo { 0 }, 596dffa9051STero Kristo }; 597dffa9051STero Kristo 598dffa9051STero Kristo static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = { 599dffa9051STero Kristo "func_128m_clk", 600dffa9051STero Kristo "dpll_per_h13x2_ck", 601dffa9051STero Kristo NULL, 602dffa9051STero Kristo }; 603dffa9051STero Kristo 604dffa9051STero Kristo static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { 605dffa9051STero Kristo "l4per2-clkctrl:012c:24", 606dffa9051STero Kristo NULL, 607dffa9051STero Kristo }; 608dffa9051STero Kristo 609dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = { 610dffa9051STero Kristo .max_div = 4, 611dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 612dffa9051STero Kristo }; 613dffa9051STero Kristo 614dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = { 615dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL }, 616dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data }, 617dffa9051STero Kristo { 0 }, 618dffa9051STero Kristo }; 619dffa9051STero Kristo 620dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { 621dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 622dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 623dffa9051STero Kristo { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 624dffa9051STero Kristo { 0 }, 625dffa9051STero Kristo }; 626dffa9051STero Kristo 627dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = { 628dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 629dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 630dffa9051STero Kristo { 0 }, 631dffa9051STero Kristo }; 632dffa9051STero Kristo 633dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { 634dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 635dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 636dffa9051STero Kristo { 0 }, 637dffa9051STero Kristo }; 638dffa9051STero Kristo 639dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = { 640dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 641dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 642dffa9051STero Kristo { 0 }, 643dffa9051STero Kristo }; 644dffa9051STero Kristo 645dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = { 646dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 647dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 648dffa9051STero Kristo { 0 }, 649dffa9051STero Kristo }; 650dffa9051STero Kristo 651dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = { 652dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 653dffa9051STero Kristo { 0 }, 654dffa9051STero Kristo }; 655dffa9051STero Kristo 656dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = { 657dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 658dffa9051STero Kristo { 0 }, 659dffa9051STero Kristo }; 660dffa9051STero Kristo 661dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = { 662dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 663dffa9051STero Kristo { 0 }, 664dffa9051STero Kristo }; 665dffa9051STero Kristo 666dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = { 667dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 668dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 669dffa9051STero Kristo { 0 }, 670dffa9051STero Kristo }; 671dffa9051STero Kristo 672dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = { 673dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 674dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 675dffa9051STero Kristo { 0 }, 676dffa9051STero Kristo }; 677dffa9051STero Kristo 678dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = { 679dffa9051STero Kristo { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 680dffa9051STero Kristo { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" }, 681dffa9051STero Kristo { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" }, 682dffa9051STero Kristo { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 683dffa9051STero Kristo { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 684dffa9051STero Kristo { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 685dffa9051STero Kristo { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" }, 686dffa9051STero Kristo { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" }, 687dffa9051STero Kristo { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" }, 688dffa9051STero Kristo { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" }, 689dffa9051STero Kristo { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" }, 690dffa9051STero Kristo { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" }, 691dffa9051STero Kristo { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" }, 692dffa9051STero Kristo { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" }, 693dffa9051STero Kristo { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" }, 694dffa9051STero Kristo { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" }, 695dffa9051STero Kristo { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" }, 696dffa9051STero Kristo { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" }, 697dffa9051STero Kristo { 0 }, 698dffa9051STero Kristo }; 699dffa9051STero Kristo 700dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = { 701dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 702dffa9051STero Kristo { 0 }, 703dffa9051STero Kristo }; 704dffa9051STero Kristo 705dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = { 706dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 707dffa9051STero Kristo { 0 }, 708dffa9051STero Kristo }; 709dffa9051STero Kristo 710dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = { 711dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 712dffa9051STero Kristo { 0 }, 713dffa9051STero Kristo }; 714dffa9051STero Kristo 715dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { 716dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 717dffa9051STero Kristo { 0 }, 718dffa9051STero Kristo }; 719dffa9051STero Kristo 720dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = { 721dffa9051STero Kristo { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 722dffa9051STero Kristo { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" }, 723dffa9051STero Kristo { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" }, 724dffa9051STero Kristo { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" }, 725dffa9051STero Kristo { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" }, 726dffa9051STero Kristo { 0 }, 727dffa9051STero Kristo }; 728dffa9051STero Kristo 729dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = { 730dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 731dffa9051STero Kristo { 0 }, 732dffa9051STero Kristo }; 733dffa9051STero Kristo 734dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = { 735dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 736dffa9051STero Kristo { 0 }, 737dffa9051STero Kristo }; 738dffa9051STero Kristo 739dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = { 740dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 741dffa9051STero Kristo { 0 }, 742dffa9051STero Kristo }; 743dffa9051STero Kristo 744dffa9051STero Kristo static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = { 745dffa9051STero Kristo "sys_clkin1", 746dffa9051STero Kristo "sys_clkin2", 747dffa9051STero Kristo NULL, 748dffa9051STero Kristo }; 749dffa9051STero Kristo 750dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = { 751dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL }, 752dffa9051STero Kristo { 0 }, 753dffa9051STero Kristo }; 754dffa9051STero Kristo 755dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { 756dffa9051STero Kristo { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 757dffa9051STero Kristo { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 758dffa9051STero Kristo { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 759dffa9051STero Kristo { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" }, 760869decd1STero Kristo { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" }, 761dffa9051STero Kristo { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 762dffa9051STero Kristo { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" }, 763dffa9051STero Kristo { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" }, 764dffa9051STero Kristo { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" }, 765dffa9051STero Kristo { 0 }, 766dffa9051STero Kristo }; 767dffa9051STero Kristo 768dffa9051STero Kristo const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { 769dffa9051STero Kristo { 0x4a005320, dra7_mpu_clkctrl_regs }, 770dffa9051STero Kristo { 0x4a005420, dra7_dsp1_clkctrl_regs }, 771dffa9051STero Kristo { 0x4a005520, dra7_ipu1_clkctrl_regs }, 772dffa9051STero Kristo { 0x4a005550, dra7_ipu_clkctrl_regs }, 773dffa9051STero Kristo { 0x4a005620, dra7_dsp2_clkctrl_regs }, 774dffa9051STero Kristo { 0x4a005720, dra7_rtc_clkctrl_regs }, 775dffa9051STero Kristo { 0x4a008620, dra7_coreaon_clkctrl_regs }, 776dffa9051STero Kristo { 0x4a008720, dra7_l3main1_clkctrl_regs }, 777dffa9051STero Kristo { 0x4a008920, dra7_ipu2_clkctrl_regs }, 778dffa9051STero Kristo { 0x4a008a20, dra7_dma_clkctrl_regs }, 779dffa9051STero Kristo { 0x4a008b20, dra7_emif_clkctrl_regs }, 780dffa9051STero Kristo { 0x4a008c00, dra7_atl_clkctrl_regs }, 781dffa9051STero Kristo { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, 782dffa9051STero Kristo { 0x4a008e20, dra7_l3instr_clkctrl_regs }, 783dffa9051STero Kristo { 0x4a009120, dra7_dss_clkctrl_regs }, 784dffa9051STero Kristo { 0x4a009320, dra7_l3init_clkctrl_regs }, 785dffa9051STero Kristo { 0x4a0093b0, dra7_pcie_clkctrl_regs }, 786dffa9051STero Kristo { 0x4a0093d0, dra7_gmac_clkctrl_regs }, 787dffa9051STero Kristo { 0x4a009728, dra7_l4per_clkctrl_regs }, 788dffa9051STero Kristo { 0x4a0098a0, dra7_l4sec_clkctrl_regs }, 789dffa9051STero Kristo { 0x4a00970c, dra7_l4per2_clkctrl_regs }, 790dffa9051STero Kristo { 0x4a009714, dra7_l4per3_clkctrl_regs }, 791dffa9051STero Kristo { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, 792dffa9051STero Kristo { 0 }, 793dffa9051STero Kristo }; 794dffa9051STero Kristo 795dffa9051STero Kristo static struct ti_dt_clk dra7xx_clks[] = { 796dffa9051STero Kristo DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 797dffa9051STero Kristo DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 798dffa9051STero Kristo DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 799dffa9051STero Kristo DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"), 800dffa9051STero Kristo DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"), 801dffa9051STero Kristo DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"), 802dffa9051STero Kristo DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"), 803dffa9051STero Kristo DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"), 804dffa9051STero Kristo DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"), 805dffa9051STero Kristo DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"), 806dffa9051STero Kristo DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"), 807dffa9051STero Kristo DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"), 808dffa9051STero Kristo DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"), 809dffa9051STero Kristo DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"), 810dffa9051STero Kristo DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"), 811dffa9051STero Kristo DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"), 812dffa9051STero Kristo DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"), 813dffa9051STero Kristo DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"), 814dffa9051STero Kristo DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"), 815dffa9051STero Kristo DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"), 816dffa9051STero Kristo DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"), 817dffa9051STero Kristo DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"), 818dffa9051STero Kristo DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"), 819dffa9051STero Kristo DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"), 820dffa9051STero Kristo DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"), 821dffa9051STero Kristo DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"), 822dffa9051STero Kristo DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"), 823dffa9051STero Kristo DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"), 824dffa9051STero Kristo DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"), 825dffa9051STero Kristo DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"), 826dffa9051STero Kristo DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"), 827dffa9051STero Kristo DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"), 828dffa9051STero Kristo DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"), 829dffa9051STero Kristo DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"), 830dffa9051STero Kristo DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"), 831dffa9051STero Kristo DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"), 832dffa9051STero Kristo DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"), 833dffa9051STero Kristo DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"), 834dffa9051STero Kristo DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"), 835dffa9051STero Kristo DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"), 836dffa9051STero Kristo DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"), 837dffa9051STero Kristo DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"), 838dffa9051STero Kristo DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), 839dffa9051STero Kristo DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"), 840dffa9051STero Kristo DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"), 841dffa9051STero Kristo DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), 842dffa9051STero Kristo DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"), 843dffa9051STero Kristo DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"), 844dffa9051STero Kristo DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"), 845dffa9051STero Kristo DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"), 846dffa9051STero Kristo DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"), 847dffa9051STero Kristo DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"), 848dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"), 849dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"), 850dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"), 851dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"), 852dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"), 853dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"), 854dffa9051STero Kristo DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"), 855dffa9051STero Kristo DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"), 856dffa9051STero Kristo DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"), 857dffa9051STero Kristo DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), 858dffa9051STero Kristo DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"), 859dffa9051STero Kristo DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"), 860dffa9051STero Kristo DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"), 861dffa9051STero Kristo DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"), 862dffa9051STero Kristo DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"), 863dffa9051STero Kristo DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"), 864dffa9051STero Kristo DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"), 865dffa9051STero Kristo DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"), 866dffa9051STero Kristo DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"), 867dffa9051STero Kristo DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"), 868dffa9051STero Kristo DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"), 869dffa9051STero Kristo DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"), 870dffa9051STero Kristo DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"), 871dffa9051STero Kristo DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"), 872dffa9051STero Kristo DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"), 873dffa9051STero Kristo DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"), 874dffa9051STero Kristo DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"), 875dffa9051STero Kristo DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"), 876dffa9051STero Kristo DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"), 877dffa9051STero Kristo DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"), 878dffa9051STero Kristo DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"), 879dffa9051STero Kristo DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"), 880dffa9051STero Kristo DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"), 881dffa9051STero Kristo DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"), 882dffa9051STero Kristo DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"), 883dffa9051STero Kristo DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"), 884dffa9051STero Kristo DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"), 885dffa9051STero Kristo { .node_name = NULL }, 886dffa9051STero Kristo }; 887dffa9051STero Kristo 888251a449dSTero Kristo int __init dra7xx_dt_clk_init(void) 889251a449dSTero Kristo { 890251a449dSTero Kristo int rc; 8914b3061b3SPeter Ujfalusi struct clk *dpll_ck, *hdcp_ck; 892251a449dSTero Kristo 893dffa9051STero Kristo if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) 89443c56e04STero Kristo ti_dt_clocks_register(dra7xx_compat_clks); 895dffa9051STero Kristo else 896dffa9051STero Kristo ti_dt_clocks_register(dra7xx_clks); 897251a449dSTero Kristo 898251a449dSTero Kristo omap2_clk_disable_autoidle_all(); 899251a449dSTero Kristo 900a8202cd5STero Kristo ti_clk_add_aliases(); 901a8202cd5STero Kristo 902251a449dSTero Kristo dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); 903251a449dSTero Kristo rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); 904251a449dSTero Kristo if (rc) 905251a449dSTero Kristo pr_err("%s: failed to configure GMAC DPLL!\n", __func__); 906251a449dSTero Kristo 90794e72ae5SRoger Quadros dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); 90894e72ae5SRoger Quadros rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); 90994e72ae5SRoger Quadros if (rc) 91094e72ae5SRoger Quadros pr_err("%s: failed to configure USB DPLL!\n", __func__); 91194e72ae5SRoger Quadros 91294e72ae5SRoger Quadros dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); 91394e72ae5SRoger Quadros rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); 91494e72ae5SRoger Quadros if (rc) 91594e72ae5SRoger Quadros pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 91694e72ae5SRoger Quadros 917f892b203STomi Valkeinen hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); 918f892b203STomi Valkeinen rc = clk_prepare_enable(hdcp_ck); 919f892b203STomi Valkeinen if (rc) 920f892b203STomi Valkeinen pr_err("%s: failed to set dss_deshdcp_clk\n", __func__); 921f892b203STomi Valkeinen 922251a449dSTero Kristo return rc; 923251a449dSTero Kristo } 924