1251a449dSTero Kristo /* 2251a449dSTero Kristo * DRA7 Clock init 3251a449dSTero Kristo * 4251a449dSTero Kristo * Copyright (C) 2013 Texas Instruments, Inc. 5251a449dSTero Kristo * 6251a449dSTero Kristo * Tero Kristo (t-kristo@ti.com) 7251a449dSTero Kristo * 8251a449dSTero Kristo * This program is free software; you can redistribute it and/or modify 9251a449dSTero Kristo * it under the terms of the GNU General Public License version 2 as 10251a449dSTero Kristo * published by the Free Software Foundation. 11251a449dSTero Kristo */ 12251a449dSTero Kristo 13251a449dSTero Kristo #include <linux/kernel.h> 14251a449dSTero Kristo #include <linux/list.h> 15251a449dSTero Kristo #include <linux/clk-private.h> 16251a449dSTero Kristo #include <linux/clkdev.h> 17251a449dSTero Kristo #include <linux/clk/ti.h> 18251a449dSTero Kristo 19251a449dSTero Kristo #define DRA7_DPLL_ABE_DEFFREQ 361267200 20251a449dSTero Kristo #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 21251a449dSTero Kristo 22251a449dSTero Kristo 23251a449dSTero Kristo static struct ti_dt_clk dra7xx_clks[] = { 24251a449dSTero Kristo DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), 25251a449dSTero Kristo DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), 26251a449dSTero Kristo DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), 270cccd919SPeter Ujfalusi DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"), 28251a449dSTero Kristo DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), 29251a449dSTero Kristo DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), 30251a449dSTero Kristo DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), 31251a449dSTero Kristo DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"), 32251a449dSTero Kristo DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"), 33251a449dSTero Kristo DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"), 34251a449dSTero Kristo DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"), 35251a449dSTero Kristo DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"), 36251a449dSTero Kristo DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"), 37251a449dSTero Kristo DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"), 38251a449dSTero Kristo DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), 39251a449dSTero Kristo DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 40251a449dSTero Kristo DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), 41251a449dSTero Kristo DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), 42251a449dSTero Kristo DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), 43251a449dSTero Kristo DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 44251a449dSTero Kristo DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"), 45251a449dSTero Kristo DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 46251a449dSTero Kristo DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), 47251a449dSTero Kristo DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), 48251a449dSTero Kristo DT_CLK(NULL, "sys_clkin1", "sys_clkin1"), 49251a449dSTero Kristo DT_CLK(NULL, "sys_clkin2", "sys_clkin2"), 50251a449dSTero Kristo DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"), 51251a449dSTero Kristo DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"), 52251a449dSTero Kristo DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"), 53251a449dSTero Kristo DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"), 54251a449dSTero Kristo DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"), 55251a449dSTero Kristo DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"), 56251a449dSTero Kristo DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), 57251a449dSTero Kristo DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), 58251a449dSTero Kristo DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), 59251a449dSTero Kristo DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), 60251a449dSTero Kristo DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), 61251a449dSTero Kristo DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), 62251a449dSTero Kristo DT_CLK(NULL, "abe_clk", "abe_clk"), 63251a449dSTero Kristo DT_CLK(NULL, "aess_fclk", "aess_fclk"), 64251a449dSTero Kristo DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"), 65251a449dSTero Kristo DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), 66251a449dSTero Kristo DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"), 67251a449dSTero Kristo DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"), 68251a449dSTero Kristo DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"), 69251a449dSTero Kristo DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"), 70251a449dSTero Kristo DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"), 71251a449dSTero Kristo DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"), 72251a449dSTero Kristo DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"), 73251a449dSTero Kristo DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"), 74251a449dSTero Kristo DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"), 75251a449dSTero Kristo DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"), 76251a449dSTero Kristo DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), 77251a449dSTero Kristo DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"), 78251a449dSTero Kristo DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), 79251a449dSTero Kristo DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 80251a449dSTero Kristo DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 81251a449dSTero Kristo DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), 82251a449dSTero Kristo DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), 83251a449dSTero Kristo DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 84251a449dSTero Kristo DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 85251a449dSTero Kristo DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"), 86251a449dSTero Kristo DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"), 87251a449dSTero Kristo DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"), 88251a449dSTero Kristo DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"), 89251a449dSTero Kristo DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"), 90251a449dSTero Kristo DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), 91251a449dSTero Kristo DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), 92251a449dSTero Kristo DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"), 93251a449dSTero Kristo DT_CLK(NULL, "iva_dclk", "iva_dclk"), 94251a449dSTero Kristo DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"), 95251a449dSTero Kristo DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"), 96251a449dSTero Kristo DT_CLK(NULL, "gpu_dclk", "gpu_dclk"), 97251a449dSTero Kristo DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), 98251a449dSTero Kristo DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"), 99251a449dSTero Kristo DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), 100251a449dSTero Kristo DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), 101251a449dSTero Kristo DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"), 102251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"), 103251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"), 104251a449dSTero Kristo DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"), 105251a449dSTero Kristo DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"), 106251a449dSTero Kristo DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"), 107251a449dSTero Kristo DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"), 108251a449dSTero Kristo DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), 109251a449dSTero Kristo DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 110251a449dSTero Kristo DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 111251a449dSTero Kristo DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"), 112251a449dSTero Kristo DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), 113251a449dSTero Kristo DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), 114251a449dSTero Kristo DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), 115251a449dSTero Kristo DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"), 116251a449dSTero Kristo DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"), 117251a449dSTero Kristo DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"), 118251a449dSTero Kristo DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"), 119251a449dSTero Kristo DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"), 120251a449dSTero Kristo DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"), 121251a449dSTero Kristo DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"), 122251a449dSTero Kristo DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"), 123251a449dSTero Kristo DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"), 124251a449dSTero Kristo DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"), 125251a449dSTero Kristo DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"), 126251a449dSTero Kristo DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"), 127251a449dSTero Kristo DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"), 128251a449dSTero Kristo DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"), 129251a449dSTero Kristo DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"), 130251a449dSTero Kristo DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), 131251a449dSTero Kristo DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), 132251a449dSTero Kristo DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), 133251a449dSTero Kristo DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), 134251a449dSTero Kristo DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), 135251a449dSTero Kristo DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), 136251a449dSTero Kristo DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), 137251a449dSTero Kristo DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"), 138251a449dSTero Kristo DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"), 139251a449dSTero Kristo DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"), 140251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"), 141251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"), 142251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"), 143251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"), 144251a449dSTero Kristo DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"), 145251a449dSTero Kristo DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), 146251a449dSTero Kristo DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), 147251a449dSTero Kristo DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), 148251a449dSTero Kristo DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"), 149251a449dSTero Kristo DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), 150251a449dSTero Kristo DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), 151251a449dSTero Kristo DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), 152251a449dSTero Kristo DT_CLK(NULL, "eve_clk", "eve_clk"), 153251a449dSTero Kristo DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), 154251a449dSTero Kristo DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), 155251a449dSTero Kristo DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), 156251a449dSTero Kristo DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), 157251a449dSTero Kristo DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), 158251a449dSTero Kristo DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"), 159251a449dSTero Kristo DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"), 160251a449dSTero Kristo DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"), 161251a449dSTero Kristo DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"), 162251a449dSTero Kristo DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), 163251a449dSTero Kristo DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), 164251a449dSTero Kristo DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), 165251a449dSTero Kristo DT_CLK(NULL, "mlb_clk", "mlb_clk"), 166251a449dSTero Kristo DT_CLK(NULL, "mlbp_clk", "mlbp_clk"), 167251a449dSTero Kristo DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"), 168251a449dSTero Kristo DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"), 169251a449dSTero Kristo DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"), 170251a449dSTero Kristo DT_CLK(NULL, "video1_div_clk", "video1_div_clk"), 171251a449dSTero Kristo DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"), 172251a449dSTero Kristo DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"), 173251a449dSTero Kristo DT_CLK(NULL, "video2_div_clk", "video2_div_clk"), 174251a449dSTero Kristo DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"), 175251a449dSTero Kristo DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), 176251a449dSTero Kristo DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), 177251a449dSTero Kristo DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), 178251a449dSTero Kristo DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), 179251a449dSTero Kristo DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), 180251a449dSTero Kristo DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), 181251a449dSTero Kristo DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), 182251a449dSTero Kristo DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 183251a449dSTero Kristo DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 184251a449dSTero Kristo DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 185251a449dSTero Kristo DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 186251a449dSTero Kristo DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 187251a449dSTero Kristo DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), 188251a449dSTero Kristo DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), 189251a449dSTero Kristo DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), 190251a449dSTero Kristo DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"), 191251a449dSTero Kristo DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"), 192251a449dSTero Kristo DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"), 193251a449dSTero Kristo DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"), 194251a449dSTero Kristo DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), 195251a449dSTero Kristo DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"), 196251a449dSTero Kristo DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"), 197251a449dSTero Kristo DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"), 198251a449dSTero Kristo DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"), 199251a449dSTero Kristo DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"), 200251a449dSTero Kristo DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"), 201251a449dSTero Kristo DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"), 202251a449dSTero Kristo DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"), 203251a449dSTero Kristo DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"), 204251a449dSTero Kristo DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"), 205251a449dSTero Kristo DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), 206251a449dSTero Kristo DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), 207251a449dSTero Kristo DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"), 208251a449dSTero Kristo DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), 209251a449dSTero Kristo DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"), 210251a449dSTero Kristo DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"), 211251a449dSTero Kristo DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"), 212251a449dSTero Kristo DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"), 213251a449dSTero Kristo DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"), 214251a449dSTero Kristo DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"), 215251a449dSTero Kristo DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"), 216251a449dSTero Kristo DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"), 217251a449dSTero Kristo DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"), 218251a449dSTero Kristo DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"), 219251a449dSTero Kristo DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"), 220251a449dSTero Kristo DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"), 221251a449dSTero Kristo DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"), 222251a449dSTero Kristo DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), 223251a449dSTero Kristo DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), 224251a449dSTero Kristo DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), 225251a449dSTero Kristo DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"), 226251a449dSTero Kristo DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), 227251a449dSTero Kristo DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), 228251a449dSTero Kristo DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), 229251a449dSTero Kristo DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), 230251a449dSTero Kristo DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"), 231251a449dSTero Kristo DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"), 232251a449dSTero Kristo DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"), 233251a449dSTero Kristo DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"), 234251a449dSTero Kristo DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"), 235251a449dSTero Kristo DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"), 236251a449dSTero Kristo DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"), 237251a449dSTero Kristo DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), 238251a449dSTero Kristo DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), 239251a449dSTero Kristo DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"), 240251a449dSTero Kristo DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"), 241251a449dSTero Kristo DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"), 242251a449dSTero Kristo DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"), 243251a449dSTero Kristo DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), 244251a449dSTero Kristo DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), 245251a449dSTero Kristo DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), 246251a449dSTero Kristo DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), 247251a449dSTero Kristo DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), 248251a449dSTero Kristo DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), 249251a449dSTero Kristo DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), 250251a449dSTero Kristo DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), 251251a449dSTero Kristo DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), 252251a449dSTero Kristo DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"), 253251a449dSTero Kristo DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"), 254251a449dSTero Kristo DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"), 255251a449dSTero Kristo DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"), 256251a449dSTero Kristo DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"), 257251a449dSTero Kristo DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"), 258251a449dSTero Kristo DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"), 259251a449dSTero Kristo DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"), 260251a449dSTero Kristo DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"), 261251a449dSTero Kristo DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"), 262251a449dSTero Kristo DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"), 263251a449dSTero Kristo DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"), 264251a449dSTero Kristo DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"), 265251a449dSTero Kristo DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 266251a449dSTero Kristo DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 267251a449dSTero Kristo DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 268251a449dSTero Kristo DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 269251a449dSTero Kristo DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 270251a449dSTero Kristo DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 271251a449dSTero Kristo DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 272251a449dSTero Kristo DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 273251a449dSTero Kristo DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 274251a449dSTero Kristo DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 275251a449dSTero Kristo DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 276251a449dSTero Kristo DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 277251a449dSTero Kristo DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 278251a449dSTero Kristo DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 279251a449dSTero Kristo DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 280251a449dSTero Kristo DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 281251a449dSTero Kristo DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 282251a449dSTero Kristo DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 283251a449dSTero Kristo DT_CLK(NULL, "uart1_ick", "dummy_ck"), 284251a449dSTero Kristo DT_CLK(NULL, "uart2_ick", "dummy_ck"), 285251a449dSTero Kristo DT_CLK(NULL, "uart3_ick", "dummy_ck"), 286251a449dSTero Kristo DT_CLK(NULL, "uart4_ick", "dummy_ck"), 287251a449dSTero Kristo DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 288251a449dSTero Kristo DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 289251a449dSTero Kristo DT_CLK("omap_wdt", "ick", "dummy_ck"), 290251a449dSTero Kristo DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 291251a449dSTero Kristo DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"), 292251a449dSTero Kristo DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"), 293251a449dSTero Kristo DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"), 294251a449dSTero Kristo DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"), 295251a449dSTero Kristo DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"), 296251a449dSTero Kristo DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"), 297251a449dSTero Kristo DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"), 298251a449dSTero Kristo DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), 299251a449dSTero Kristo DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), 300251a449dSTero Kristo DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), 301251a449dSTero Kristo DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), 302251a449dSTero Kristo DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 303251a449dSTero Kristo { .node_name = NULL }, 304251a449dSTero Kristo }; 305251a449dSTero Kristo 306251a449dSTero Kristo int __init dra7xx_dt_clk_init(void) 307251a449dSTero Kristo { 308251a449dSTero Kristo int rc; 309251a449dSTero Kristo struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; 310251a449dSTero Kristo 311251a449dSTero Kristo ti_dt_clocks_register(dra7xx_clks); 312251a449dSTero Kristo 313251a449dSTero Kristo omap2_clk_disable_autoidle_all(); 314251a449dSTero Kristo 315251a449dSTero Kristo abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); 316251a449dSTero Kristo sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); 317251a449dSTero Kristo dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); 318251a449dSTero Kristo 319251a449dSTero Kristo rc = clk_set_parent(abe_dpll_mux, sys_clkin2); 320251a449dSTero Kristo if (!rc) 321251a449dSTero Kristo rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); 322251a449dSTero Kristo if (rc) 323251a449dSTero Kristo pr_err("%s: failed to configure ABE DPLL!\n", __func__); 324251a449dSTero Kristo 325251a449dSTero Kristo dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); 326251a449dSTero Kristo rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); 327251a449dSTero Kristo if (rc) 328251a449dSTero Kristo pr_err("%s: failed to configure GMAC DPLL!\n", __func__); 329251a449dSTero Kristo 330251a449dSTero Kristo return rc; 331251a449dSTero Kristo } 332