1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP5 Clock init 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 * 7 * Tero Kristo (t-kristo@ti.com) 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/list.h> 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/io.h> 15 #include <linux/clk/ti.h> 16 #include <dt-bindings/clock/omap5.h> 17 18 #include "clock.h" 19 20 #define OMAP5_DPLL_ABE_DEFFREQ 98304000 21 22 /* 23 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings" 24 * states it must be at 960MHz 25 */ 26 #define OMAP5_DPLL_USB_DEFFREQ 960000000 27 28 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = { 29 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 30 { 0 }, 31 }; 32 33 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = { 34 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" }, 35 { 0 }, 36 }; 37 38 static const char * const omap5_aess_fclk_parents[] __initconst = { 39 "abe_clk", 40 NULL, 41 }; 42 43 static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = { 44 .max_div = 2, 45 }; 46 47 static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = { 48 { 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data }, 49 { 0 }, 50 }; 51 52 static const char * const omap5_dmic_gfclk_parents[] __initconst = { 53 "abe_cm:clk:0018:26", 54 "pad_clks_ck", 55 "slimbus_clk", 56 NULL, 57 }; 58 59 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = { 60 "abe_24m_fclk", 61 "dss_syc_gfclk_div", 62 "func_24m_clk", 63 NULL, 64 }; 65 66 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { 67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL }, 68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 69 { 0 }, 70 }; 71 72 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { 73 "abe_cm:clk:0028:26", 74 "pad_clks_ck", 75 "slimbus_clk", 76 NULL, 77 }; 78 79 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = { 80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL }, 81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 82 { 0 }, 83 }; 84 85 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { 86 "abe_cm:clk:0030:26", 87 "pad_clks_ck", 88 "slimbus_clk", 89 NULL, 90 }; 91 92 static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = { 93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL }, 94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 95 { 0 }, 96 }; 97 98 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { 99 "abe_cm:clk:0038:26", 100 "pad_clks_ck", 101 "slimbus_clk", 102 NULL, 103 }; 104 105 static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = { 106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL }, 107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 108 { 0 }, 109 }; 110 111 static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = { 112 "dss_syc_gfclk_div", 113 "sys_32k_ck", 114 NULL, 115 }; 116 117 static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = { 118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 119 { 0 }, 120 }; 121 122 static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = { 123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 124 { 0 }, 125 }; 126 127 static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = { 128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 129 { 0 }, 130 }; 131 132 static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = { 133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 134 { 0 }, 135 }; 136 137 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { 138 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, 139 { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, 140 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, 141 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, 142 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, 143 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, 144 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, 145 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, 146 { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, 147 { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, 148 { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, 149 { 0 }, 150 }; 151 152 static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = { 153 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 154 { 0 }, 155 }; 156 157 static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = { 158 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 159 { 0 }, 160 }; 161 162 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = { 163 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" }, 164 { 0 }, 165 }; 166 167 static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = { 168 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 169 { 0 }, 170 }; 171 172 static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = { 173 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 174 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 175 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 176 { 0 }, 177 }; 178 179 static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = { 180 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 181 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 182 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 183 { 0 }, 184 }; 185 186 static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = { 187 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 188 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 189 { 0 }, 190 }; 191 192 static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = { 193 "sys_clkin", 194 "sys_32k_ck", 195 NULL, 196 }; 197 198 static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = { 199 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 200 { 0 }, 201 }; 202 203 static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = { 204 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 205 { 0 }, 206 }; 207 208 static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = { 209 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 210 { 0 }, 211 }; 212 213 static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = { 214 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 215 { 0 }, 216 }; 217 218 static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = { 219 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 220 { 0 }, 221 }; 222 223 static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = { 224 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 225 { 0 }, 226 }; 227 228 static const char * const omap5_gpio2_dbclk_parents[] __initconst = { 229 "sys_32k_ck", 230 NULL, 231 }; 232 233 static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = { 234 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 235 { 0 }, 236 }; 237 238 static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = { 239 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 240 { 0 }, 241 }; 242 243 static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = { 244 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 245 { 0 }, 246 }; 247 248 static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = { 249 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 250 { 0 }, 251 }; 252 253 static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = { 254 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 255 { 0 }, 256 }; 257 258 static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = { 259 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 260 { 0 }, 261 }; 262 263 static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { 264 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 265 { 0 }, 266 }; 267 268 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { 269 { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, 270 { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, 271 { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, 272 { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, 273 { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 274 { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 275 { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 276 { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 277 { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 278 { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 279 { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 280 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 281 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 282 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 283 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 284 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 285 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 286 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 287 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 288 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 289 { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 290 { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 291 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 292 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 293 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 294 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 295 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 296 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 297 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 298 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 299 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 300 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 301 { 0 }, 302 }; 303 304 static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = { 305 { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, 306 { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, 307 { 0 }, 308 }; 309 310 static const char * const omap5_dss_dss_clk_parents[] __initconst = { 311 "dpll_per_h12x2_ck", 312 NULL, 313 }; 314 315 static const char * const omap5_dss_48mhz_clk_parents[] __initconst = { 316 "func_48m_fclk", 317 NULL, 318 }; 319 320 static const char * const omap5_dss_sys_clk_parents[] __initconst = { 321 "dss_syc_gfclk_div", 322 NULL, 323 }; 324 325 static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = { 326 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL }, 327 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL }, 328 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL }, 329 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 330 { 0 }, 331 }; 332 333 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { 334 { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 335 { 0 }, 336 }; 337 338 static const char * const omap5_gpu_core_mux_parents[] __initconst = { 339 "dpll_core_h14x2_ck", 340 "dpll_per_h14x2_ck", 341 NULL, 342 }; 343 344 static const char * const omap5_gpu_hyd_mux_parents[] __initconst = { 345 "dpll_core_h14x2_ck", 346 "dpll_per_h14x2_ck", 347 NULL, 348 }; 349 350 static const char * const omap5_gpu_sys_clk_parents[] __initconst = { 351 "sys_clkin", 352 NULL, 353 }; 354 355 static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = { 356 .max_div = 2, 357 }; 358 359 static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = { 360 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL }, 361 { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL }, 362 { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data }, 363 { 0 }, 364 }; 365 366 static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = { 367 { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" }, 368 { 0 }, 369 }; 370 371 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { 372 "func_128m_clk", 373 "dpll_per_m2x2_ck", 374 NULL, 375 }; 376 377 static const char * const omap5_mmc1_fclk_parents[] __initconst = { 378 "l3init_cm:clk:0008:24", 379 NULL, 380 }; 381 382 static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = { 383 .max_div = 2, 384 }; 385 386 static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { 387 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 388 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 389 { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data }, 390 { 0 }, 391 }; 392 393 static const char * const omap5_mmc2_fclk_parents[] __initconst = { 394 "l3init_cm:clk:0010:24", 395 NULL, 396 }; 397 398 static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = { 399 .max_div = 2, 400 }; 401 402 static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = { 403 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 404 { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data }, 405 { 0 }, 406 }; 407 408 static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = { 409 "l3init_60m_fclk", 410 NULL, 411 }; 412 413 static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = { 414 "dpll_usb_m2_ck", 415 NULL, 416 }; 417 418 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { 419 "l3init_cm:clk:0038:24", 420 NULL, 421 }; 422 423 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { 424 "l3init_cm:clk:0038:25", 425 NULL, 426 }; 427 428 static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = { 429 "l3init_60m_fclk", 430 "xclk60mhsp1_ck", 431 NULL, 432 }; 433 434 static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = { 435 "l3init_60m_fclk", 436 "xclk60mhsp2_ck", 437 NULL, 438 }; 439 440 static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = { 441 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 442 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 443 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL }, 444 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL }, 445 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 446 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 447 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 448 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 449 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 450 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL }, 451 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL }, 452 { 0 }, 453 }; 454 455 static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = { 456 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 457 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 458 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 459 { 0 }, 460 }; 461 462 static const char * const omap5_sata_ref_clk_parents[] __initconst = { 463 "sys_clkin", 464 NULL, 465 }; 466 467 static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = { 468 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL }, 469 { 0 }, 470 }; 471 472 static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = { 473 "dpll_usb_clkdcoldo", 474 NULL, 475 }; 476 477 static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = { 478 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL }, 479 { 0 }, 480 }; 481 482 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { 483 { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, 484 { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, 485 { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, 486 { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 487 { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 488 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 489 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 490 { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 491 { 0 }, 492 }; 493 494 static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = { 495 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 496 { 0 }, 497 }; 498 499 static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = { 500 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 501 { 0 }, 502 }; 503 504 static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = { 505 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 506 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 507 { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 508 { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 509 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 510 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 511 { 0 }, 512 }; 513 514 const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { 515 { 0x4a004320, omap5_mpu_clkctrl_regs }, 516 { 0x4a004420, omap5_dsp_clkctrl_regs }, 517 { 0x4a004520, omap5_abe_clkctrl_regs }, 518 { 0x4a008720, omap5_l3main1_clkctrl_regs }, 519 { 0x4a008820, omap5_l3main2_clkctrl_regs }, 520 { 0x4a008920, omap5_ipu_clkctrl_regs }, 521 { 0x4a008a20, omap5_dma_clkctrl_regs }, 522 { 0x4a008b20, omap5_emif_clkctrl_regs }, 523 { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, 524 { 0x4a008e20, omap5_l3instr_clkctrl_regs }, 525 { 0x4a009020, omap5_l4per_clkctrl_regs }, 526 { 0x4a009220, omap5_iva_clkctrl_regs }, 527 { 0x4a009420, omap5_dss_clkctrl_regs }, 528 { 0x4a009520, omap5_gpu_clkctrl_regs }, 529 { 0x4a009620, omap5_l3init_clkctrl_regs }, 530 { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, 531 { 0 }, 532 }; 533 534 static struct ti_dt_clk omap54xx_clks[] = { 535 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 536 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), 537 DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), 538 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), 539 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 540 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 541 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 542 DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), 543 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 544 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), 545 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), 546 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), 547 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), 548 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), 549 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), 550 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), 551 DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), 552 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), 553 DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), 554 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), 555 DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), 556 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), 557 DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), 558 DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), 559 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 560 DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), 561 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 562 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 563 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), 564 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), 565 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 566 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), 567 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), 568 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), 569 DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), 570 DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), 571 DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), 572 DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), 573 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), 574 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), 575 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), 576 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), 577 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), 578 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), 579 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), 580 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), 581 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), 582 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), 583 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), 584 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), 585 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), 586 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), 587 DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), 588 DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), 589 { .node_name = NULL }, 590 }; 591 592 int __init omap5xxx_dt_clk_init(void) 593 { 594 int rc; 595 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 596 597 ti_dt_clocks_register(omap54xx_clks); 598 599 omap2_clk_disable_autoidle_all(); 600 601 ti_clk_add_aliases(); 602 603 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); 604 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 605 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 606 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 607 if (!rc) 608 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); 609 if (rc) 610 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 611 612 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); 613 if (!rc) 614 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); 615 if (rc) 616 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); 617 618 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 619 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); 620 if (rc) 621 pr_err("%s: failed to configure USB DPLL!\n", __func__); 622 623 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); 624 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); 625 if (rc) 626 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 627 628 return 0; 629 } 630