1 /* 2 * OMAP5 Clock init 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo (t-kristo@ti.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/list.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/io.h> 18 #include <linux/clk/ti.h> 19 20 #include "clock.h" 21 22 #define OMAP5_DPLL_ABE_DEFFREQ 98304000 23 24 /* 25 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings" 26 * states it must be at 960MHz 27 */ 28 #define OMAP5_DPLL_USB_DEFFREQ 960000000 29 30 static struct ti_dt_clk omap54xx_clks[] = { 31 DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), 32 DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), 33 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), 34 DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), 35 DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), 36 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 37 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), 38 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), 39 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), 40 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 41 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 42 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), 43 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), 44 DT_CLK(NULL, "sys_clkin", "sys_clkin"), 45 DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), 46 DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), 47 DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), 48 DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), 49 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), 50 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), 51 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), 52 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), 53 DT_CLK(NULL, "abe_clk", "abe_clk"), 54 DT_CLK(NULL, "abe_iclk", "abe_iclk"), 55 DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), 56 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), 57 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 58 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 59 DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"), 60 DT_CLK(NULL, "c2c_fclk", "c2c_fclk"), 61 DT_CLK(NULL, "c2c_iclk", "c2c_iclk"), 62 DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), 63 DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"), 64 DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), 65 DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), 66 DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), 67 DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), 68 DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), 69 DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), 70 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), 71 DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), 72 DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), 73 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), 74 DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), 75 DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"), 76 DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"), 77 DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), 78 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 79 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 80 DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), 81 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 82 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), 83 DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), 84 DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), 85 DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), 86 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 87 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), 88 DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), 89 DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"), 90 DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"), 91 DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"), 92 DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"), 93 DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"), 94 DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"), 95 DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), 96 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), 97 DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), 98 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), 99 DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"), 100 DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), 101 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), 102 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), 103 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), 104 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), 105 DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), 106 DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"), 107 DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), 108 DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), 109 DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), 110 DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), 111 DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), 112 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), 113 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), 114 DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), 115 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 116 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 117 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 118 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 119 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 120 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), 121 DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), 122 DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), 123 DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), 124 DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"), 125 DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"), 126 DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"), 127 DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), 128 DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), 129 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), 130 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), 131 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"), 132 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), 133 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), 134 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"), 135 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), 136 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), 137 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), 138 DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"), 139 DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), 140 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), 141 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), 142 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), 143 DT_CLK(NULL, "aess_fclk", "aess_fclk"), 144 DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), 145 DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"), 146 DT_CLK(NULL, "fdif_fclk", "fdif_fclk"), 147 DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), 148 DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), 149 DT_CLK(NULL, "hsi_fclk", "hsi_fclk"), 150 DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), 151 DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"), 152 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), 153 DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"), 154 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), 155 DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"), 156 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), 157 DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"), 158 DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), 159 DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"), 160 DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), 161 DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"), 162 DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), 163 DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), 164 DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), 165 DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), 166 DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), 167 DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), 168 DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), 169 DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), 170 DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), 171 DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), 172 DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), 173 DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), 174 DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), 175 DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), 176 DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), 177 DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), 178 DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), 179 DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), 180 DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), 181 DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), 182 DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), 183 DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), 184 DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), 185 DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), 186 DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), 187 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 188 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 189 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 190 DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 191 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 192 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 193 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 194 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 195 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 196 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 197 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 198 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 199 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 200 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 201 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 202 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 203 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 204 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 205 DT_CLK(NULL, "uart1_ick", "dummy_ck"), 206 DT_CLK(NULL, "uart2_ick", "dummy_ck"), 207 DT_CLK(NULL, "uart3_ick", "dummy_ck"), 208 DT_CLK(NULL, "uart4_ick", "dummy_ck"), 209 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 210 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 211 DT_CLK("omap_wdt", "ick", "dummy_ck"), 212 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 213 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), 214 DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"), 215 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"), 216 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"), 217 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"), 218 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"), 219 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"), 220 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"), 221 DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 222 DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 223 DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 224 DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 225 { .node_name = NULL }, 226 }; 227 228 int __init omap5xxx_dt_clk_init(void) 229 { 230 int rc; 231 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 232 233 ti_dt_clocks_register(omap54xx_clks); 234 235 omap2_clk_disable_autoidle_all(); 236 237 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); 238 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 239 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 240 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 241 if (!rc) 242 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); 243 if (rc) 244 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 245 246 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); 247 if (!rc) 248 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); 249 if (rc) 250 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); 251 252 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 253 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); 254 if (rc) 255 pr_err("%s: failed to configure USB DPLL!\n", __func__); 256 257 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); 258 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); 259 if (rc) 260 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 261 262 return 0; 263 } 264