152b14728STero Kristo /* 252b14728STero Kristo * OMAP5 Clock init 352b14728STero Kristo * 452b14728STero Kristo * Copyright (C) 2013 Texas Instruments, Inc. 552b14728STero Kristo * 652b14728STero Kristo * Tero Kristo (t-kristo@ti.com) 752b14728STero Kristo * 852b14728STero Kristo * This program is free software; you can redistribute it and/or modify 952b14728STero Kristo * it under the terms of the GNU General Public License version 2 as 1052b14728STero Kristo * published by the Free Software Foundation. 1152b14728STero Kristo */ 1252b14728STero Kristo 1352b14728STero Kristo #include <linux/kernel.h> 1452b14728STero Kristo #include <linux/list.h> 15e387088aSStephen Boyd #include <linux/clk.h> 1652b14728STero Kristo #include <linux/clkdev.h> 1752b14728STero Kristo #include <linux/io.h> 1852b14728STero Kristo #include <linux/clk/ti.h> 190ad902f6STero Kristo #include <dt-bindings/clock/omap5.h> 2052b14728STero Kristo 21a3314e9cSTero Kristo #include "clock.h" 22a3314e9cSTero Kristo 2352b14728STero Kristo #define OMAP5_DPLL_ABE_DEFFREQ 98304000 2452b14728STero Kristo 2562125a46SRoger Quadros /* 2662125a46SRoger Quadros * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings" 2762125a46SRoger Quadros * states it must be at 960MHz 2862125a46SRoger Quadros */ 2962125a46SRoger Quadros #define OMAP5_DPLL_USB_DEFFREQ 960000000 3062125a46SRoger Quadros 310ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = { 320ad902f6STero Kristo { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 330ad902f6STero Kristo { 0 }, 340ad902f6STero Kristo }; 350ad902f6STero Kristo 360ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = { 370ad902f6STero Kristo { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" }, 380ad902f6STero Kristo { 0 }, 390ad902f6STero Kristo }; 400ad902f6STero Kristo 410ad902f6STero Kristo static const char * const omap5_dmic_gfclk_parents[] __initconst = { 420ad902f6STero Kristo "abe_cm:clk:0018:26", 430ad902f6STero Kristo "pad_clks_ck", 440ad902f6STero Kristo "slimbus_clk", 450ad902f6STero Kristo NULL, 460ad902f6STero Kristo }; 470ad902f6STero Kristo 480ad902f6STero Kristo static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = { 490ad902f6STero Kristo "abe_24m_fclk", 500ad902f6STero Kristo "dss_syc_gfclk_div", 510ad902f6STero Kristo "func_24m_clk", 520ad902f6STero Kristo NULL, 530ad902f6STero Kristo }; 540ad902f6STero Kristo 550ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { 560ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL }, 570ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 580ad902f6STero Kristo { 0 }, 590ad902f6STero Kristo }; 600ad902f6STero Kristo 610ad902f6STero Kristo static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { 620ad902f6STero Kristo "abe_cm:clk:0028:26", 630ad902f6STero Kristo "pad_clks_ck", 640ad902f6STero Kristo "slimbus_clk", 650ad902f6STero Kristo NULL, 660ad902f6STero Kristo }; 670ad902f6STero Kristo 680ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = { 690ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL }, 700ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 710ad902f6STero Kristo { 0 }, 720ad902f6STero Kristo }; 730ad902f6STero Kristo 740ad902f6STero Kristo static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { 750ad902f6STero Kristo "abe_cm:clk:0030:26", 760ad902f6STero Kristo "pad_clks_ck", 770ad902f6STero Kristo "slimbus_clk", 780ad902f6STero Kristo NULL, 790ad902f6STero Kristo }; 800ad902f6STero Kristo 810ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = { 820ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL }, 830ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 840ad902f6STero Kristo { 0 }, 850ad902f6STero Kristo }; 860ad902f6STero Kristo 870ad902f6STero Kristo static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { 880ad902f6STero Kristo "abe_cm:clk:0038:26", 890ad902f6STero Kristo "pad_clks_ck", 900ad902f6STero Kristo "slimbus_clk", 910ad902f6STero Kristo NULL, 920ad902f6STero Kristo }; 930ad902f6STero Kristo 940ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = { 950ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL }, 960ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 970ad902f6STero Kristo { 0 }, 980ad902f6STero Kristo }; 990ad902f6STero Kristo 1000ad902f6STero Kristo static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = { 1010ad902f6STero Kristo "dss_syc_gfclk_div", 1020ad902f6STero Kristo "sys_32k_ck", 1030ad902f6STero Kristo NULL, 1040ad902f6STero Kristo }; 1050ad902f6STero Kristo 1060ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = { 1070ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1080ad902f6STero Kristo { 0 }, 1090ad902f6STero Kristo }; 1100ad902f6STero Kristo 1110ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = { 1120ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1130ad902f6STero Kristo { 0 }, 1140ad902f6STero Kristo }; 1150ad902f6STero Kristo 1160ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = { 1170ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1180ad902f6STero Kristo { 0 }, 1190ad902f6STero Kristo }; 1200ad902f6STero Kristo 1210ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = { 1220ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1230ad902f6STero Kristo { 0 }, 1240ad902f6STero Kristo }; 1250ad902f6STero Kristo 1260ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { 1270ad902f6STero Kristo { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, 1280ad902f6STero Kristo { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, 1290ad902f6STero Kristo { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, 1300ad902f6STero Kristo { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, 1310ad902f6STero Kristo { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, 1320ad902f6STero Kristo { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, 1330ad902f6STero Kristo { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, 1340ad902f6STero Kristo { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, 1350ad902f6STero Kristo { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, 1360ad902f6STero Kristo { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, 1370ad902f6STero Kristo { 0 }, 1380ad902f6STero Kristo }; 1390ad902f6STero Kristo 1400ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = { 1410ad902f6STero Kristo { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1420ad902f6STero Kristo { 0 }, 1430ad902f6STero Kristo }; 1440ad902f6STero Kristo 1450ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = { 1460ad902f6STero Kristo { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1470ad902f6STero Kristo { 0 }, 1480ad902f6STero Kristo }; 1490ad902f6STero Kristo 1500ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = { 1510ad902f6STero Kristo { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, 1520ad902f6STero Kristo { 0 }, 1530ad902f6STero Kristo }; 1540ad902f6STero Kristo 1550ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = { 1560ad902f6STero Kristo { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1570ad902f6STero Kristo { 0 }, 1580ad902f6STero Kristo }; 1590ad902f6STero Kristo 1600ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = { 1610ad902f6STero Kristo { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1620ad902f6STero Kristo { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 1630ad902f6STero Kristo { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 1640ad902f6STero Kristo { 0 }, 1650ad902f6STero Kristo }; 1660ad902f6STero Kristo 1670ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = { 1680ad902f6STero Kristo { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 1690ad902f6STero Kristo { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 1700ad902f6STero Kristo { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 1710ad902f6STero Kristo { 0 }, 1720ad902f6STero Kristo }; 1730ad902f6STero Kristo 1740ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = { 1750ad902f6STero Kristo { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 1760ad902f6STero Kristo { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 1770ad902f6STero Kristo { 0 }, 1780ad902f6STero Kristo }; 1790ad902f6STero Kristo 1800ad902f6STero Kristo static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = { 1810ad902f6STero Kristo "sys_clkin", 1820ad902f6STero Kristo "sys_32k_ck", 1830ad902f6STero Kristo NULL, 1840ad902f6STero Kristo }; 1850ad902f6STero Kristo 1860ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = { 1870ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 1880ad902f6STero Kristo { 0 }, 1890ad902f6STero Kristo }; 1900ad902f6STero Kristo 1910ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = { 1920ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 1930ad902f6STero Kristo { 0 }, 1940ad902f6STero Kristo }; 1950ad902f6STero Kristo 1960ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = { 1970ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 1980ad902f6STero Kristo { 0 }, 1990ad902f6STero Kristo }; 2000ad902f6STero Kristo 2010ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = { 2020ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 2030ad902f6STero Kristo { 0 }, 2040ad902f6STero Kristo }; 2050ad902f6STero Kristo 2060ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = { 2070ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 2080ad902f6STero Kristo { 0 }, 2090ad902f6STero Kristo }; 2100ad902f6STero Kristo 2110ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = { 2120ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 2130ad902f6STero Kristo { 0 }, 2140ad902f6STero Kristo }; 2150ad902f6STero Kristo 2160ad902f6STero Kristo static const char * const omap5_gpio2_dbclk_parents[] __initconst = { 2170ad902f6STero Kristo "sys_32k_ck", 2180ad902f6STero Kristo NULL, 2190ad902f6STero Kristo }; 2200ad902f6STero Kristo 2210ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = { 2220ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2230ad902f6STero Kristo { 0 }, 2240ad902f6STero Kristo }; 2250ad902f6STero Kristo 2260ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = { 2270ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2280ad902f6STero Kristo { 0 }, 2290ad902f6STero Kristo }; 2300ad902f6STero Kristo 2310ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = { 2320ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2330ad902f6STero Kristo { 0 }, 2340ad902f6STero Kristo }; 2350ad902f6STero Kristo 2360ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = { 2370ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2380ad902f6STero Kristo { 0 }, 2390ad902f6STero Kristo }; 2400ad902f6STero Kristo 2410ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = { 2420ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2430ad902f6STero Kristo { 0 }, 2440ad902f6STero Kristo }; 2450ad902f6STero Kristo 2460ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = { 2470ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2480ad902f6STero Kristo { 0 }, 2490ad902f6STero Kristo }; 2500ad902f6STero Kristo 2510ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { 2520ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2530ad902f6STero Kristo { 0 }, 2540ad902f6STero Kristo }; 2550ad902f6STero Kristo 2560ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { 2570ad902f6STero Kristo { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, 2580ad902f6STero Kristo { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, 2590ad902f6STero Kristo { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, 2600ad902f6STero Kristo { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, 2610ad902f6STero Kristo { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 2620ad902f6STero Kristo { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 2630ad902f6STero Kristo { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2640ad902f6STero Kristo { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2650ad902f6STero Kristo { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2660ad902f6STero Kristo { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2670ad902f6STero Kristo { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2680ad902f6STero Kristo { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2690ad902f6STero Kristo { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2700ad902f6STero Kristo { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2710ad902f6STero Kristo { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2720ad902f6STero Kristo { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 2730ad902f6STero Kristo { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2740ad902f6STero Kristo { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2750ad902f6STero Kristo { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2760ad902f6STero Kristo { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2770ad902f6STero Kristo { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2780ad902f6STero Kristo { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2790ad902f6STero Kristo { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2800ad902f6STero Kristo { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2810ad902f6STero Kristo { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2820ad902f6STero Kristo { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2830ad902f6STero Kristo { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2840ad902f6STero Kristo { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2850ad902f6STero Kristo { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2860ad902f6STero Kristo { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2870ad902f6STero Kristo { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2880ad902f6STero Kristo { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2890ad902f6STero Kristo { 0 }, 2900ad902f6STero Kristo }; 2910ad902f6STero Kristo 2920ad902f6STero Kristo static const char * const omap5_dss_dss_clk_parents[] __initconst = { 2930ad902f6STero Kristo "dpll_per_h12x2_ck", 2940ad902f6STero Kristo NULL, 2950ad902f6STero Kristo }; 2960ad902f6STero Kristo 2970ad902f6STero Kristo static const char * const omap5_dss_48mhz_clk_parents[] __initconst = { 2980ad902f6STero Kristo "func_48m_fclk", 2990ad902f6STero Kristo NULL, 3000ad902f6STero Kristo }; 3010ad902f6STero Kristo 3020ad902f6STero Kristo static const char * const omap5_dss_sys_clk_parents[] __initconst = { 3030ad902f6STero Kristo "dss_syc_gfclk_div", 3040ad902f6STero Kristo NULL, 3050ad902f6STero Kristo }; 3060ad902f6STero Kristo 3070ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = { 3080ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL }, 3090ad902f6STero Kristo { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL }, 3100ad902f6STero Kristo { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL }, 3110ad902f6STero Kristo { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 3120ad902f6STero Kristo { 0 }, 3130ad902f6STero Kristo }; 3140ad902f6STero Kristo 3150ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { 3160ad902f6STero Kristo { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 3170ad902f6STero Kristo { 0 }, 3180ad902f6STero Kristo }; 3190ad902f6STero Kristo 3200ad902f6STero Kristo static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { 3210ad902f6STero Kristo "func_128m_clk", 3220ad902f6STero Kristo "dpll_per_m2x2_ck", 3230ad902f6STero Kristo NULL, 3240ad902f6STero Kristo }; 3250ad902f6STero Kristo 3260ad902f6STero Kristo static const char * const omap5_mmc1_fclk_parents[] __initconst = { 3270ad902f6STero Kristo "l3init_cm:clk:0008:24", 3280ad902f6STero Kristo NULL, 3290ad902f6STero Kristo }; 3300ad902f6STero Kristo 3310ad902f6STero Kristo static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = { 3320ad902f6STero Kristo .max_div = 2, 3330ad902f6STero Kristo }; 3340ad902f6STero Kristo 3350ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { 3360ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 3370ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 3380ad902f6STero Kristo { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data }, 3390ad902f6STero Kristo { 0 }, 3400ad902f6STero Kristo }; 3410ad902f6STero Kristo 3420ad902f6STero Kristo static const char * const omap5_mmc2_fclk_parents[] __initconst = { 3430ad902f6STero Kristo "l3init_cm:clk:0010:24", 3440ad902f6STero Kristo NULL, 3450ad902f6STero Kristo }; 3460ad902f6STero Kristo 3470ad902f6STero Kristo static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = { 3480ad902f6STero Kristo .max_div = 2, 3490ad902f6STero Kristo }; 3500ad902f6STero Kristo 3510ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = { 3520ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 3530ad902f6STero Kristo { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data }, 3540ad902f6STero Kristo { 0 }, 3550ad902f6STero Kristo }; 3560ad902f6STero Kristo 3570ad902f6STero Kristo static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = { 3580ad902f6STero Kristo "l3init_60m_fclk", 3590ad902f6STero Kristo NULL, 3600ad902f6STero Kristo }; 3610ad902f6STero Kristo 3620ad902f6STero Kristo static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = { 3630ad902f6STero Kristo "dpll_usb_m2_ck", 3640ad902f6STero Kristo NULL, 3650ad902f6STero Kristo }; 3660ad902f6STero Kristo 3670ad902f6STero Kristo static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { 3680ad902f6STero Kristo "l3init_cm:clk:0038:24", 3690ad902f6STero Kristo NULL, 3700ad902f6STero Kristo }; 3710ad902f6STero Kristo 3720ad902f6STero Kristo static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { 3730ad902f6STero Kristo "l3init_cm:clk:0038:25", 3740ad902f6STero Kristo NULL, 3750ad902f6STero Kristo }; 3760ad902f6STero Kristo 3770ad902f6STero Kristo static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = { 3780ad902f6STero Kristo "l3init_60m_fclk", 3790ad902f6STero Kristo "xclk60mhsp1_ck", 3800ad902f6STero Kristo NULL, 3810ad902f6STero Kristo }; 3820ad902f6STero Kristo 3830ad902f6STero Kristo static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = { 3840ad902f6STero Kristo "l3init_60m_fclk", 3850ad902f6STero Kristo "xclk60mhsp2_ck", 3860ad902f6STero Kristo NULL, 3870ad902f6STero Kristo }; 3880ad902f6STero Kristo 3890ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = { 3900ad902f6STero Kristo { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 3910ad902f6STero Kristo { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 3920ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL }, 3930ad902f6STero Kristo { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL }, 3940ad902f6STero Kristo { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 3950ad902f6STero Kristo { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 3960ad902f6STero Kristo { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 3970ad902f6STero Kristo { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 3980ad902f6STero Kristo { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 3990ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL }, 4000ad902f6STero Kristo { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL }, 4010ad902f6STero Kristo { 0 }, 4020ad902f6STero Kristo }; 4030ad902f6STero Kristo 4040ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = { 4050ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4060ad902f6STero Kristo { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4070ad902f6STero Kristo { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4080ad902f6STero Kristo { 0 }, 4090ad902f6STero Kristo }; 4100ad902f6STero Kristo 4110ad902f6STero Kristo static const char * const omap5_sata_ref_clk_parents[] __initconst = { 4120ad902f6STero Kristo "sys_clkin", 4130ad902f6STero Kristo NULL, 4140ad902f6STero Kristo }; 4150ad902f6STero Kristo 4160ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = { 4170ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL }, 4180ad902f6STero Kristo { 0 }, 4190ad902f6STero Kristo }; 4200ad902f6STero Kristo 4210ad902f6STero Kristo static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = { 4220ad902f6STero Kristo "dpll_usb_clkdcoldo", 4230ad902f6STero Kristo NULL, 4240ad902f6STero Kristo }; 4250ad902f6STero Kristo 4260ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = { 4270ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL }, 4280ad902f6STero Kristo { 0 }, 4290ad902f6STero Kristo }; 4300ad902f6STero Kristo 4310ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { 4320ad902f6STero Kristo { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, 4330ad902f6STero Kristo { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, 4340ad902f6STero Kristo { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, 4350ad902f6STero Kristo { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 4360ad902f6STero Kristo { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 4370ad902f6STero Kristo { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 4380ad902f6STero Kristo { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 4390ad902f6STero Kristo { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 4400ad902f6STero Kristo { 0 }, 4410ad902f6STero Kristo }; 4420ad902f6STero Kristo 4430ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = { 4440ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 4450ad902f6STero Kristo { 0 }, 4460ad902f6STero Kristo }; 4470ad902f6STero Kristo 4480ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = { 4490ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 4500ad902f6STero Kristo { 0 }, 4510ad902f6STero Kristo }; 4520ad902f6STero Kristo 4530ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = { 4540ad902f6STero Kristo { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 4550ad902f6STero Kristo { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 4560ad902f6STero Kristo { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 4570ad902f6STero Kristo { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 4580ad902f6STero Kristo { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 4590ad902f6STero Kristo { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 4600ad902f6STero Kristo { 0 }, 4610ad902f6STero Kristo }; 4620ad902f6STero Kristo 4630ad902f6STero Kristo const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { 4640ad902f6STero Kristo { 0x4a004320, omap5_mpu_clkctrl_regs }, 4650ad902f6STero Kristo { 0x4a004420, omap5_dsp_clkctrl_regs }, 4660ad902f6STero Kristo { 0x4a004520, omap5_abe_clkctrl_regs }, 4670ad902f6STero Kristo { 0x4a008720, omap5_l3main1_clkctrl_regs }, 4680ad902f6STero Kristo { 0x4a008820, omap5_l3main2_clkctrl_regs }, 4690ad902f6STero Kristo { 0x4a008920, omap5_ipu_clkctrl_regs }, 4700ad902f6STero Kristo { 0x4a008a20, omap5_dma_clkctrl_regs }, 4710ad902f6STero Kristo { 0x4a008b20, omap5_emif_clkctrl_regs }, 4720ad902f6STero Kristo { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, 4730ad902f6STero Kristo { 0x4a008e20, omap5_l3instr_clkctrl_regs }, 4740ad902f6STero Kristo { 0x4a009020, omap5_l4per_clkctrl_regs }, 4750ad902f6STero Kristo { 0x4a009420, omap5_dss_clkctrl_regs }, 4760ad902f6STero Kristo { 0x4a009620, omap5_l3init_clkctrl_regs }, 4770ad902f6STero Kristo { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, 4780ad902f6STero Kristo { 0 }, 4790ad902f6STero Kristo }; 4800ad902f6STero Kristo 48152b14728STero Kristo static struct ti_dt_clk omap54xx_clks[] = { 48252b14728STero Kristo DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 483d5630b7aSGrygorii Strashko DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), 4840ad902f6STero Kristo DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), 4850ad902f6STero Kristo DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), 4860ad902f6STero Kristo DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 4870ad902f6STero Kristo DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 4880ad902f6STero Kristo DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 4890ad902f6STero Kristo DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), 4900ad902f6STero Kristo DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 4910ad902f6STero Kristo DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), 4920ad902f6STero Kristo DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), 4930ad902f6STero Kristo DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), 4940ad902f6STero Kristo DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), 4950ad902f6STero Kristo DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), 4960ad902f6STero Kristo DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), 4970ad902f6STero Kristo DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), 4980ad902f6STero Kristo DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), 4990ad902f6STero Kristo DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), 5000ad902f6STero Kristo DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), 5010ad902f6STero Kristo DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), 5020ad902f6STero Kristo DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), 5030ad902f6STero Kristo DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), 5040ad902f6STero Kristo DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), 5050ad902f6STero Kristo DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), 5060ad902f6STero Kristo DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 5070ad902f6STero Kristo DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), 5080ad902f6STero Kristo DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 5090ad902f6STero Kristo DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 5100ad902f6STero Kristo DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), 5110ad902f6STero Kristo DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), 5120ad902f6STero Kristo DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 5130ad902f6STero Kristo DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), 5140ad902f6STero Kristo DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), 5150ad902f6STero Kristo DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), 5160ad902f6STero Kristo DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), 5170ad902f6STero Kristo DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), 5180ad902f6STero Kristo DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), 5190ad902f6STero Kristo DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), 5200ad902f6STero Kristo DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), 5210ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), 5220ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), 5230ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), 5240ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), 5250ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), 5260ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), 5270ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), 5280ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), 5290ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), 5300ad902f6STero Kristo DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), 5310ad902f6STero Kristo DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), 5320ad902f6STero Kristo DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), 5330ad902f6STero Kristo DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), 5340ad902f6STero Kristo DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), 5350ad902f6STero Kristo DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), 53652b14728STero Kristo { .node_name = NULL }, 53752b14728STero Kristo }; 53852b14728STero Kristo 53952b14728STero Kristo int __init omap5xxx_dt_clk_init(void) 54052b14728STero Kristo { 54152b14728STero Kristo int rc; 54262125a46SRoger Quadros struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 54352b14728STero Kristo 54452b14728STero Kristo ti_dt_clocks_register(omap54xx_clks); 54552b14728STero Kristo 54652b14728STero Kristo omap2_clk_disable_autoidle_all(); 54752b14728STero Kristo 548d41e5304STero Kristo ti_clk_add_aliases(); 549d41e5304STero Kristo 55052b14728STero Kristo abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); 55152b14728STero Kristo sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 55252b14728STero Kristo rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 55352b14728STero Kristo abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 55452b14728STero Kristo if (!rc) 55552b14728STero Kristo rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); 55652b14728STero Kristo if (rc) 55752b14728STero Kristo pr_err("%s: failed to configure ABE DPLL!\n", __func__); 55852b14728STero Kristo 55981c7e03aSPeter Ujfalusi abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); 56081c7e03aSPeter Ujfalusi if (!rc) 56181c7e03aSPeter Ujfalusi rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); 56281c7e03aSPeter Ujfalusi if (rc) 56381c7e03aSPeter Ujfalusi pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); 56481c7e03aSPeter Ujfalusi 56562125a46SRoger Quadros usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 56662125a46SRoger Quadros rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); 56762125a46SRoger Quadros if (rc) 56862125a46SRoger Quadros pr_err("%s: failed to configure USB DPLL!\n", __func__); 56962125a46SRoger Quadros 57062125a46SRoger Quadros usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); 57162125a46SRoger Quadros rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); 57262125a46SRoger Quadros if (rc) 57362125a46SRoger Quadros pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 57462125a46SRoger Quadros 57552b14728STero Kristo return 0; 57652b14728STero Kristo } 577