1 /* 2 * OMAP4 Clock init 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo (t-kristo@ti.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/list.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/clk/ti.h> 18 19 #include "clock.h" 20 21 /* 22 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section 23 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK 24 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is 25 * half of this value. 26 */ 27 #define OMAP4_DPLL_ABE_DEFFREQ 98304000 28 29 /* 30 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section 31 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred 32 * locked frequency for the USB DPLL is 960MHz. 33 */ 34 #define OMAP4_DPLL_USB_DEFFREQ 960000000 35 36 static struct ti_dt_clk omap44xx_clks[] = { 37 DT_CLK("smp_twd", NULL, "mpu_periphclk"), 38 DT_CLK("omapdss_dss", "ick", "dss_fck"), 39 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), 40 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"), 41 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"), 42 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"), 43 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"), 44 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 45 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 46 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 47 DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 48 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 49 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 50 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 51 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 52 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 53 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 54 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 55 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 56 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 57 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 58 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 59 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 60 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 61 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 62 DT_CLK(NULL, "uart1_ick", "dummy_ck"), 63 DT_CLK(NULL, "uart2_ick", "dummy_ck"), 64 DT_CLK(NULL, "uart3_ick", "dummy_ck"), 65 DT_CLK(NULL, "uart4_ick", "dummy_ck"), 66 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 67 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 68 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"), 69 DT_CLK("omap_wdt", "ick", "dummy_ck"), 70 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 71 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), 72 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), 73 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), 74 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"), 75 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"), 76 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"), 77 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"), 78 DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"), 79 DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"), 80 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), 81 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), 82 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), 83 { .node_name = NULL }, 84 }; 85 86 int __init omap4xxx_dt_clk_init(void) 87 { 88 int rc; 89 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 90 91 ti_dt_clocks_register(omap44xx_clks); 92 93 omap2_clk_disable_autoidle_all(); 94 95 ti_clk_add_aliases(); 96 97 /* 98 * Lock USB DPLL on OMAP4 devices so that the L3INIT power 99 * domain can transition to retention state when not in use. 100 */ 101 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 102 rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); 103 if (rc) 104 pr_err("%s: failed to configure USB DPLL!\n", __func__); 105 106 /* 107 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 108 * state when turning the ABE clock domain. Workaround this by 109 * locking the ABE DPLL on boot. 110 * Lock the ABE DPLL in any case to avoid issues with audio. 111 */ 112 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); 113 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 114 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 115 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 116 if (!rc) 117 rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); 118 if (rc) 119 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 120 121 return 0; 122 } 123