xref: /openbmc/linux/drivers/clk/ti/clk-44xx.c (revision 2359ccdd)
1 /*
2  * OMAP4 Clock init
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * Tero Kristo (t-kristo@ti.com)
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/clk/ti.h>
18 #include <dt-bindings/clock/omap4.h>
19 
20 #include "clock.h"
21 
22 /*
23  * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
24  * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
25  * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
26  * half of this value.
27  */
28 #define OMAP4_DPLL_ABE_DEFFREQ				98304000
29 
30 /*
31  * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
32  * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
33  * locked frequency for the USB DPLL is 960MHz.
34  */
35 #define OMAP4_DPLL_USB_DEFFREQ				960000000
36 
37 static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
38 	{ OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
39 	{ 0 },
40 };
41 
42 static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
43 	{ OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" },
44 	{ 0 },
45 };
46 
47 static const char * const omap4_aess_fclk_parents[] __initconst = {
48 	"abe_clk",
49 	NULL,
50 };
51 
52 static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
53 	.max_div = 2,
54 };
55 
56 static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
57 	{ 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
58 	{ 0 },
59 };
60 
61 static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
62 	"abe_cm:clk:0018:26",
63 	"pad_clks_ck",
64 	"slimbus_clk",
65 	NULL,
66 };
67 
68 static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
69 	"abe_24m_fclk",
70 	"syc_clk_div_ck",
71 	"func_24m_clk",
72 	NULL,
73 };
74 
75 static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
76 	{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
77 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
78 	{ 0 },
79 };
80 
81 static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
82 	"abe_cm:clk:0020:26",
83 	"pad_clks_ck",
84 	"slimbus_clk",
85 	NULL,
86 };
87 
88 static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
89 	{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
90 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
91 	{ 0 },
92 };
93 
94 static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
95 	"abe_cm:clk:0028:26",
96 	"pad_clks_ck",
97 	"slimbus_clk",
98 	NULL,
99 };
100 
101 static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
102 	{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
103 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
104 	{ 0 },
105 };
106 
107 static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
108 	"abe_cm:clk:0030:26",
109 	"pad_clks_ck",
110 	"slimbus_clk",
111 	NULL,
112 };
113 
114 static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
115 	{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
116 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
117 	{ 0 },
118 };
119 
120 static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
121 	"abe_cm:clk:0038:26",
122 	"pad_clks_ck",
123 	"slimbus_clk",
124 	NULL,
125 };
126 
127 static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
128 	{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
129 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
130 	{ 0 },
131 };
132 
133 static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
134 	"abe_24m_fclk",
135 	NULL,
136 };
137 
138 static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
139 	"func_24m_clk",
140 	NULL,
141 };
142 
143 static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
144 	"pad_clks_ck",
145 	NULL,
146 };
147 
148 static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
149 	"slimbus_clk",
150 	NULL,
151 };
152 
153 static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
154 	{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
155 	{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
156 	{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
157 	{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
158 	{ 0 },
159 };
160 
161 static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
162 	"syc_clk_div_ck",
163 	"sys_32k_ck",
164 	NULL,
165 };
166 
167 static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
168 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
169 	{ 0 },
170 };
171 
172 static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
173 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
174 	{ 0 },
175 };
176 
177 static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
178 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
179 	{ 0 },
180 };
181 
182 static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
183 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
184 	{ 0 },
185 };
186 
187 static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
188 	{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
189 	{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
190 	{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
191 	{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
192 	{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
193 	{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
194 	{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
195 	{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
196 	{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
197 	{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
198 	{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
199 	{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
200 	{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
201 	{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
202 	{ 0 },
203 };
204 
205 static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
206 	{ OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
207 	{ OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
208 	{ OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
209 	{ 0 },
210 };
211 
212 static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
213 	{ OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
214 	{ 0 },
215 };
216 
217 static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
218 	{ OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
219 	{ OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
220 	{ OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
221 	{ 0 },
222 };
223 
224 static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
225 	{ OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" },
226 	{ 0 },
227 };
228 
229 static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
230 	{ OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
231 	{ 0 },
232 };
233 
234 static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
235 	{ OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
236 	{ OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
237 	{ OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
238 	{ 0 },
239 };
240 
241 static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
242 	{ OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
243 	{ 0 },
244 };
245 
246 static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
247 	{ OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
248 	{ OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
249 	{ OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
250 	{ 0 },
251 };
252 
253 static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
254 	{ OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
255 	{ OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
256 	{ OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
257 	{ 0 },
258 };
259 
260 static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
261 	{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
262 	{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
263 	{ 0 },
264 };
265 
266 static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
267 	"func_96m_fclk",
268 	NULL,
269 };
270 
271 static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
272 	{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
273 	{ 0 },
274 };
275 
276 static const char * const omap4_fdif_fck_parents[] __initconst = {
277 	"dpll_per_m4x2_ck",
278 	NULL,
279 };
280 
281 static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
282 	.max_div = 4,
283 	.flags = CLK_DIVIDER_POWER_OF_TWO,
284 };
285 
286 static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
287 	{ 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
288 	{ 0 },
289 };
290 
291 static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
292 	{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
293 	{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
294 	{ 0 },
295 };
296 
297 static const char * const omap4_dss_dss_clk_parents[] __initconst = {
298 	"dpll_per_m5x2_ck",
299 	NULL,
300 };
301 
302 static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
303 	"func_48mc_fclk",
304 	NULL,
305 };
306 
307 static const char * const omap4_dss_sys_clk_parents[] __initconst = {
308 	"syc_clk_div_ck",
309 	NULL,
310 };
311 
312 static const char * const omap4_dss_tv_clk_parents[] __initconst = {
313 	"extalt_clkin_ck",
314 	NULL,
315 };
316 
317 static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
318 	{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
319 	{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
320 	{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
321 	{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
322 	{ 0 },
323 };
324 
325 static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
326 	{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
327 	{ 0 },
328 };
329 
330 static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
331 	"dpll_core_m7x2_ck",
332 	"dpll_per_m7x2_ck",
333 	NULL,
334 };
335 
336 static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
337 	{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
338 	{ 0 },
339 };
340 
341 static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
342 	{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
343 	{ 0 },
344 };
345 
346 static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
347 	"func_64m_fclk",
348 	"func_96m_fclk",
349 	NULL,
350 };
351 
352 static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
353 	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
354 	{ 0 },
355 };
356 
357 static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
358 	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
359 	{ 0 },
360 };
361 
362 static const char * const omap4_hsi_fck_parents[] __initconst = {
363 	"dpll_per_m2x2_ck",
364 	NULL,
365 };
366 
367 static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
368 	.max_div = 4,
369 	.flags = CLK_DIVIDER_POWER_OF_TWO,
370 };
371 
372 static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
373 	{ 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
374 	{ 0 },
375 };
376 
377 static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
378 	"l3_init_cm:clk:0038:24",
379 	NULL,
380 };
381 
382 static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
383 	"l3_init_cm:clk:0038:25",
384 	NULL,
385 };
386 
387 static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
388 	"init_60m_fclk",
389 	NULL,
390 };
391 
392 static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
393 	"dpll_usb_m2_ck",
394 	NULL,
395 };
396 
397 static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
398 	"init_60m_fclk",
399 	"xclk60mhsp1_ck",
400 	NULL,
401 };
402 
403 static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
404 	"init_60m_fclk",
405 	"xclk60mhsp2_ck",
406 	NULL,
407 };
408 
409 static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
410 	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
411 	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
412 	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
413 	{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
414 	{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
415 	{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
416 	{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
417 	{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
418 	{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
419 	{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
420 	{ 0 },
421 };
422 
423 static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
424 	"l3_init_cm:clk:0040:24",
425 	NULL,
426 };
427 
428 static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
429 	"utmi_phy_clkout_ck",
430 	"xclk60motg_ck",
431 	NULL,
432 };
433 
434 static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
435 	{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
436 	{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
437 	{ 0 },
438 };
439 
440 static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
441 	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
442 	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
443 	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
444 	{ 0 },
445 };
446 
447 static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
448 	"func_48m_fclk",
449 	NULL,
450 };
451 
452 static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
453 	{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
454 	{ 0 },
455 };
456 
457 static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
458 	{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
459 	{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
460 	{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
461 	{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
462 	{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
463 	{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
464 	{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
465 	{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
466 	{ 0 },
467 };
468 
469 static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
470 	"sys_clkin_ck",
471 	"sys_32k_ck",
472 	NULL,
473 };
474 
475 static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
476 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
477 	{ 0 },
478 };
479 
480 static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
481 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
482 	{ 0 },
483 };
484 
485 static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
486 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
487 	{ 0 },
488 };
489 
490 static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
491 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
492 	{ 0 },
493 };
494 
495 static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
496 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
497 	{ 0 },
498 };
499 
500 static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
501 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
502 	{ 0 },
503 };
504 
505 static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
506 	"sys_32k_ck",
507 	NULL,
508 };
509 
510 static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
511 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
512 	{ 0 },
513 };
514 
515 static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
516 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
517 	{ 0 },
518 };
519 
520 static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
521 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
522 	{ 0 },
523 };
524 
525 static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
526 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
527 	{ 0 },
528 };
529 
530 static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
531 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
532 	{ 0 },
533 };
534 
535 static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
536 	"l4_per_cm:clk:00c0:26",
537 	"pad_clks_ck",
538 	NULL,
539 };
540 
541 static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
542 	"func_96m_fclk",
543 	"per_abe_nc_fclk",
544 	NULL,
545 };
546 
547 static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
548 	{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
549 	{ 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
550 	{ 0 },
551 };
552 
553 static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
554 	"func_24mc_fclk",
555 	NULL,
556 };
557 
558 static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
559 	"per_abe_24m_fclk",
560 	NULL,
561 };
562 
563 static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
564 	"pad_slimbus_core_clks_ck",
565 	NULL,
566 };
567 
568 static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
569 	{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
570 	{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
571 	{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
572 	{ 0 },
573 };
574 
575 static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
576 	{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
577 	{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
578 	{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
579 	{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
580 	{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
581 	{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
582 	{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
583 	{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
584 	{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
585 	{ OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
586 	{ OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
587 	{ OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
588 	{ OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
589 	{ OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
590 	{ OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
591 	{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
592 	{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
593 	{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
594 	{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
595 	{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
596 	{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
597 	{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
598 	{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
599 	{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
600 	{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
601 	{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
602 	{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
603 	{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
604 	{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
605 	{ OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
606 	{ OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
607 	{ 0 },
608 };
609 
610 static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
611 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
612 	{ 0 },
613 };
614 
615 static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
616 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
617 	{ 0 },
618 };
619 
620 static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
621 	{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
622 	{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
623 	{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
624 	{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
625 	{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
626 	{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
627 	{ 0 },
628 };
629 
630 static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
631 	"sys_clkin_ck",
632 	"dpll_core_m6x2_ck",
633 	"tie_low_clock_ck",
634 	NULL,
635 };
636 
637 static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
638 	"emu_sys_cm:clk:0000:22",
639 	NULL,
640 };
641 
642 static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
643 	0,
644 	1,
645 	2,
646 	0,
647 	4,
648 	-1,
649 };
650 
651 static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
652 	.dividers = omap4_trace_clk_div_div_ck_divs,
653 };
654 
655 static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
656 	"emu_sys_cm:clk:0000:20",
657 	NULL,
658 };
659 
660 static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
661 	.max_div = 64,
662 	.flags = CLK_DIVIDER_POWER_OF_TWO,
663 };
664 
665 static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
666 	{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
667 	{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
668 	{ 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
669 	{ 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
670 	{ 0 },
671 };
672 
673 static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
674 	{ OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
675 	{ 0 },
676 };
677 
678 const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
679 	{ 0x4a004320, omap4_mpuss_clkctrl_regs },
680 	{ 0x4a004420, omap4_tesla_clkctrl_regs },
681 	{ 0x4a004520, omap4_abe_clkctrl_regs },
682 	{ 0x4a008620, omap4_l4_ao_clkctrl_regs },
683 	{ 0x4a008720, omap4_l3_1_clkctrl_regs },
684 	{ 0x4a008820, omap4_l3_2_clkctrl_regs },
685 	{ 0x4a008920, omap4_ducati_clkctrl_regs },
686 	{ 0x4a008a20, omap4_l3_dma_clkctrl_regs },
687 	{ 0x4a008b20, omap4_l3_emif_clkctrl_regs },
688 	{ 0x4a008c20, omap4_d2d_clkctrl_regs },
689 	{ 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
690 	{ 0x4a008e20, omap4_l3_instr_clkctrl_regs },
691 	{ 0x4a008f20, omap4_ivahd_clkctrl_regs },
692 	{ 0x4a009020, omap4_iss_clkctrl_regs },
693 	{ 0x4a009120, omap4_l3_dss_clkctrl_regs },
694 	{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
695 	{ 0x4a009320, omap4_l3_init_clkctrl_regs },
696 	{ 0x4a009420, omap4_l4_per_clkctrl_regs },
697 	{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
698 	{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
699 	{ 0 },
700 };
701 
702 static struct ti_dt_clk omap44xx_clks[] = {
703 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
704 	/*
705 	 * XXX: All the clock aliases below are only needed for legacy
706 	 * hwmod support. Once hwmod is removed, these can be removed
707 	 * also.
708 	 */
709 	DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
710 	DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
711 	DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
712 	DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
713 	DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
714 	DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
715 	DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
716 	DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
717 	DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
718 	DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
719 	DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
720 	DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
721 	DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
722 	DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
723 	DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
724 	DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
725 	DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
726 	DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
727 	DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
728 	DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
729 	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
730 	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
731 	DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
732 	DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
733 	DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
734 	DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
735 	DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
736 	DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
737 	DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
738 	DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
739 	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
740 	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
741 	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
742 	DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
743 	DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
744 	DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
745 	DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
746 	DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
747 	DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
748 	DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
749 	DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
750 	DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
751 	DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
752 	DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
753 	DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
754 	DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
755 	DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
756 	DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
757 	DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
758 	DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
759 	DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
760 	DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
761 	DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
762 	DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
763 	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
764 	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
765 	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
766 	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
767 	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
768 	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
769 	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
770 	DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
771 	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
772 	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
773 	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
774 	DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
775 	DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
776 	{ .node_name = NULL },
777 };
778 
779 int __init omap4xxx_dt_clk_init(void)
780 {
781 	int rc;
782 	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
783 
784 	ti_dt_clocks_register(omap44xx_clks);
785 
786 	omap2_clk_disable_autoidle_all();
787 
788 	ti_clk_add_aliases();
789 
790 	/*
791 	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
792 	 * domain can transition to retention state when not in use.
793 	 */
794 	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
795 	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
796 	if (rc)
797 		pr_err("%s: failed to configure USB DPLL!\n", __func__);
798 
799 	/*
800 	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
801 	 * state when turning the ABE clock domain. Workaround this by
802 	 * locking the ABE DPLL on boot.
803 	 * Lock the ABE DPLL in any case to avoid issues with audio.
804 	 */
805 	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
806 	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
807 	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
808 	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
809 	if (!rc)
810 		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
811 	if (rc)
812 		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
813 
814 	return 0;
815 }
816