1ffab2399STero Kristo /* 2ffab2399STero Kristo * AM43XX Clock init 3ffab2399STero Kristo * 4ffab2399STero Kristo * Copyright (C) 2013 Texas Instruments, Inc 5ffab2399STero Kristo * Tero Kristo (t-kristo@ti.com) 6ffab2399STero Kristo * 7ffab2399STero Kristo * This program is free software; you can redistribute it and/or 8ffab2399STero Kristo * modify it under the terms of the GNU General Public License as 9ffab2399STero Kristo * published by the Free Software Foundation version 2. 10ffab2399STero Kristo * 11ffab2399STero Kristo * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12ffab2399STero Kristo * kind, whether express or implied; without even the implied warranty 13ffab2399STero Kristo * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14ffab2399STero Kristo * GNU General Public License for more details. 15ffab2399STero Kristo */ 16ffab2399STero Kristo 17ffab2399STero Kristo #include <linux/kernel.h> 18ffab2399STero Kristo #include <linux/list.h> 191b29e601SStephen Boyd #include <linux/clk.h> 20ffab2399STero Kristo #include <linux/clk-provider.h> 21ffab2399STero Kristo #include <linux/clk/ti.h> 22a3da10b7STero Kristo #include <dt-bindings/clock/am4.h> 23ffab2399STero Kristo 24a3314e9cSTero Kristo #include "clock.h" 25a3314e9cSTero Kristo 2676a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = { 2776a1049bSTero Kristo { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" }, 2876a1049bSTero Kristo { 0 }, 2976a1049bSTero Kristo }; 3076a1049bSTero Kristo 3176a1049bSTero Kristo static const char * const am4_synctimer_32kclk_parents[] __initconst = { 3276a1049bSTero Kristo "mux_synctimer32k_ck", 3376a1049bSTero Kristo NULL, 3476a1049bSTero Kristo }; 3576a1049bSTero Kristo 3676a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = { 3776a1049bSTero Kristo { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL }, 3876a1049bSTero Kristo { 0 }, 3976a1049bSTero Kristo }; 4076a1049bSTero Kristo 4176a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = { 4276a1049bSTero Kristo { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" }, 4376a1049bSTero Kristo { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" }, 4476a1049bSTero Kristo { 0 }, 4576a1049bSTero Kristo }; 4676a1049bSTero Kristo 4776a1049bSTero Kristo static const char * const am4_gpio0_dbclk_parents[] __initconst = { 4876a1049bSTero Kristo "gpio0_dbclk_mux_ck", 4976a1049bSTero Kristo NULL, 5076a1049bSTero Kristo }; 5176a1049bSTero Kristo 5276a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = { 5376a1049bSTero Kristo { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL }, 5476a1049bSTero Kristo { 0 }, 5576a1049bSTero Kristo }; 5676a1049bSTero Kristo 5776a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = { 5876a1049bSTero Kristo { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, 5976a1049bSTero Kristo { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, 6076a1049bSTero Kristo { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" }, 6176a1049bSTero Kristo { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 6276a1049bSTero Kristo { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 6376a1049bSTero Kristo { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" }, 6476a1049bSTero Kristo { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" }, 6576a1049bSTero Kristo { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, 6676a1049bSTero Kristo { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" }, 6776a1049bSTero Kristo { 0 }, 6876a1049bSTero Kristo }; 6976a1049bSTero Kristo 7076a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = { 7176a1049bSTero Kristo { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 7276a1049bSTero Kristo { 0 }, 7376a1049bSTero Kristo }; 7476a1049bSTero Kristo 7576a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { 76ece3e465STero Kristo { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" }, 7776a1049bSTero Kristo { 0 }, 7876a1049bSTero Kristo }; 7976a1049bSTero Kristo 8076a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = { 815f3d9b07STony Lindgren { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" }, 8276a1049bSTero Kristo { 0 }, 8376a1049bSTero Kristo }; 8476a1049bSTero Kristo 8576a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = { 8676a1049bSTero Kristo { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 8776a1049bSTero Kristo { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" }, 8876a1049bSTero Kristo { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 8976a1049bSTero Kristo { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9076a1049bSTero Kristo { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9176a1049bSTero Kristo { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9276a1049bSTero Kristo { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9376a1049bSTero Kristo { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9476a1049bSTero Kristo { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9576a1049bSTero Kristo { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 9676a1049bSTero Kristo { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" }, 9776a1049bSTero Kristo { 0 }, 9876a1049bSTero Kristo }; 9976a1049bSTero Kristo 10076a1049bSTero Kristo static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = { 10176a1049bSTero Kristo "dpll_per_clkdcoldo", 10276a1049bSTero Kristo NULL, 10376a1049bSTero Kristo }; 10476a1049bSTero Kristo 10576a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = { 10676a1049bSTero Kristo { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL }, 10776a1049bSTero Kristo { 0 }, 10876a1049bSTero Kristo }; 10976a1049bSTero Kristo 11076a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = { 11176a1049bSTero Kristo { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL }, 11276a1049bSTero Kristo { 0 }, 11376a1049bSTero Kristo }; 11476a1049bSTero Kristo 11576a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = { 11676a1049bSTero Kristo { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 11776a1049bSTero Kristo { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 11876a1049bSTero Kristo { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" }, 11976a1049bSTero Kristo { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" }, 12076a1049bSTero Kristo { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" }, 12176a1049bSTero Kristo { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 12276a1049bSTero Kristo { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" }, 12376a1049bSTero Kristo { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" }, 12476a1049bSTero Kristo { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" }, 12576a1049bSTero Kristo { 0 }, 12676a1049bSTero Kristo }; 12776a1049bSTero Kristo 12876a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = { 129caf00b53STero Kristo { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" }, 13076a1049bSTero Kristo { 0 }, 13176a1049bSTero Kristo }; 13276a1049bSTero Kristo 13376a1049bSTero Kristo static const char * const am4_gpio1_dbclk_parents[] __initconst = { 13476a1049bSTero Kristo "clkdiv32k_ick", 13576a1049bSTero Kristo NULL, 13676a1049bSTero Kristo }; 13776a1049bSTero Kristo 13876a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = { 13976a1049bSTero Kristo { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, 14076a1049bSTero Kristo { 0 }, 14176a1049bSTero Kristo }; 14276a1049bSTero Kristo 14376a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = { 14476a1049bSTero Kristo { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, 14576a1049bSTero Kristo { 0 }, 14676a1049bSTero Kristo }; 14776a1049bSTero Kristo 14876a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = { 14976a1049bSTero Kristo { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, 15076a1049bSTero Kristo { 0 }, 15176a1049bSTero Kristo }; 15276a1049bSTero Kristo 15376a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = { 15476a1049bSTero Kristo { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, 15576a1049bSTero Kristo { 0 }, 15676a1049bSTero Kristo }; 15776a1049bSTero Kristo 15876a1049bSTero Kristo static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = { 15976a1049bSTero Kristo { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, 16076a1049bSTero Kristo { 0 }, 16176a1049bSTero Kristo }; 16276a1049bSTero Kristo 16376a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = { 16476a1049bSTero Kristo { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 16576a1049bSTero Kristo { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 16676a1049bSTero Kristo { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 16776a1049bSTero Kristo { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 16876a1049bSTero Kristo { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 16976a1049bSTero Kristo { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 17076a1049bSTero Kristo { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 17176a1049bSTero Kristo { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 17276a1049bSTero Kristo { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 17376a1049bSTero Kristo { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 17476a1049bSTero Kristo { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 17576a1049bSTero Kristo { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 17676a1049bSTero Kristo { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 17776a1049bSTero Kristo { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 17876a1049bSTero Kristo { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 17976a1049bSTero Kristo { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" }, 18076a1049bSTero Kristo { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 18176a1049bSTero Kristo { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 18276a1049bSTero Kristo { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 18376a1049bSTero Kristo { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 18476a1049bSTero Kristo { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 18576a1049bSTero Kristo { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 18676a1049bSTero Kristo { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 18776a1049bSTero Kristo { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 18876a1049bSTero Kristo { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 18976a1049bSTero Kristo { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 19076a1049bSTero Kristo { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 19176a1049bSTero Kristo { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 19276a1049bSTero Kristo { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 19376a1049bSTero Kristo { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 19476a1049bSTero Kristo { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 19576a1049bSTero Kristo { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 19676a1049bSTero Kristo { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 19776a1049bSTero Kristo { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 19876a1049bSTero Kristo { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" }, 19976a1049bSTero Kristo { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" }, 20076a1049bSTero Kristo { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" }, 20176a1049bSTero Kristo { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" }, 20276a1049bSTero Kristo { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 20376a1049bSTero Kristo { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 20476a1049bSTero Kristo { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 20576a1049bSTero Kristo { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 20676a1049bSTero Kristo { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 20776a1049bSTero Kristo { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 20876a1049bSTero Kristo { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 20976a1049bSTero Kristo { 0 }, 21076a1049bSTero Kristo }; 21176a1049bSTero Kristo 21276a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = { 21376a1049bSTero Kristo { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" }, 21476a1049bSTero Kristo { 0 }, 21576a1049bSTero Kristo }; 21676a1049bSTero Kristo 21776a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = { 21876a1049bSTero Kristo { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" }, 21976a1049bSTero Kristo { 0 }, 22076a1049bSTero Kristo }; 22176a1049bSTero Kristo 22276a1049bSTero Kristo static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = { 22376a1049bSTero Kristo { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" }, 22476a1049bSTero Kristo { 0 }, 22576a1049bSTero Kristo }; 22676a1049bSTero Kristo 22776a1049bSTero Kristo const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = { 22876a1049bSTero Kristo { 0x44df2920, am4_l3s_tsc_clkctrl_regs }, 22976a1049bSTero Kristo { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs }, 23076a1049bSTero Kristo { 0x44df2a20, am4_l4_wkup_clkctrl_regs }, 23176a1049bSTero Kristo { 0x44df8320, am4_mpu_clkctrl_regs }, 23276a1049bSTero Kristo { 0x44df8420, am4_gfx_l3_clkctrl_regs }, 23376a1049bSTero Kristo { 0x44df8520, am4_l4_rtc_clkctrl_regs }, 23476a1049bSTero Kristo { 0x44df8820, am4_l3_clkctrl_regs }, 23576a1049bSTero Kristo { 0x44df8868, am4_l3s_clkctrl_regs }, 23676a1049bSTero Kristo { 0x44df8b20, am4_pruss_ocp_clkctrl_regs }, 23776a1049bSTero Kristo { 0x44df8c20, am4_l4ls_clkctrl_regs }, 23876a1049bSTero Kristo { 0x44df8f20, am4_emif_clkctrl_regs }, 23976a1049bSTero Kristo { 0x44df9220, am4_dss_clkctrl_regs }, 24076a1049bSTero Kristo { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs }, 24176a1049bSTero Kristo { 0 }, 24276a1049bSTero Kristo }; 24376a1049bSTero Kristo 24476a1049bSTero Kristo const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = { 24576a1049bSTero Kristo { 0x44df2920, am4_l3s_tsc_clkctrl_regs }, 24676a1049bSTero Kristo { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs }, 24776a1049bSTero Kristo { 0x44df2a20, am4_l4_wkup_clkctrl_regs }, 24876a1049bSTero Kristo { 0x44df8320, am4_mpu_clkctrl_regs }, 24976a1049bSTero Kristo { 0x44df8420, am4_gfx_l3_clkctrl_regs }, 25076a1049bSTero Kristo { 0x44df8820, am4_l3_clkctrl_regs }, 25176a1049bSTero Kristo { 0x44df8868, am4_l3s_clkctrl_regs }, 25276a1049bSTero Kristo { 0x44df8b20, am4_pruss_ocp_clkctrl_regs }, 25376a1049bSTero Kristo { 0x44df8c20, am4_l4ls_clkctrl_regs }, 25476a1049bSTero Kristo { 0x44df8f20, am4_emif_clkctrl_regs }, 25576a1049bSTero Kristo { 0x44df9220, am4_dss_clkctrl_regs }, 25676a1049bSTero Kristo { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs }, 25776a1049bSTero Kristo { 0 }, 25876a1049bSTero Kristo }; 25976a1049bSTero Kristo 26076a1049bSTero Kristo static struct ti_dt_clk am43xx_clks[] = { 26176a1049bSTero Kristo DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 26276a1049bSTero Kristo DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 26376a1049bSTero Kristo DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"), 26476a1049bSTero Kristo DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"), 26576a1049bSTero Kristo DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"), 26676a1049bSTero Kristo DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"), 26776a1049bSTero Kristo DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"), 26876a1049bSTero Kristo DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"), 26976a1049bSTero Kristo DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"), 27076a1049bSTero Kristo DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"), 27176a1049bSTero Kristo DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"), 27276a1049bSTero Kristo { .node_name = NULL }, 27376a1049bSTero Kristo }; 27476a1049bSTero Kristo 275*d36edb04STony Lindgren static const char *enable_init_clks[] = { 276*d36edb04STony Lindgren /* AM4_L3_L3_MAIN_CLKCTRL, needed during suspend */ 277*d36edb04STony Lindgren "l3-clkctrl:0000:0", 278*d36edb04STony Lindgren }; 279*d36edb04STony Lindgren 280ffab2399STero Kristo int __init am43xx_dt_clk_init(void) 281ffab2399STero Kristo { 282f9786f41SGeorge Cherian struct clk *clk1, *clk2; 283f9786f41SGeorge Cherian 28476a1049bSTero Kristo if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) 285131ee08fSTero Kristo ti_dt_clocks_register(am43xx_compat_clks); 28676a1049bSTero Kristo else 28776a1049bSTero Kristo ti_dt_clocks_register(am43xx_clks); 288ffab2399STero Kristo 289ffab2399STero Kristo omap2_clk_disable_autoidle_all(); 290ffab2399STero Kristo 291*d36edb04STony Lindgren omap2_clk_enable_init_clocks(enable_init_clks, 292*d36edb04STony Lindgren ARRAY_SIZE(enable_init_clks)); 293*d36edb04STony Lindgren 29478aac800STero Kristo ti_clk_add_aliases(); 29578aac800STero Kristo 296f9786f41SGeorge Cherian /* 297f9786f41SGeorge Cherian * cpsw_cpts_rft_clk has got the choice of 3 clocksources 298f9786f41SGeorge Cherian * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck. 299f9786f41SGeorge Cherian * By default dpll_core_m4_ck is selected, witn this as clock 300f9786f41SGeorge Cherian * source the CPTS doesnot work properly. It gives clockcheck errors 301f9786f41SGeorge Cherian * while running PTP. 302f9786f41SGeorge Cherian * clockcheck: clock jumped backward or running slower than expected! 303f9786f41SGeorge Cherian * By selecting dpll_core_m5_ck as the clocksource fixes this issue. 304f9786f41SGeorge Cherian * In AM335x dpll_core_m5_ck is the default clocksource. 305f9786f41SGeorge Cherian */ 306f9786f41SGeorge Cherian clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); 307f9786f41SGeorge Cherian clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); 308f9786f41SGeorge Cherian clk_set_parent(clk1, clk2); 309f9786f41SGeorge Cherian 310ffab2399STero Kristo return 0; 311ffab2399STero Kristo } 312