1 /* 2 * OMAP3 Clock init 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 #include <linux/clk.h> 20 #include <linux/clk-provider.h> 21 #include <linux/clk/ti.h> 22 23 #include "clock.h" 24 25 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 26 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 27 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 28 29 #define OMAP34XX_CM_IDLEST_VAL 1 30 31 /* 32 * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported 33 * in the same register at a bit offset of 0x8. The EN_ACK for ICK is 34 * at an offset of 4 from ICK enable bit. 35 */ 36 #define AM35XX_IPSS_ICK_MASK 0xF 37 #define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 38 #define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 39 #define AM35XX_IPSS_CLK_IDLEST_VAL 0 40 41 #define AM35XX_ST_IPSS_SHIFT 5 42 43 /** 44 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI 45 * @clk: struct clk * being enabled 46 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into 47 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into 48 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator 49 * 50 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift 51 * from the CM_{I,F}CLKEN bit. Pass back the correct info via 52 * @idlest_reg and @idlest_bit. No return value. 53 */ 54 static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, 55 struct clk_omap_reg *idlest_reg, 56 u8 *idlest_bit, 57 u8 *idlest_val) 58 { 59 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); 60 idlest_reg->offset &= ~0xf0; 61 idlest_reg->offset |= 0x20; 62 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; 63 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 64 } 65 66 const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { 67 .allow_idle = omap2_clkt_iclk_allow_idle, 68 .deny_idle = omap2_clkt_iclk_deny_idle, 69 .find_idlest = omap3430es2_clk_ssi_find_idlest, 70 .find_companion = omap2_clk_dflt_find_companion, 71 }; 72 73 /** 74 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST 75 * @clk: struct clk * being enabled 76 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into 77 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into 78 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator 79 * 80 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and 81 * target IDLEST bits. For our purposes, we are concerned with the 82 * target IDLEST bits, which exist at a different bit position than 83 * the *CLKEN bit position for these modules (DSS and USBHOST) (The 84 * default find_idlest code assumes that they are at the same 85 * position.) No return value. 86 */ 87 static void 88 omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, 89 struct clk_omap_reg *idlest_reg, 90 u8 *idlest_bit, u8 *idlest_val) 91 { 92 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); 93 94 idlest_reg->offset &= ~0xf0; 95 idlest_reg->offset |= 0x20; 96 /* USBHOST_IDLE has same shift */ 97 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; 98 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 99 } 100 101 const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { 102 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, 103 .find_companion = omap2_clk_dflt_find_companion, 104 }; 105 106 const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { 107 .allow_idle = omap2_clkt_iclk_allow_idle, 108 .deny_idle = omap2_clkt_iclk_deny_idle, 109 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, 110 .find_companion = omap2_clk_dflt_find_companion, 111 }; 112 113 /** 114 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB 115 * @clk: struct clk * being enabled 116 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into 117 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into 118 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator 119 * 120 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different 121 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via 122 * @idlest_reg and @idlest_bit. No return value. 123 */ 124 static void 125 omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, 126 struct clk_omap_reg *idlest_reg, 127 u8 *idlest_bit, 128 u8 *idlest_val) 129 { 130 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); 131 idlest_reg->offset &= ~0xf0; 132 idlest_reg->offset |= 0x20; 133 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; 134 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 135 } 136 137 const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { 138 .allow_idle = omap2_clkt_iclk_allow_idle, 139 .deny_idle = omap2_clkt_iclk_deny_idle, 140 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, 141 .find_companion = omap2_clk_dflt_find_companion, 142 }; 143 144 /** 145 * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS 146 * @clk: struct clk * being enabled 147 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into 148 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into 149 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator 150 * 151 * The interface clocks on AM35xx IPSS reflects the clock idle status 152 * in the enable register itsel at a bit offset of 4 from the enable 153 * bit. A value of 1 indicates that clock is enabled. 154 */ 155 static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, 156 struct clk_omap_reg *idlest_reg, 157 u8 *idlest_bit, 158 u8 *idlest_val) 159 { 160 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); 161 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; 162 *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; 163 } 164 165 /** 166 * am35xx_clk_find_companion - find companion clock to @clk 167 * @clk: struct clk * to find the companion clock of 168 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 169 * @other_bit: u8 ** to return the companion clock bit shift in 170 * 171 * Some clocks don't have companion clocks. For example, modules with 172 * only an interface clock (such as HECC) don't have a companion 173 * clock. Right now, this code relies on the hardware exporting a bit 174 * in the correct companion register that indicates that the 175 * nonexistent 'companion clock' is active. Future patches will 176 * associate this type of code with per-module data structures to 177 * avoid this issue, and remove the casts. No return value. 178 */ 179 static void am35xx_clk_find_companion(struct clk_hw_omap *clk, 180 struct clk_omap_reg *other_reg, 181 u8 *other_bit) 182 { 183 memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg)); 184 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) 185 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; 186 else 187 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; 188 } 189 190 const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { 191 .find_idlest = am35xx_clk_find_idlest, 192 .find_companion = am35xx_clk_find_companion, 193 }; 194 195 /** 196 * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS 197 * @clk: struct clk * being enabled 198 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into 199 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into 200 * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator 201 * 202 * The IPSS target CM_IDLEST bit is at a different shift from the 203 * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg 204 * and @idlest_bit. No return value. 205 */ 206 static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, 207 struct clk_omap_reg *idlest_reg, 208 u8 *idlest_bit, 209 u8 *idlest_val) 210 { 211 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); 212 213 idlest_reg->offset &= ~0xf0; 214 idlest_reg->offset |= 0x20; 215 *idlest_bit = AM35XX_ST_IPSS_SHIFT; 216 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 217 } 218 219 const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { 220 .allow_idle = omap2_clkt_iclk_allow_idle, 221 .deny_idle = omap2_clkt_iclk_deny_idle, 222 .find_idlest = am35xx_clk_ipss_find_idlest, 223 .find_companion = omap2_clk_dflt_find_companion, 224 }; 225 226 static struct ti_dt_clk omap3xxx_clks[] = { 227 DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), 228 DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), 229 DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), 230 DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), 231 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 232 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 233 DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"), 234 DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"), 235 DT_CLK("twl", "fck", "osc_sys_ck"), 236 DT_CLK(NULL, "sys_ck", "sys_ck"), 237 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), 238 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), 239 DT_CLK(NULL, "sys_altclk", "sys_altclk"), 240 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), 241 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), 242 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), 243 DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"), 244 DT_CLK(NULL, "dpll3_ck", "dpll3_ck"), 245 DT_CLK(NULL, "core_ck", "core_ck"), 246 DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"), 247 DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"), 248 DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"), 249 DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"), 250 DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"), 251 DT_CLK(NULL, "dpll4_ck", "dpll4_ck"), 252 DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"), 253 DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"), 254 DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"), 255 DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"), 256 DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"), 257 DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"), 258 DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"), 259 DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"), 260 DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"), 261 DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"), 262 DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"), 263 DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"), 264 DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"), 265 DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"), 266 DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"), 267 DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"), 268 DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"), 269 DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"), 270 DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), 271 DT_CLK(NULL, "corex2_fck", "corex2_fck"), 272 DT_CLK(NULL, "dpll1_fck", "dpll1_fck"), 273 DT_CLK(NULL, "mpu_ck", "mpu_ck"), 274 DT_CLK(NULL, "arm_fck", "arm_fck"), 275 DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"), 276 DT_CLK(NULL, "l3_ick", "l3_ick"), 277 DT_CLK(NULL, "l4_ick", "l4_ick"), 278 DT_CLK(NULL, "rm_ick", "rm_ick"), 279 DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), 280 DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), 281 DT_CLK(NULL, "core_96m_fck", "core_96m_fck"), 282 DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), 283 DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), 284 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), 285 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), 286 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), 287 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), 288 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), 289 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), 290 DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), 291 DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), 292 DT_CLK(NULL, "uart2_fck", "uart2_fck"), 293 DT_CLK(NULL, "uart1_fck", "uart1_fck"), 294 DT_CLK(NULL, "core_12m_fck", "core_12m_fck"), 295 DT_CLK("omap_hdq.0", "fck", "hdq_fck"), 296 DT_CLK(NULL, "hdq_fck", "hdq_fck"), 297 DT_CLK(NULL, "core_l3_ick", "core_l3_ick"), 298 DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), 299 DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), 300 DT_CLK(NULL, "core_l4_ick", "core_l4_ick"), 301 DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), 302 DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), 303 DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), 304 DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), 305 DT_CLK("omap_hdq.0", "ick", "hdq_ick"), 306 DT_CLK(NULL, "hdq_ick", "hdq_ick"), 307 DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"), 308 DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), 309 DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), 310 DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), 311 DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"), 312 DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), 313 DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), 314 DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), 315 DT_CLK("omap_i2c.3", "ick", "i2c3_ick"), 316 DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), 317 DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), 318 DT_CLK(NULL, "i2c3_ick", "i2c3_ick"), 319 DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), 320 DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), 321 DT_CLK(NULL, "uart2_ick", "uart2_ick"), 322 DT_CLK(NULL, "uart1_ick", "uart1_ick"), 323 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), 324 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), 325 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), 326 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), 327 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), 328 DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"), 329 DT_CLK(NULL, "init_60m_fclk", "dummy_ck"), 330 DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), 331 DT_CLK(NULL, "aes2_ick", "aes2_ick"), 332 DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"), 333 DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"), 334 DT_CLK(NULL, "sha12_ick", "sha12_ick"), 335 DT_CLK(NULL, "wdt2_fck", "wdt2_fck"), 336 DT_CLK("omap_wdt", "ick", "wdt2_ick"), 337 DT_CLK(NULL, "wdt2_ick", "wdt2_ick"), 338 DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), 339 DT_CLK(NULL, "gpio1_ick", "gpio1_ick"), 340 DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"), 341 DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), 342 DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), 343 DT_CLK(NULL, "per_96m_fck", "per_96m_fck"), 344 DT_CLK(NULL, "per_48m_fck", "per_48m_fck"), 345 DT_CLK(NULL, "uart3_fck", "uart3_fck"), 346 DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), 347 DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), 348 DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), 349 DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), 350 DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), 351 DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), 352 DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), 353 DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), 354 DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"), 355 DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"), 356 DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"), 357 DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"), 358 DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"), 359 DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"), 360 DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), 361 DT_CLK(NULL, "per_l4_ick", "per_l4_ick"), 362 DT_CLK(NULL, "gpio6_ick", "gpio6_ick"), 363 DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), 364 DT_CLK(NULL, "gpio4_ick", "gpio4_ick"), 365 DT_CLK(NULL, "gpio3_ick", "gpio3_ick"), 366 DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), 367 DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), 368 DT_CLK(NULL, "uart3_ick", "uart3_ick"), 369 DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), 370 DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), 371 DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), 372 DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), 373 DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), 374 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), 375 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), 376 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), 377 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), 378 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), 379 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"), 380 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), 381 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"), 382 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), 383 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), 384 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), 385 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), 386 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), 387 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), 388 DT_CLK("etb", "emu_src_ck", "emu_src_ck"), 389 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), 390 DT_CLK(NULL, "pclk_fck", "pclk_fck"), 391 DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"), 392 DT_CLK(NULL, "atclk_fck", "atclk_fck"), 393 DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"), 394 DT_CLK(NULL, "traceclk_fck", "traceclk_fck"), 395 DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"), 396 DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), 397 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), 398 DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), 399 DT_CLK(NULL, "timer_sys_ck", "sys_ck"), 400 DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"), 401 { .node_name = NULL }, 402 }; 403 404 static struct ti_dt_clk omap34xx_omap36xx_clks[] = { 405 DT_CLK(NULL, "aes1_ick", "aes1_ick"), 406 DT_CLK("omap_rng", "ick", "rng_ick"), 407 DT_CLK("omap3-rom-rng", "ick", "rng_ick"), 408 DT_CLK(NULL, "sha11_ick", "sha11_ick"), 409 DT_CLK(NULL, "des1_ick", "des1_ick"), 410 DT_CLK(NULL, "cam_mclk", "cam_mclk"), 411 DT_CLK(NULL, "cam_ick", "cam_ick"), 412 DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"), 413 DT_CLK(NULL, "security_l3_ick", "security_l3_ick"), 414 DT_CLK(NULL, "pka_ick", "pka_ick"), 415 DT_CLK(NULL, "icr_ick", "icr_ick"), 416 DT_CLK("omap-aes", "ick", "aes2_ick"), 417 DT_CLK("omap-sham", "ick", "sha12_ick"), 418 DT_CLK(NULL, "des2_ick", "des2_ick"), 419 DT_CLK(NULL, "mspro_ick", "mspro_ick"), 420 DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), 421 DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), 422 DT_CLK(NULL, "sr1_fck", "sr1_fck"), 423 DT_CLK(NULL, "sr2_fck", "sr2_fck"), 424 DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"), 425 DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"), 426 DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"), 427 DT_CLK(NULL, "dpll2_fck", "dpll2_fck"), 428 DT_CLK(NULL, "iva2_ck", "iva2_ck"), 429 DT_CLK(NULL, "modem_fck", "modem_fck"), 430 DT_CLK(NULL, "sad2d_ick", "sad2d_ick"), 431 DT_CLK(NULL, "mad2d_ick", "mad2d_ick"), 432 DT_CLK(NULL, "mspro_fck", "mspro_fck"), 433 DT_CLK(NULL, "dpll2_ck", "dpll2_ck"), 434 DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"), 435 { .node_name = NULL }, 436 }; 437 438 static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { 439 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), 440 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), 441 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"), 442 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), 443 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), 444 DT_CLK(NULL, "usim_fck", "usim_fck"), 445 DT_CLK(NULL, "usim_ick", "usim_ick"), 446 { .node_name = NULL }, 447 }; 448 449 static struct ti_dt_clk omap3430es1_clks[] = { 450 DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"), 451 DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"), 452 DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"), 453 DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"), 454 DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"), 455 DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"), 456 DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"), 457 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), 458 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), 459 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"), 460 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), 461 DT_CLK(NULL, "fac_ick", "fac_ick"), 462 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), 463 DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), 464 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), 465 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"), 466 DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), 467 { .node_name = NULL }, 468 }; 469 470 static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { 471 DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"), 472 DT_CLK(NULL, "dpll5_ck", "dpll5_ck"), 473 DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"), 474 DT_CLK(NULL, "sgx_fck", "sgx_fck"), 475 DT_CLK(NULL, "sgx_ick", "sgx_ick"), 476 DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"), 477 DT_CLK(NULL, "ts_fck", "ts_fck"), 478 DT_CLK(NULL, "usbtll_fck", "usbtll_fck"), 479 DT_CLK(NULL, "usbtll_ick", "usbtll_ick"), 480 DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"), 481 DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"), 482 DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"), 483 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), 484 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"), 485 DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), 486 DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"), 487 DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"), 488 DT_CLK(NULL, "usbhost_ick", "usbhost_ick"), 489 { .node_name = NULL }, 490 }; 491 492 static struct ti_dt_clk am35xx_clks[] = { 493 DT_CLK(NULL, "ipss_ick", "ipss_ick"), 494 DT_CLK(NULL, "rmii_ck", "rmii_ck"), 495 DT_CLK(NULL, "pclk_ck", "pclk_ck"), 496 DT_CLK(NULL, "emac_ick", "emac_ick"), 497 DT_CLK(NULL, "emac_fck", "emac_fck"), 498 DT_CLK("davinci_emac.0", NULL, "emac_ick"), 499 DT_CLK("davinci_mdio.0", NULL, "emac_fck"), 500 DT_CLK("vpfe-capture", "master", "vpfe_ick"), 501 DT_CLK("vpfe-capture", "slave", "vpfe_fck"), 502 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), 503 DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), 504 DT_CLK(NULL, "hecc_ck", "hecc_ck"), 505 DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), 506 DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), 507 { .node_name = NULL }, 508 }; 509 510 static struct ti_dt_clk omap36xx_clks[] = { 511 DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"), 512 DT_CLK(NULL, "uart4_fck", "uart4_fck"), 513 DT_CLK(NULL, "uart4_ick", "uart4_ick"), 514 { .node_name = NULL }, 515 }; 516 517 static const char *enable_init_clks[] = { 518 "sdrc_ick", 519 "gpmc_fck", 520 "omapctrl_ick", 521 }; 522 523 enum { 524 OMAP3_SOC_AM35XX, 525 OMAP3_SOC_OMAP3430_ES1, 526 OMAP3_SOC_OMAP3430_ES2_PLUS, 527 OMAP3_SOC_OMAP3630, 528 }; 529 530 /** 531 * omap3_clk_lock_dpll5 - locks DPLL5 532 * 533 * Locks DPLL5 to a pre-defined frequency. This is required for proper 534 * operation of USB. 535 */ 536 void __init omap3_clk_lock_dpll5(void) 537 { 538 struct clk *dpll5_clk; 539 struct clk *dpll5_m2_clk; 540 541 /* 542 * Errata sprz319f advisory 2.1 documents a USB host clock drift issue 543 * that can be worked around using specially crafted dpll5 settings 544 * with a dpll5_m2 divider set to 8. Set the dpll5 rate to 8x the USB 545 * host clock rate, its .set_rate handler() will detect that frequency 546 * and use the errata settings. 547 */ 548 dpll5_clk = clk_get(NULL, "dpll5_ck"); 549 clk_set_rate(dpll5_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST * 8); 550 clk_prepare_enable(dpll5_clk); 551 552 /* Program dpll5_m2_clk divider */ 553 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); 554 clk_prepare_enable(dpll5_m2_clk); 555 clk_set_rate(dpll5_m2_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST); 556 557 clk_disable_unprepare(dpll5_m2_clk); 558 clk_disable_unprepare(dpll5_clk); 559 } 560 561 static int __init omap3xxx_dt_clk_init(int soc_type) 562 { 563 if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 || 564 soc_type == OMAP3_SOC_OMAP3430_ES1 || 565 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) 566 ti_dt_clocks_register(omap3xxx_clks); 567 568 if (soc_type == OMAP3_SOC_AM35XX) 569 ti_dt_clocks_register(am35xx_clks); 570 571 if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX || 572 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) 573 ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks); 574 575 if (soc_type == OMAP3_SOC_OMAP3430_ES1) 576 ti_dt_clocks_register(omap3430es1_clks); 577 578 if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || 579 soc_type == OMAP3_SOC_OMAP3630) 580 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); 581 582 if (soc_type == OMAP3_SOC_OMAP3430_ES1 || 583 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || 584 soc_type == OMAP3_SOC_OMAP3630) 585 ti_dt_clocks_register(omap34xx_omap36xx_clks); 586 587 if (soc_type == OMAP3_SOC_OMAP3630) 588 ti_dt_clocks_register(omap36xx_clks); 589 590 omap2_clk_disable_autoidle_all(); 591 592 omap2_clk_enable_init_clocks(enable_init_clks, 593 ARRAY_SIZE(enable_init_clks)); 594 595 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 596 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), 597 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, 598 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), 599 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); 600 601 if (soc_type != OMAP3_SOC_OMAP3430_ES1) 602 omap3_clk_lock_dpll5(); 603 604 return 0; 605 } 606 607 int __init omap3430_dt_clk_init(void) 608 { 609 return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS); 610 } 611 612 int __init omap3630_dt_clk_init(void) 613 { 614 return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630); 615 } 616 617 int __init am35xx_dt_clk_init(void) 618 { 619 return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX); 620 } 621