1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AM33XX Clock init 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc 6 * Tero Kristo (t-kristo@ti.com) 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/list.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/clk/ti.h> 14 #include <dt-bindings/clock/am3.h> 15 16 #include "clock.h" 17 18 static const char * const am3_gpio1_dbclk_parents[] __initconst = { 19 "clk-24mhz-clkctrl:0000:0", 20 NULL, 21 }; 22 23 static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { 24 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, 25 { 0 }, 26 }; 27 28 static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { 29 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, 30 { 0 }, 31 }; 32 33 static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = { 34 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, 35 { 0 }, 36 }; 37 38 static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = { 39 { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 40 { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 41 { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 42 { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 43 { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 44 { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 45 { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 46 { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 47 { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 48 { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 49 { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 50 { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 51 { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 52 { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 53 { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 54 { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 55 { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 56 { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 57 { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 58 { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 59 { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 60 { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 61 { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 62 { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 63 { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 64 { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 65 { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 66 { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 67 { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 68 { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 69 { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 70 { 0 }, 71 }; 72 73 static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = { 74 { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" }, 75 { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" }, 76 { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" }, 77 { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" }, 78 { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 79 { 0 }, 80 }; 81 82 static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = { 83 { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 84 { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" }, 85 { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 86 { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" }, 87 { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 88 { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 89 { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 90 { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 91 { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 92 { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 93 { 0 }, 94 }; 95 96 static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = { 97 { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" }, 98 { 0 }, 99 }; 100 101 static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = { 102 { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" }, 103 { 0 }, 104 }; 105 106 static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = { 107 { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" }, 108 { 0 }, 109 }; 110 111 static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = { 112 { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" }, 113 { 0 }, 114 }; 115 116 static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = { 117 { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" }, 118 { 0 }, 119 }; 120 121 static const char * const am3_gpio0_dbclk_parents[] __initconst = { 122 "gpio0_dbclk_mux_ck", 123 NULL, 124 }; 125 126 static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { 127 { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, 128 { 0 }, 129 }; 130 131 static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { 132 { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 133 { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 134 { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 135 { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 136 { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 137 { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" }, 138 { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" }, 139 { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, 140 { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" }, 141 { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" }, 142 { 0 }, 143 }; 144 145 static const char * const am3_dbg_sysclk_ck_parents[] __initconst = { 146 "sys_clkin_ck", 147 NULL, 148 }; 149 150 static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = { 151 "l3-aon-clkctrl:0000:19", 152 "l3-aon-clkctrl:0000:30", 153 NULL, 154 }; 155 156 static const char * const am3_trace_clk_div_ck_parents[] __initconst = { 157 "l3-aon-clkctrl:0000:20", 158 NULL, 159 }; 160 161 static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = { 162 .max_div = 64, 163 .flags = CLK_DIVIDER_POWER_OF_TWO, 164 }; 165 166 static const char * const am3_stm_clk_div_ck_parents[] __initconst = { 167 "l3-aon-clkctrl:0000:22", 168 NULL, 169 }; 170 171 static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = { 172 .max_div = 64, 173 .flags = CLK_DIVIDER_POWER_OF_TWO, 174 }; 175 176 static const char * const am3_dbg_clka_ck_parents[] __initconst = { 177 "dpll_core_m4_ck", 178 NULL, 179 }; 180 181 static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = { 182 { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL }, 183 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, 184 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, 185 { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data }, 186 { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data }, 187 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL }, 188 { 0 }, 189 }; 190 191 static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = { 192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" }, 193 { 0 }, 194 }; 195 196 static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = { 197 { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" }, 198 { 0 }, 199 }; 200 201 static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = { 202 { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 203 { 0 }, 204 }; 205 206 static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = { 207 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" }, 208 { 0 }, 209 }; 210 211 static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = { 212 { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" }, 213 { 0 }, 214 }; 215 216 static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = { 217 { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, 218 { 0 }, 219 }; 220 221 const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = { 222 { 0x44e00038, am3_l4ls_clkctrl_regs }, 223 { 0x44e0001c, am3_l3s_clkctrl_regs }, 224 { 0x44e00024, am3_l3_clkctrl_regs }, 225 { 0x44e00120, am3_l4hs_clkctrl_regs }, 226 { 0x44e000e8, am3_pruss_ocp_clkctrl_regs }, 227 { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs }, 228 { 0x44e00018, am3_lcdc_clkctrl_regs }, 229 { 0x44e0014c, am3_clk_24mhz_clkctrl_regs }, 230 { 0x44e00400, am3_l4_wkup_clkctrl_regs }, 231 { 0x44e00414, am3_l3_aon_clkctrl_regs }, 232 { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs }, 233 { 0x44e00600, am3_mpu_clkctrl_regs }, 234 { 0x44e00800, am3_l4_rtc_clkctrl_regs }, 235 { 0x44e00900, am3_gfx_l3_clkctrl_regs }, 236 { 0x44e00a00, am3_l4_cefuse_clkctrl_regs }, 237 { 0 }, 238 }; 239 240 static struct ti_dt_clk am33xx_clks[] = { 241 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"), 242 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 243 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"), 244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"), 245 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"), 246 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"), 247 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"), 248 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"), 249 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"), 250 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"), 251 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"), 252 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"), 253 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"), 254 { .node_name = NULL }, 255 }; 256 257 static const char *enable_init_clks[] = { 258 "dpll_ddr_m2_ck", 259 "dpll_mpu_m2_ck", 260 "l3_gclk", 261 /* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */ 262 "l3-clkctrl:00bc:0", 263 "l4hs_gclk", 264 "l4fw_gclk", 265 "l4ls_gclk", 266 /* Required for external peripherals like, Audio codecs */ 267 "clkout2_ck", 268 }; 269 270 int __init am33xx_dt_clk_init(void) 271 { 272 struct clk *clk1, *clk2; 273 274 ti_dt_clocks_register(am33xx_clks); 275 276 omap2_clk_disable_autoidle_all(); 277 278 ti_clk_add_aliases(); 279 280 omap2_clk_enable_init_clocks(enable_init_clks, 281 ARRAY_SIZE(enable_init_clks)); 282 283 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always 284 * physically present, in such a case HWMOD enabling of 285 * clock would be failure with default parent. And timer 286 * probe thinks clock is already enabled, this leads to 287 * crash upon accessing timer 3 & 6 registers in probe. 288 * Fix by setting parent of both these timers to master 289 * oscillator clock. 290 */ 291 292 clk1 = clk_get_sys(NULL, "sys_clkin_ck"); 293 clk2 = clk_get_sys(NULL, "timer3_fck"); 294 clk_set_parent(clk2, clk1); 295 296 clk2 = clk_get_sys(NULL, "timer6_fck"); 297 clk_set_parent(clk2, clk1); 298 /* 299 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per 300 * the design/spec, so as a result, for example, timer which supposed 301 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is 302 * not expected by any use-case, so change WDT1 clock source to PRCM 303 * 32KHz clock. 304 */ 305 clk1 = clk_get_sys(NULL, "wdt1_fck"); 306 clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); 307 clk_set_parent(clk1, clk2); 308 309 return 0; 310 } 311