145622e21STero Kristo /* 245622e21STero Kristo * AM33XX Clock init 345622e21STero Kristo * 445622e21STero Kristo * Copyright (C) 2013 Texas Instruments, Inc 545622e21STero Kristo * Tero Kristo (t-kristo@ti.com) 645622e21STero Kristo * 745622e21STero Kristo * This program is free software; you can redistribute it and/or 845622e21STero Kristo * modify it under the terms of the GNU General Public License as 945622e21STero Kristo * published by the Free Software Foundation version 2. 1045622e21STero Kristo * 1145622e21STero Kristo * This program is distributed "as is" WITHOUT ANY WARRANTY of any 1245622e21STero Kristo * kind, whether express or implied; without even the implied warranty 1345622e21STero Kristo * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1445622e21STero Kristo * GNU General Public License for more details. 1545622e21STero Kristo */ 1645622e21STero Kristo 1745622e21STero Kristo #include <linux/kernel.h> 1845622e21STero Kristo #include <linux/list.h> 191b29e601SStephen Boyd #include <linux/clk.h> 2045622e21STero Kristo #include <linux/clk-provider.h> 2145622e21STero Kristo #include <linux/clk/ti.h> 22df54bfc5STero Kristo #include <dt-bindings/clock/am3.h> 2345622e21STero Kristo 24a5aa8a60STero Kristo #include "clock.h" 25a5aa8a60STero Kristo 26296e583eSTero Kristo static const char * const am3_gpio1_dbclk_parents[] __initconst = { 27296e583eSTero Kristo "clk-24mhz-clkctrl:0000:0", 28296e583eSTero Kristo NULL, 29296e583eSTero Kristo }; 30296e583eSTero Kristo 31296e583eSTero Kristo static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { 32296e583eSTero Kristo { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, 33296e583eSTero Kristo { 0 }, 34296e583eSTero Kristo }; 35296e583eSTero Kristo 36296e583eSTero Kristo static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { 37296e583eSTero Kristo { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, 38296e583eSTero Kristo { 0 }, 39296e583eSTero Kristo }; 40296e583eSTero Kristo 41296e583eSTero Kristo static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = { 42296e583eSTero Kristo { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, 43296e583eSTero Kristo { 0 }, 44296e583eSTero Kristo }; 45296e583eSTero Kristo 46296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = { 47296e583eSTero Kristo { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 48296e583eSTero Kristo { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 49296e583eSTero Kristo { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 50296e583eSTero Kristo { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 51296e583eSTero Kristo { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 52296e583eSTero Kristo { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 53296e583eSTero Kristo { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 54296e583eSTero Kristo { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 55296e583eSTero Kristo { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 56296e583eSTero Kristo { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 57296e583eSTero Kristo { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 58296e583eSTero Kristo { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 59296e583eSTero Kristo { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 60296e583eSTero Kristo { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 61296e583eSTero Kristo { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 62296e583eSTero Kristo { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 63296e583eSTero Kristo { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 64296e583eSTero Kristo { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 65296e583eSTero Kristo { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 66296e583eSTero Kristo { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 67296e583eSTero Kristo { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 68296e583eSTero Kristo { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 69296e583eSTero Kristo { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 70296e583eSTero Kristo { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 71296e583eSTero Kristo { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 72296e583eSTero Kristo { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 73296e583eSTero Kristo { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 74296e583eSTero Kristo { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 75296e583eSTero Kristo { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 76296e583eSTero Kristo { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 77296e583eSTero Kristo { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 78296e583eSTero Kristo { 0 }, 79296e583eSTero Kristo }; 80296e583eSTero Kristo 81296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = { 82296e583eSTero Kristo { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" }, 83296e583eSTero Kristo { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" }, 84296e583eSTero Kristo { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" }, 85296e583eSTero Kristo { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" }, 86296e583eSTero Kristo { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 87296e583eSTero Kristo { 0 }, 88296e583eSTero Kristo }; 89296e583eSTero Kristo 90296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = { 91296e583eSTero Kristo { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 92296e583eSTero Kristo { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" }, 93296e583eSTero Kristo { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 94296e583eSTero Kristo { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" }, 95296e583eSTero Kristo { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 96296e583eSTero Kristo { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 97296e583eSTero Kristo { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 98296e583eSTero Kristo { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 99296e583eSTero Kristo { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 100296e583eSTero Kristo { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" }, 101296e583eSTero Kristo { 0 }, 102296e583eSTero Kristo }; 103296e583eSTero Kristo 104296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = { 105296e583eSTero Kristo { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" }, 106296e583eSTero Kristo { 0 }, 107296e583eSTero Kristo }; 108296e583eSTero Kristo 109296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = { 1104d0030bdSTero Kristo { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" }, 111296e583eSTero Kristo { 0 }, 112296e583eSTero Kristo }; 113296e583eSTero Kristo 114296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = { 115296e583eSTero Kristo { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" }, 116296e583eSTero Kristo { 0 }, 117296e583eSTero Kristo }; 118296e583eSTero Kristo 119296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = { 120296e583eSTero Kristo { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" }, 121296e583eSTero Kristo { 0 }, 122296e583eSTero Kristo }; 123296e583eSTero Kristo 124296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = { 125296e583eSTero Kristo { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" }, 126296e583eSTero Kristo { 0 }, 127296e583eSTero Kristo }; 128296e583eSTero Kristo 129296e583eSTero Kristo static const char * const am3_gpio0_dbclk_parents[] __initconst = { 130296e583eSTero Kristo "gpio0_dbclk_mux_ck", 131296e583eSTero Kristo NULL, 132296e583eSTero Kristo }; 133296e583eSTero Kristo 134296e583eSTero Kristo static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { 135296e583eSTero Kristo { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, 136296e583eSTero Kristo { 0 }, 137296e583eSTero Kristo }; 138296e583eSTero Kristo 139296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { 140296e583eSTero Kristo { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 141296e583eSTero Kristo { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 142296e583eSTero Kristo { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 143296e583eSTero Kristo { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 144296e583eSTero Kristo { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 145296e583eSTero Kristo { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" }, 146296e583eSTero Kristo { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" }, 147296e583eSTero Kristo { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, 148296e583eSTero Kristo { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" }, 149296e583eSTero Kristo { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" }, 150296e583eSTero Kristo { 0 }, 151296e583eSTero Kristo }; 152296e583eSTero Kristo 153296e583eSTero Kristo static const char * const am3_dbg_sysclk_ck_parents[] __initconst = { 154296e583eSTero Kristo "sys_clkin_ck", 155296e583eSTero Kristo NULL, 156296e583eSTero Kristo }; 157296e583eSTero Kristo 158296e583eSTero Kristo static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = { 159296e583eSTero Kristo "l3-aon-clkctrl:0000:19", 160296e583eSTero Kristo "l3-aon-clkctrl:0000:30", 161296e583eSTero Kristo NULL, 162296e583eSTero Kristo }; 163296e583eSTero Kristo 164296e583eSTero Kristo static const char * const am3_trace_clk_div_ck_parents[] __initconst = { 165296e583eSTero Kristo "l3-aon-clkctrl:0000:20", 166296e583eSTero Kristo NULL, 167296e583eSTero Kristo }; 168296e583eSTero Kristo 169296e583eSTero Kristo static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = { 170296e583eSTero Kristo .max_div = 64, 171296e583eSTero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 172296e583eSTero Kristo }; 173296e583eSTero Kristo 174296e583eSTero Kristo static const char * const am3_stm_clk_div_ck_parents[] __initconst = { 175296e583eSTero Kristo "l3-aon-clkctrl:0000:22", 176296e583eSTero Kristo NULL, 177296e583eSTero Kristo }; 178296e583eSTero Kristo 179296e583eSTero Kristo static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = { 180296e583eSTero Kristo .max_div = 64, 181296e583eSTero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 182296e583eSTero Kristo }; 183296e583eSTero Kristo 184296e583eSTero Kristo static const char * const am3_dbg_clka_ck_parents[] __initconst = { 185296e583eSTero Kristo "dpll_core_m4_ck", 186296e583eSTero Kristo NULL, 187296e583eSTero Kristo }; 188296e583eSTero Kristo 189296e583eSTero Kristo static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = { 190296e583eSTero Kristo { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL }, 191296e583eSTero Kristo { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, 192296e583eSTero Kristo { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, 193296e583eSTero Kristo { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data }, 194296e583eSTero Kristo { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data }, 195296e583eSTero Kristo { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL }, 196296e583eSTero Kristo { 0 }, 197296e583eSTero Kristo }; 198296e583eSTero Kristo 199296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = { 200296e583eSTero Kristo { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" }, 201296e583eSTero Kristo { 0 }, 202296e583eSTero Kristo }; 203296e583eSTero Kristo 204296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = { 205296e583eSTero Kristo { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" }, 206296e583eSTero Kristo { 0 }, 207296e583eSTero Kristo }; 208296e583eSTero Kristo 209296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = { 210296e583eSTero Kristo { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 211296e583eSTero Kristo { 0 }, 212296e583eSTero Kristo }; 213296e583eSTero Kristo 214296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = { 215dc6dbd51STero Kristo { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" }, 216296e583eSTero Kristo { 0 }, 217296e583eSTero Kristo }; 218296e583eSTero Kristo 219296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = { 22019407181STero Kristo { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" }, 221296e583eSTero Kristo { 0 }, 222296e583eSTero Kristo }; 223296e583eSTero Kristo 224296e583eSTero Kristo static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = { 225296e583eSTero Kristo { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, 226296e583eSTero Kristo { 0 }, 227296e583eSTero Kristo }; 228296e583eSTero Kristo 229296e583eSTero Kristo const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = { 230296e583eSTero Kristo { 0x44e00038, am3_l4ls_clkctrl_regs }, 231296e583eSTero Kristo { 0x44e0001c, am3_l3s_clkctrl_regs }, 232296e583eSTero Kristo { 0x44e00024, am3_l3_clkctrl_regs }, 233296e583eSTero Kristo { 0x44e00120, am3_l4hs_clkctrl_regs }, 234296e583eSTero Kristo { 0x44e000e8, am3_pruss_ocp_clkctrl_regs }, 235296e583eSTero Kristo { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs }, 236296e583eSTero Kristo { 0x44e00018, am3_lcdc_clkctrl_regs }, 237296e583eSTero Kristo { 0x44e0014c, am3_clk_24mhz_clkctrl_regs }, 238296e583eSTero Kristo { 0x44e00400, am3_l4_wkup_clkctrl_regs }, 239296e583eSTero Kristo { 0x44e00414, am3_l3_aon_clkctrl_regs }, 240296e583eSTero Kristo { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs }, 241296e583eSTero Kristo { 0x44e00600, am3_mpu_clkctrl_regs }, 242296e583eSTero Kristo { 0x44e00800, am3_l4_rtc_clkctrl_regs }, 243296e583eSTero Kristo { 0x44e00900, am3_gfx_l3_clkctrl_regs }, 244296e583eSTero Kristo { 0x44e00a00, am3_l4_cefuse_clkctrl_regs }, 245296e583eSTero Kristo { 0 }, 246296e583eSTero Kristo }; 247296e583eSTero Kristo 248296e583eSTero Kristo static struct ti_dt_clk am33xx_clks[] = { 249296e583eSTero Kristo DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"), 250296e583eSTero Kristo DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 251296e583eSTero Kristo DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"), 252296e583eSTero Kristo DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"), 253296e583eSTero Kristo DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"), 254296e583eSTero Kristo DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"), 255296e583eSTero Kristo DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"), 256296e583eSTero Kristo DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"), 257296e583eSTero Kristo DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"), 258296e583eSTero Kristo DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"), 259296e583eSTero Kristo DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"), 260296e583eSTero Kristo DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"), 261296e583eSTero Kristo DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"), 262296e583eSTero Kristo { .node_name = NULL }, 263296e583eSTero Kristo }; 264296e583eSTero Kristo 26545622e21STero Kristo static const char *enable_init_clks[] = { 26645622e21STero Kristo "dpll_ddr_m2_ck", 26745622e21STero Kristo "dpll_mpu_m2_ck", 26845622e21STero Kristo "l3_gclk", 269*9fac0899STony Lindgren /* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */ 270*9fac0899STony Lindgren "l3-clkctrl:00bc:0", 27145622e21STero Kristo "l4hs_gclk", 27245622e21STero Kristo "l4fw_gclk", 27345622e21STero Kristo "l4ls_gclk", 27445622e21STero Kristo /* Required for external peripherals like, Audio codecs */ 27545622e21STero Kristo "clkout2_ck", 27645622e21STero Kristo }; 27745622e21STero Kristo 27845622e21STero Kristo int __init am33xx_dt_clk_init(void) 27945622e21STero Kristo { 28045622e21STero Kristo struct clk *clk1, *clk2; 28145622e21STero Kristo 282296e583eSTero Kristo if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) 283e97017f9STero Kristo ti_dt_clocks_register(am33xx_compat_clks); 284296e583eSTero Kristo else 285296e583eSTero Kristo ti_dt_clocks_register(am33xx_clks); 28645622e21STero Kristo 28745622e21STero Kristo omap2_clk_disable_autoidle_all(); 28845622e21STero Kristo 2897368b18dSTero Kristo ti_clk_add_aliases(); 2907368b18dSTero Kristo 29145622e21STero Kristo omap2_clk_enable_init_clocks(enable_init_clks, 29245622e21STero Kristo ARRAY_SIZE(enable_init_clks)); 29345622e21STero Kristo 29445622e21STero Kristo /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always 29545622e21STero Kristo * physically present, in such a case HWMOD enabling of 29645622e21STero Kristo * clock would be failure with default parent. And timer 29745622e21STero Kristo * probe thinks clock is already enabled, this leads to 29845622e21STero Kristo * crash upon accessing timer 3 & 6 registers in probe. 29945622e21STero Kristo * Fix by setting parent of both these timers to master 30045622e21STero Kristo * oscillator clock. 30145622e21STero Kristo */ 30245622e21STero Kristo 30345622e21STero Kristo clk1 = clk_get_sys(NULL, "sys_clkin_ck"); 30445622e21STero Kristo clk2 = clk_get_sys(NULL, "timer3_fck"); 30545622e21STero Kristo clk_set_parent(clk2, clk1); 30645622e21STero Kristo 30745622e21STero Kristo clk2 = clk_get_sys(NULL, "timer6_fck"); 30845622e21STero Kristo clk_set_parent(clk2, clk1); 30945622e21STero Kristo /* 31045622e21STero Kristo * The On-Chip 32K RC Osc clock is not an accurate clock-source as per 31145622e21STero Kristo * the design/spec, so as a result, for example, timer which supposed 31245622e21STero Kristo * to get expired @60Sec, but will expire somewhere ~@40Sec, which is 31345622e21STero Kristo * not expected by any use-case, so change WDT1 clock source to PRCM 31445622e21STero Kristo * 32KHz clock. 31545622e21STero Kristo */ 31645622e21STero Kristo clk1 = clk_get_sys(NULL, "wdt1_fck"); 31745622e21STero Kristo clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); 31845622e21STero Kristo clk_set_parent(clk1, clk2); 31945622e21STero Kristo 32045622e21STero Kristo return 0; 32145622e21STero Kristo } 322