145622e21STero Kristo /* 245622e21STero Kristo * AM33XX Clock init 345622e21STero Kristo * 445622e21STero Kristo * Copyright (C) 2013 Texas Instruments, Inc 545622e21STero Kristo * Tero Kristo (t-kristo@ti.com) 645622e21STero Kristo * 745622e21STero Kristo * This program is free software; you can redistribute it and/or 845622e21STero Kristo * modify it under the terms of the GNU General Public License as 945622e21STero Kristo * published by the Free Software Foundation version 2. 1045622e21STero Kristo * 1145622e21STero Kristo * This program is distributed "as is" WITHOUT ANY WARRANTY of any 1245622e21STero Kristo * kind, whether express or implied; without even the implied warranty 1345622e21STero Kristo * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1445622e21STero Kristo * GNU General Public License for more details. 1545622e21STero Kristo */ 1645622e21STero Kristo 1745622e21STero Kristo #include <linux/kernel.h> 1845622e21STero Kristo #include <linux/list.h> 191b29e601SStephen Boyd #include <linux/clk.h> 2045622e21STero Kristo #include <linux/clk-provider.h> 2145622e21STero Kristo #include <linux/clk/ti.h> 2245622e21STero Kristo 2345622e21STero Kristo static struct ti_dt_clk am33xx_clks[] = { 2445622e21STero Kristo DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), 2545622e21STero Kristo DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), 2645622e21STero Kristo DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 2745622e21STero Kristo DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), 2845622e21STero Kristo DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), 2945622e21STero Kristo DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 3045622e21STero Kristo DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), 3145622e21STero Kristo DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), 3245622e21STero Kristo DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 3345622e21STero Kristo DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 3445622e21STero Kristo DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), 3545622e21STero Kristo DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), 3645622e21STero Kristo DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), 3745622e21STero Kristo DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 3845622e21STero Kristo DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 3945622e21STero Kristo DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), 4045622e21STero Kristo DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), 4145622e21STero Kristo DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), 4245622e21STero Kristo DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), 4345622e21STero Kristo DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), 4445622e21STero Kristo DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 4545622e21STero Kristo DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 4645622e21STero Kristo DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), 4745622e21STero Kristo DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), 4845622e21STero Kristo DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), 4945622e21STero Kristo DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), 5045622e21STero Kristo DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), 5145622e21STero Kristo DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), 5245622e21STero Kristo DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), 5345622e21STero Kristo DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), 5445622e21STero Kristo DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), 5545622e21STero Kristo DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), 5645622e21STero Kristo DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), 5745622e21STero Kristo DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), 5845622e21STero Kristo DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), 5945622e21STero Kristo DT_CLK(NULL, "mmu_fck", "mmu_fck"), 6045622e21STero Kristo DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), 6145622e21STero Kristo DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), 6245622e21STero Kristo DT_CLK(NULL, "sha0_fck", "sha0_fck"), 6345622e21STero Kristo DT_CLK(NULL, "aes0_fck", "aes0_fck"), 6445622e21STero Kristo DT_CLK(NULL, "rng_fck", "rng_fck"), 6545622e21STero Kristo DT_CLK(NULL, "timer1_fck", "timer1_fck"), 6645622e21STero Kristo DT_CLK(NULL, "timer2_fck", "timer2_fck"), 6745622e21STero Kristo DT_CLK(NULL, "timer3_fck", "timer3_fck"), 6845622e21STero Kristo DT_CLK(NULL, "timer4_fck", "timer4_fck"), 6945622e21STero Kristo DT_CLK(NULL, "timer5_fck", "timer5_fck"), 7045622e21STero Kristo DT_CLK(NULL, "timer6_fck", "timer6_fck"), 7145622e21STero Kristo DT_CLK(NULL, "timer7_fck", "timer7_fck"), 7245622e21STero Kristo DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), 7345622e21STero Kristo DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), 7445622e21STero Kristo DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), 7545622e21STero Kristo DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), 7645622e21STero Kristo DT_CLK(NULL, "l3_gclk", "l3_gclk"), 7745622e21STero Kristo DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), 7845622e21STero Kristo DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), 7945622e21STero Kristo DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), 8045622e21STero Kristo DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), 8145622e21STero Kristo DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), 8245622e21STero Kristo DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), 8345622e21STero Kristo DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), 8445622e21STero Kristo DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), 8545622e21STero Kristo DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), 8645622e21STero Kristo DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), 8745622e21STero Kristo DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), 8845622e21STero Kristo DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 8945622e21STero Kristo DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 9045622e21STero Kristo DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 9145622e21STero Kristo DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), 9245622e21STero Kristo DT_CLK(NULL, "mmc_clk", "mmc_clk"), 9345622e21STero Kristo DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), 9445622e21STero Kristo DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), 9545622e21STero Kristo DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), 9645622e21STero Kristo DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), 9745622e21STero Kristo DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 9845622e21STero Kristo DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 9945622e21STero Kristo DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), 10045622e21STero Kristo DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), 10145622e21STero Kristo DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), 10245622e21STero Kristo DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), 10345622e21STero Kristo DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), 10445622e21STero Kristo DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), 10545622e21STero Kristo DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), 10645622e21STero Kristo DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), 10745622e21STero Kristo DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), 10845622e21STero Kristo DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), 10945622e21STero Kristo { .node_name = NULL }, 11045622e21STero Kristo }; 11145622e21STero Kristo 11245622e21STero Kristo static const char *enable_init_clks[] = { 11345622e21STero Kristo "dpll_ddr_m2_ck", 11445622e21STero Kristo "dpll_mpu_m2_ck", 11545622e21STero Kristo "l3_gclk", 11645622e21STero Kristo "l4hs_gclk", 11745622e21STero Kristo "l4fw_gclk", 11845622e21STero Kristo "l4ls_gclk", 11945622e21STero Kristo /* Required for external peripherals like, Audio codecs */ 12045622e21STero Kristo "clkout2_ck", 12145622e21STero Kristo }; 12245622e21STero Kristo 12345622e21STero Kristo int __init am33xx_dt_clk_init(void) 12445622e21STero Kristo { 12545622e21STero Kristo struct clk *clk1, *clk2; 12645622e21STero Kristo 12745622e21STero Kristo ti_dt_clocks_register(am33xx_clks); 12845622e21STero Kristo 12945622e21STero Kristo omap2_clk_disable_autoidle_all(); 13045622e21STero Kristo 13145622e21STero Kristo omap2_clk_enable_init_clocks(enable_init_clks, 13245622e21STero Kristo ARRAY_SIZE(enable_init_clks)); 13345622e21STero Kristo 13445622e21STero Kristo /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always 13545622e21STero Kristo * physically present, in such a case HWMOD enabling of 13645622e21STero Kristo * clock would be failure with default parent. And timer 13745622e21STero Kristo * probe thinks clock is already enabled, this leads to 13845622e21STero Kristo * crash upon accessing timer 3 & 6 registers in probe. 13945622e21STero Kristo * Fix by setting parent of both these timers to master 14045622e21STero Kristo * oscillator clock. 14145622e21STero Kristo */ 14245622e21STero Kristo 14345622e21STero Kristo clk1 = clk_get_sys(NULL, "sys_clkin_ck"); 14445622e21STero Kristo clk2 = clk_get_sys(NULL, "timer3_fck"); 14545622e21STero Kristo clk_set_parent(clk2, clk1); 14645622e21STero Kristo 14745622e21STero Kristo clk2 = clk_get_sys(NULL, "timer6_fck"); 14845622e21STero Kristo clk_set_parent(clk2, clk1); 14945622e21STero Kristo /* 15045622e21STero Kristo * The On-Chip 32K RC Osc clock is not an accurate clock-source as per 15145622e21STero Kristo * the design/spec, so as a result, for example, timer which supposed 15245622e21STero Kristo * to get expired @60Sec, but will expire somewhere ~@40Sec, which is 15345622e21STero Kristo * not expected by any use-case, so change WDT1 clock source to PRCM 15445622e21STero Kristo * 32KHz clock. 15545622e21STero Kristo */ 15645622e21STero Kristo clk1 = clk_get_sys(NULL, "wdt1_fck"); 15745622e21STero Kristo clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); 15845622e21STero Kristo clk_set_parent(clk1, clk2); 15945622e21STero Kristo 16045622e21STero Kristo return 0; 16145622e21STero Kristo } 162