xref: /openbmc/linux/drivers/clk/ti/apll.c (revision 6d99a79c) 
1 /*
2  * OMAP APLL clock support
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * J Keerthy <j-keerthy@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17 
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/string.h>
25 #include <linux/log2.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/clk/ti.h>
29 #include <linux/delay.h>
30 
31 #include "clock.h"
32 
33 #define APLL_FORCE_LOCK 0x1
34 #define APLL_AUTO_IDLE	0x2
35 #define MAX_APLL_WAIT_TRIES		1000000
36 
37 #undef pr_fmt
38 #define pr_fmt(fmt) "%s: " fmt, __func__
39 
40 static int dra7_apll_enable(struct clk_hw *hw)
41 {
42 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
43 	int r = 0, i = 0;
44 	struct dpll_data *ad;
45 	const char *clk_name;
46 	u8 state = 1;
47 	u32 v;
48 
49 	ad = clk->dpll_data;
50 	if (!ad)
51 		return -EINVAL;
52 
53 	clk_name = clk_hw_get_name(&clk->hw);
54 
55 	state <<= __ffs(ad->idlest_mask);
56 
57 	/* Check is already locked */
58 	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
59 
60 	if ((v & ad->idlest_mask) == state)
61 		return r;
62 
63 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
64 	v &= ~ad->enable_mask;
65 	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
66 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
67 
68 	state <<= __ffs(ad->idlest_mask);
69 
70 	while (1) {
71 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
72 		if ((v & ad->idlest_mask) == state)
73 			break;
74 		if (i > MAX_APLL_WAIT_TRIES)
75 			break;
76 		i++;
77 		udelay(1);
78 	}
79 
80 	if (i == MAX_APLL_WAIT_TRIES) {
81 		pr_warn("clock: %s failed transition to '%s'\n",
82 			clk_name, (state) ? "locked" : "bypassed");
83 		r = -EBUSY;
84 	} else
85 		pr_debug("clock: %s transition to '%s' in %d loops\n",
86 			 clk_name, (state) ? "locked" : "bypassed", i);
87 
88 	return r;
89 }
90 
91 static void dra7_apll_disable(struct clk_hw *hw)
92 {
93 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
94 	struct dpll_data *ad;
95 	u8 state = 1;
96 	u32 v;
97 
98 	ad = clk->dpll_data;
99 
100 	state <<= __ffs(ad->idlest_mask);
101 
102 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
103 	v &= ~ad->enable_mask;
104 	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
105 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
106 }
107 
108 static int dra7_apll_is_enabled(struct clk_hw *hw)
109 {
110 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
111 	struct dpll_data *ad;
112 	u32 v;
113 
114 	ad = clk->dpll_data;
115 
116 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
117 	v &= ad->enable_mask;
118 
119 	v >>= __ffs(ad->enable_mask);
120 
121 	return v == APLL_AUTO_IDLE ? 0 : 1;
122 }
123 
124 static u8 dra7_init_apll_parent(struct clk_hw *hw)
125 {
126 	return 0;
127 }
128 
129 static const struct clk_ops apll_ck_ops = {
130 	.enable		= &dra7_apll_enable,
131 	.disable	= &dra7_apll_disable,
132 	.is_enabled	= &dra7_apll_is_enabled,
133 	.get_parent	= &dra7_init_apll_parent,
134 };
135 
136 static void __init omap_clk_register_apll(void *user,
137 					  struct device_node *node)
138 {
139 	struct clk_hw *hw = user;
140 	struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
141 	struct dpll_data *ad = clk_hw->dpll_data;
142 	struct clk *clk;
143 
144 	clk = of_clk_get(node, 0);
145 	if (IS_ERR(clk)) {
146 		pr_debug("clk-ref for %pOFn not ready, retry\n",
147 			 node);
148 		if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
149 			return;
150 
151 		goto cleanup;
152 	}
153 
154 	ad->clk_ref = __clk_get_hw(clk);
155 
156 	clk = of_clk_get(node, 1);
157 	if (IS_ERR(clk)) {
158 		pr_debug("clk-bypass for %pOFn not ready, retry\n",
159 			 node);
160 		if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
161 			return;
162 
163 		goto cleanup;
164 	}
165 
166 	ad->clk_bypass = __clk_get_hw(clk);
167 
168 	clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
169 	if (!IS_ERR(clk)) {
170 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
171 		kfree(clk_hw->hw.init->parent_names);
172 		kfree(clk_hw->hw.init);
173 		return;
174 	}
175 
176 cleanup:
177 	kfree(clk_hw->dpll_data);
178 	kfree(clk_hw->hw.init->parent_names);
179 	kfree(clk_hw->hw.init);
180 	kfree(clk_hw);
181 }
182 
183 static void __init of_dra7_apll_setup(struct device_node *node)
184 {
185 	struct dpll_data *ad = NULL;
186 	struct clk_hw_omap *clk_hw = NULL;
187 	struct clk_init_data *init = NULL;
188 	const char **parent_names = NULL;
189 	int ret;
190 
191 	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
192 	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
193 	init = kzalloc(sizeof(*init), GFP_KERNEL);
194 	if (!ad || !clk_hw || !init)
195 		goto cleanup;
196 
197 	clk_hw->dpll_data = ad;
198 	clk_hw->hw.init = init;
199 
200 	init->name = node->name;
201 	init->ops = &apll_ck_ops;
202 
203 	init->num_parents = of_clk_get_parent_count(node);
204 	if (init->num_parents < 1) {
205 		pr_err("dra7 apll %pOFn must have parent(s)\n", node);
206 		goto cleanup;
207 	}
208 
209 	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
210 	if (!parent_names)
211 		goto cleanup;
212 
213 	of_clk_parent_fill(node, parent_names, init->num_parents);
214 
215 	init->parent_names = parent_names;
216 
217 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
218 	ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);
219 
220 	if (ret)
221 		goto cleanup;
222 
223 	ad->idlest_mask = 0x1;
224 	ad->enable_mask = 0x3;
225 
226 	omap_clk_register_apll(&clk_hw->hw, node);
227 	return;
228 
229 cleanup:
230 	kfree(parent_names);
231 	kfree(ad);
232 	kfree(clk_hw);
233 	kfree(init);
234 }
235 CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
236 
237 #define OMAP2_EN_APLL_LOCKED	0x3
238 #define OMAP2_EN_APLL_STOPPED	0x0
239 
240 static int omap2_apll_is_enabled(struct clk_hw *hw)
241 {
242 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
243 	struct dpll_data *ad = clk->dpll_data;
244 	u32 v;
245 
246 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
247 	v &= ad->enable_mask;
248 
249 	v >>= __ffs(ad->enable_mask);
250 
251 	return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
252 }
253 
254 static unsigned long omap2_apll_recalc(struct clk_hw *hw,
255 				       unsigned long parent_rate)
256 {
257 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
258 
259 	if (omap2_apll_is_enabled(hw))
260 		return clk->fixed_rate;
261 
262 	return 0;
263 }
264 
265 static int omap2_apll_enable(struct clk_hw *hw)
266 {
267 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
268 	struct dpll_data *ad = clk->dpll_data;
269 	u32 v;
270 	int i = 0;
271 
272 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
273 	v &= ~ad->enable_mask;
274 	v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
275 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
276 
277 	while (1) {
278 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
279 		if (v & ad->idlest_mask)
280 			break;
281 		if (i > MAX_APLL_WAIT_TRIES)
282 			break;
283 		i++;
284 		udelay(1);
285 	}
286 
287 	if (i == MAX_APLL_WAIT_TRIES) {
288 		pr_warn("%s failed to transition to locked\n",
289 			clk_hw_get_name(&clk->hw));
290 		return -EBUSY;
291 	}
292 
293 	return 0;
294 }
295 
296 static void omap2_apll_disable(struct clk_hw *hw)
297 {
298 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
299 	struct dpll_data *ad = clk->dpll_data;
300 	u32 v;
301 
302 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
303 	v &= ~ad->enable_mask;
304 	v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
305 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
306 }
307 
308 static const struct clk_ops omap2_apll_ops = {
309 	.enable		= &omap2_apll_enable,
310 	.disable	= &omap2_apll_disable,
311 	.is_enabled	= &omap2_apll_is_enabled,
312 	.recalc_rate	= &omap2_apll_recalc,
313 };
314 
315 static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
316 {
317 	struct dpll_data *ad = clk->dpll_data;
318 	u32 v;
319 
320 	v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
321 	v &= ~ad->autoidle_mask;
322 	v |= val << __ffs(ad->autoidle_mask);
323 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
324 }
325 
326 #define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP	0x3
327 #define OMAP2_APLL_AUTOIDLE_DISABLE		0x0
328 
329 static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
330 {
331 	omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
332 }
333 
334 static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
335 {
336 	omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
337 }
338 
339 static const struct clk_hw_omap_ops omap2_apll_hwops = {
340 	.allow_idle	= &omap2_apll_allow_idle,
341 	.deny_idle	= &omap2_apll_deny_idle,
342 };
343 
344 static void __init of_omap2_apll_setup(struct device_node *node)
345 {
346 	struct dpll_data *ad = NULL;
347 	struct clk_hw_omap *clk_hw = NULL;
348 	struct clk_init_data *init = NULL;
349 	struct clk *clk;
350 	const char *parent_name;
351 	u32 val;
352 	int ret;
353 
354 	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
355 	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
356 	init = kzalloc(sizeof(*init), GFP_KERNEL);
357 
358 	if (!ad || !clk_hw || !init)
359 		goto cleanup;
360 
361 	clk_hw->dpll_data = ad;
362 	clk_hw->hw.init = init;
363 	init->ops = &omap2_apll_ops;
364 	init->name = node->name;
365 	clk_hw->ops = &omap2_apll_hwops;
366 
367 	init->num_parents = of_clk_get_parent_count(node);
368 	if (init->num_parents != 1) {
369 		pr_err("%pOFn must have one parent\n", node);
370 		goto cleanup;
371 	}
372 
373 	parent_name = of_clk_get_parent_name(node, 0);
374 	init->parent_names = &parent_name;
375 
376 	if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
377 		pr_err("%pOFn missing clock-frequency\n", node);
378 		goto cleanup;
379 	}
380 	clk_hw->fixed_rate = val;
381 
382 	if (of_property_read_u32(node, "ti,bit-shift", &val)) {
383 		pr_err("%pOFn missing bit-shift\n", node);
384 		goto cleanup;
385 	}
386 
387 	clk_hw->enable_bit = val;
388 	ad->enable_mask = 0x3 << val;
389 	ad->autoidle_mask = 0x3 << val;
390 
391 	if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
392 		pr_err("%pOFn missing idlest-shift\n", node);
393 		goto cleanup;
394 	}
395 
396 	ad->idlest_mask = 1 << val;
397 
398 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
399 	ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);
400 	ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);
401 
402 	if (ret)
403 		goto cleanup;
404 
405 	clk = clk_register(NULL, &clk_hw->hw);
406 	if (!IS_ERR(clk)) {
407 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
408 		kfree(init);
409 		return;
410 	}
411 cleanup:
412 	kfree(ad);
413 	kfree(clk_hw);
414 	kfree(init);
415 }
416 CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
417 	       of_omap2_apll_setup);
418