121330497STony Lindgren /* 221330497STony Lindgren * This program is free software; you can redistribute it and/or 321330497STony Lindgren * modify it under the terms of the GNU General Public License as 421330497STony Lindgren * published by the Free Software Foundation version 2. 521330497STony Lindgren * 621330497STony Lindgren * This program is distributed "as is" WITHOUT ANY WARRANTY of any 721330497STony Lindgren * kind, whether express or implied; without even the implied warranty 821330497STony Lindgren * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 921330497STony Lindgren * GNU General Public License for more details. 1021330497STony Lindgren */ 1121330497STony Lindgren 1221330497STony Lindgren #include <linux/clk.h> 1321330497STony Lindgren #include <linux/clkdev.h> 1421330497STony Lindgren #include <linux/clk-provider.h> 1521330497STony Lindgren #include <linux/delay.h> 1621330497STony Lindgren #include <linux/err.h> 1721330497STony Lindgren #include <linux/math64.h> 1821330497STony Lindgren #include <linux/module.h> 1921330497STony Lindgren #include <linux/of_device.h> 2021330497STony Lindgren #include <linux/string.h> 2121330497STony Lindgren 2221330497STony Lindgren #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */ 2321330497STony Lindgren #define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64 2421330497STony Lindgren #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d 2521330497STony Lindgren 2621330497STony Lindgren #define ADPLL_PWRCTRL_OFFSET 0x00 2721330497STony Lindgren #define ADPLL_PWRCTRL_PONIN 5 2821330497STony Lindgren #define ADPLL_PWRCTRL_PGOODIN 4 2921330497STony Lindgren #define ADPLL_PWRCTRL_RET 3 3021330497STony Lindgren #define ADPLL_PWRCTRL_ISORET 2 3121330497STony Lindgren #define ADPLL_PWRCTRL_ISOSCAN 1 3221330497STony Lindgren #define ADPLL_PWRCTRL_OFFMODE 0 3321330497STony Lindgren 3421330497STony Lindgren #define ADPLL_CLKCTRL_OFFSET 0x04 3521330497STony Lindgren #define ADPLL_CLKCTRL_CLKDCOLDOEN 29 3621330497STony Lindgren #define ADPLL_CLKCTRL_IDLE 23 3721330497STony Lindgren #define ADPLL_CLKCTRL_CLKOUTEN 20 3821330497STony Lindgren #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */ 3921330497STony Lindgren #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19 4021330497STony Lindgren #define ADPLL_CLKCTRL_ULOWCLKEN 18 4121330497STony Lindgren #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17 4221330497STony Lindgren #define ADPLL_CLKCTRL_M2PWDNZ 16 4321330497STony Lindgren #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15 4421330497STony Lindgren #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13 4521330497STony Lindgren #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12 4621330497STony Lindgren #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10 4721330497STony Lindgren #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10 4821330497STony Lindgren #define ADPLL_CLKCTRL_TINITZ 0 4921330497STony Lindgren 5021330497STony Lindgren #define ADPLL_TENABLE_OFFSET 0x08 5121330497STony Lindgren #define ADPLL_TENABLEDIV_OFFSET 0x8c 5221330497STony Lindgren 5321330497STony Lindgren #define ADPLL_M2NDIV_OFFSET 0x10 5421330497STony Lindgren #define ADPLL_M2NDIV_M2 16 5521330497STony Lindgren #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5 5621330497STony Lindgren #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7 5721330497STony Lindgren 5821330497STony Lindgren #define ADPLL_MN2DIV_OFFSET 0x14 5921330497STony Lindgren #define ADPLL_MN2DIV_N2 16 6021330497STony Lindgren 6121330497STony Lindgren #define ADPLL_FRACDIV_OFFSET 0x18 6221330497STony Lindgren #define ADPLL_FRACDIV_REGSD 24 6321330497STony Lindgren #define ADPLL_FRACDIV_FRACTIONALM 0 6421330497STony Lindgren #define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff 6521330497STony Lindgren 6621330497STony Lindgren #define ADPLL_BWCTRL_OFFSET 0x1c 6721330497STony Lindgren #define ADPLL_BWCTRL_BWCONTROL 1 6821330497STony Lindgren #define ADPLL_BWCTRL_BW_INCR_DECRZ 0 6921330497STony Lindgren 7021330497STony Lindgren #define ADPLL_RESERVED_OFFSET 0x20 7121330497STony Lindgren 7221330497STony Lindgren #define ADPLL_STATUS_OFFSET 0x24 7321330497STony Lindgren #define ADPLL_STATUS_PONOUT 31 7421330497STony Lindgren #define ADPLL_STATUS_PGOODOUT 30 7521330497STony Lindgren #define ADPLL_STATUS_LDOPWDN 29 7621330497STony Lindgren #define ADPLL_STATUS_RECAL_BSTATUS3 28 7721330497STony Lindgren #define ADPLL_STATUS_RECAL_OPPIN 27 7821330497STony Lindgren #define ADPLL_STATUS_PHASELOCK 10 7921330497STony Lindgren #define ADPLL_STATUS_FREQLOCK 9 8021330497STony Lindgren #define ADPLL_STATUS_BYPASSACK 8 8121330497STony Lindgren #define ADPLL_STATUS_LOSSREF 6 8221330497STony Lindgren #define ADPLL_STATUS_CLKOUTENACK 5 8321330497STony Lindgren #define ADPLL_STATUS_LOCK2 4 8421330497STony Lindgren #define ADPLL_STATUS_M2CHANGEACK 3 8521330497STony Lindgren #define ADPLL_STATUS_HIGHJITTER 1 8621330497STony Lindgren #define ADPLL_STATUS_BYPASS 0 8721330497STony Lindgren #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \ 8821330497STony Lindgren BIT(ADPLL_STATUS_FREQLOCK)) 8921330497STony Lindgren 9021330497STony Lindgren #define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */ 9121330497STony Lindgren #define ADPLL_M3DIV_M3 0 9221330497STony Lindgren #define ADPLL_M3DIV_M3_WIDTH 5 9321330497STony Lindgren #define ADPLL_M3DIV_M3_MASK 0x1f 9421330497STony Lindgren 9521330497STony Lindgren #define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */ 9621330497STony Lindgren #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19 9721330497STony Lindgren #define ADPLL_RAMPCTRL_CLKRAMPRATE 16 9821330497STony Lindgren #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0 9921330497STony Lindgren 10021330497STony Lindgren #define MAX_ADPLL_INPUTS 3 10121330497STony Lindgren #define MAX_ADPLL_OUTPUTS 4 10221330497STony Lindgren #define ADPLL_MAX_RETRIES 5 10321330497STony Lindgren 10421330497STony Lindgren #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw) 10521330497STony Lindgren #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco) 10621330497STony Lindgren #define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw) 10721330497STony Lindgren 10821330497STony Lindgren enum ti_adpll_clocks { 10921330497STony Lindgren TI_ADPLL_DCO, 11021330497STony Lindgren TI_ADPLL_DCO_GATE, 11121330497STony Lindgren TI_ADPLL_N2, 11221330497STony Lindgren TI_ADPLL_M2, 11321330497STony Lindgren TI_ADPLL_M2_GATE, 11421330497STony Lindgren TI_ADPLL_BYPASS, 11521330497STony Lindgren TI_ADPLL_HIF, 11621330497STony Lindgren TI_ADPLL_DIV2, 11721330497STony Lindgren TI_ADPLL_CLKOUT, 11821330497STony Lindgren TI_ADPLL_CLKOUT2, 11921330497STony Lindgren TI_ADPLL_M3, 12021330497STony Lindgren }; 12121330497STony Lindgren 12221330497STony Lindgren #define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1) 12321330497STony Lindgren 12421330497STony Lindgren enum ti_adpll_inputs { 12521330497STony Lindgren TI_ADPLL_CLKINP, 12621330497STony Lindgren TI_ADPLL_CLKINPULOW, 12721330497STony Lindgren TI_ADPLL_CLKINPHIF, 12821330497STony Lindgren }; 12921330497STony Lindgren 13021330497STony Lindgren enum ti_adpll_s_outputs { 13121330497STony Lindgren TI_ADPLL_S_DCOCLKLDO, 13221330497STony Lindgren TI_ADPLL_S_CLKOUT, 13321330497STony Lindgren TI_ADPLL_S_CLKOUTX2, 13421330497STony Lindgren TI_ADPLL_S_CLKOUTHIF, 13521330497STony Lindgren }; 13621330497STony Lindgren 13721330497STony Lindgren enum ti_adpll_lj_outputs { 13821330497STony Lindgren TI_ADPLL_LJ_CLKDCOLDO, 13921330497STony Lindgren TI_ADPLL_LJ_CLKOUT, 14021330497STony Lindgren TI_ADPLL_LJ_CLKOUTLDO, 14121330497STony Lindgren }; 14221330497STony Lindgren 14321330497STony Lindgren struct ti_adpll_platform_data { 14421330497STony Lindgren const bool is_type_s; 14521330497STony Lindgren const int nr_max_inputs; 14621330497STony Lindgren const int nr_max_outputs; 14721330497STony Lindgren const int output_index; 14821330497STony Lindgren }; 14921330497STony Lindgren 15021330497STony Lindgren struct ti_adpll_clock { 15121330497STony Lindgren struct clk *clk; 15221330497STony Lindgren struct clk_lookup *cl; 15321330497STony Lindgren void (*unregister)(struct clk *clk); 15421330497STony Lindgren }; 15521330497STony Lindgren 15621330497STony Lindgren struct ti_adpll_dco_data { 15721330497STony Lindgren struct clk_hw hw; 15821330497STony Lindgren }; 15921330497STony Lindgren 16021330497STony Lindgren struct ti_adpll_clkout_data { 16121330497STony Lindgren struct ti_adpll_data *adpll; 16221330497STony Lindgren struct clk_gate gate; 16321330497STony Lindgren struct clk_hw hw; 16421330497STony Lindgren }; 16521330497STony Lindgren 16621330497STony Lindgren struct ti_adpll_data { 16721330497STony Lindgren struct device *dev; 16821330497STony Lindgren const struct ti_adpll_platform_data *c; 16921330497STony Lindgren struct device_node *np; 17021330497STony Lindgren unsigned long pa; 17121330497STony Lindgren void __iomem *iobase; 17221330497STony Lindgren void __iomem *regs; 17321330497STony Lindgren spinlock_t lock; /* For ADPLL shared register access */ 17421330497STony Lindgren const char *parent_names[MAX_ADPLL_INPUTS]; 17521330497STony Lindgren struct clk *parent_clocks[MAX_ADPLL_INPUTS]; 17621330497STony Lindgren struct ti_adpll_clock *clocks; 17721330497STony Lindgren struct clk_onecell_data outputs; 17821330497STony Lindgren struct ti_adpll_dco_data dco; 17921330497STony Lindgren }; 18021330497STony Lindgren 18121330497STony Lindgren static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d, 18221330497STony Lindgren int output_index, 18321330497STony Lindgren const char *postfix) 18421330497STony Lindgren { 18521330497STony Lindgren const char *name; 18621330497STony Lindgren int err; 18721330497STony Lindgren 18821330497STony Lindgren if (output_index >= 0) { 18921330497STony Lindgren err = of_property_read_string_index(d->np, 19021330497STony Lindgren "clock-output-names", 19121330497STony Lindgren output_index, 19221330497STony Lindgren &name); 19321330497STony Lindgren if (err) 19421330497STony Lindgren return NULL; 19521330497STony Lindgren } else { 19621330497STony Lindgren const char *base_name = "adpll"; 19721330497STony Lindgren char *buf; 19821330497STony Lindgren 19921330497STony Lindgren buf = devm_kzalloc(d->dev, 8 + 1 + strlen(base_name) + 1 + 20021330497STony Lindgren strlen(postfix), GFP_KERNEL); 20121330497STony Lindgren if (!buf) 20221330497STony Lindgren return NULL; 20321330497STony Lindgren sprintf(buf, "%08lx.%s.%s", d->pa, base_name, postfix); 20421330497STony Lindgren name = buf; 20521330497STony Lindgren } 20621330497STony Lindgren 20721330497STony Lindgren return name; 20821330497STony Lindgren } 20921330497STony Lindgren 21021330497STony Lindgren #define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */ 21121330497STony Lindgren 21221330497STony Lindgren static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, 21321330497STony Lindgren int index, int output_index, const char *name, 21421330497STony Lindgren void (*unregister)(struct clk *clk)) 21521330497STony Lindgren { 21621330497STony Lindgren struct clk_lookup *cl; 21721330497STony Lindgren const char *postfix = NULL; 21821330497STony Lindgren char con_id[ADPLL_MAX_CON_ID]; 21921330497STony Lindgren 22021330497STony Lindgren d->clocks[index].clk = clock; 22121330497STony Lindgren d->clocks[index].unregister = unregister; 22221330497STony Lindgren 22321330497STony Lindgren /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */ 22421330497STony Lindgren postfix = strrchr(name, '.'); 225df2f8451SColin Ian King if (postfix && strlen(postfix) > 1) { 22621330497STony Lindgren if (strlen(postfix) > ADPLL_MAX_CON_ID) 22721330497STony Lindgren dev_warn(d->dev, "clock %s con_id lookup may fail\n", 22821330497STony Lindgren name); 22921330497STony Lindgren snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); 23021330497STony Lindgren cl = clkdev_create(clock, con_id, NULL); 23121330497STony Lindgren if (!cl) 23221330497STony Lindgren return -ENOMEM; 23321330497STony Lindgren d->clocks[index].cl = cl; 23421330497STony Lindgren } else { 23521330497STony Lindgren dev_warn(d->dev, "no con_id for clock %s\n", name); 23621330497STony Lindgren } 23721330497STony Lindgren 23821330497STony Lindgren if (output_index < 0) 23921330497STony Lindgren return 0; 24021330497STony Lindgren 24121330497STony Lindgren d->outputs.clks[output_index] = clock; 24221330497STony Lindgren d->outputs.clk_num++; 24321330497STony Lindgren 24421330497STony Lindgren return 0; 24521330497STony Lindgren } 24621330497STony Lindgren 24721330497STony Lindgren static int ti_adpll_init_divider(struct ti_adpll_data *d, 24821330497STony Lindgren enum ti_adpll_clocks index, 24921330497STony Lindgren int output_index, char *name, 25021330497STony Lindgren struct clk *parent_clock, 25121330497STony Lindgren void __iomem *reg, 25221330497STony Lindgren u8 shift, u8 width, 25321330497STony Lindgren u8 clk_divider_flags) 25421330497STony Lindgren { 25521330497STony Lindgren const char *child_name; 25621330497STony Lindgren const char *parent_name; 25721330497STony Lindgren struct clk *clock; 25821330497STony Lindgren 25921330497STony Lindgren child_name = ti_adpll_clk_get_name(d, output_index, name); 26021330497STony Lindgren if (!child_name) 26121330497STony Lindgren return -EINVAL; 26221330497STony Lindgren 26321330497STony Lindgren parent_name = __clk_get_name(parent_clock); 26421330497STony Lindgren clock = clk_register_divider(d->dev, child_name, parent_name, 0, 26521330497STony Lindgren reg, shift, width, clk_divider_flags, 26621330497STony Lindgren &d->lock); 26721330497STony Lindgren if (IS_ERR(clock)) { 26821330497STony Lindgren dev_err(d->dev, "failed to register divider %s: %li\n", 26921330497STony Lindgren name, PTR_ERR(clock)); 27021330497STony Lindgren return PTR_ERR(clock); 27121330497STony Lindgren } 27221330497STony Lindgren 27321330497STony Lindgren return ti_adpll_setup_clock(d, clock, index, output_index, child_name, 27421330497STony Lindgren clk_unregister_divider); 27521330497STony Lindgren } 27621330497STony Lindgren 27721330497STony Lindgren static int ti_adpll_init_mux(struct ti_adpll_data *d, 27821330497STony Lindgren enum ti_adpll_clocks index, 27921330497STony Lindgren char *name, struct clk *clk0, 28021330497STony Lindgren struct clk *clk1, 28121330497STony Lindgren void __iomem *reg, 28221330497STony Lindgren u8 shift) 28321330497STony Lindgren { 28421330497STony Lindgren const char *child_name; 28521330497STony Lindgren const char *parents[2]; 28621330497STony Lindgren struct clk *clock; 28721330497STony Lindgren 28821330497STony Lindgren child_name = ti_adpll_clk_get_name(d, -ENODEV, name); 28921330497STony Lindgren if (!child_name) 29021330497STony Lindgren return -ENOMEM; 29121330497STony Lindgren parents[0] = __clk_get_name(clk0); 29221330497STony Lindgren parents[1] = __clk_get_name(clk1); 29321330497STony Lindgren clock = clk_register_mux(d->dev, child_name, parents, 2, 0, 29421330497STony Lindgren reg, shift, 1, 0, &d->lock); 29521330497STony Lindgren if (IS_ERR(clock)) { 29621330497STony Lindgren dev_err(d->dev, "failed to register mux %s: %li\n", 29721330497STony Lindgren name, PTR_ERR(clock)); 29821330497STony Lindgren return PTR_ERR(clock); 29921330497STony Lindgren } 30021330497STony Lindgren 30121330497STony Lindgren return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, 30221330497STony Lindgren clk_unregister_mux); 30321330497STony Lindgren } 30421330497STony Lindgren 30521330497STony Lindgren static int ti_adpll_init_gate(struct ti_adpll_data *d, 30621330497STony Lindgren enum ti_adpll_clocks index, 30721330497STony Lindgren int output_index, char *name, 30821330497STony Lindgren struct clk *parent_clock, 30921330497STony Lindgren void __iomem *reg, 31021330497STony Lindgren u8 bit_idx, 31121330497STony Lindgren u8 clk_gate_flags) 31221330497STony Lindgren { 31321330497STony Lindgren const char *child_name; 31421330497STony Lindgren const char *parent_name; 31521330497STony Lindgren struct clk *clock; 31621330497STony Lindgren 31721330497STony Lindgren child_name = ti_adpll_clk_get_name(d, output_index, name); 31821330497STony Lindgren if (!child_name) 31921330497STony Lindgren return -EINVAL; 32021330497STony Lindgren 32121330497STony Lindgren parent_name = __clk_get_name(parent_clock); 32221330497STony Lindgren clock = clk_register_gate(d->dev, child_name, parent_name, 0, 32321330497STony Lindgren reg, bit_idx, clk_gate_flags, 32421330497STony Lindgren &d->lock); 32521330497STony Lindgren if (IS_ERR(clock)) { 32621330497STony Lindgren dev_err(d->dev, "failed to register gate %s: %li\n", 32721330497STony Lindgren name, PTR_ERR(clock)); 32821330497STony Lindgren return PTR_ERR(clock); 32921330497STony Lindgren } 33021330497STony Lindgren 33121330497STony Lindgren return ti_adpll_setup_clock(d, clock, index, output_index, child_name, 33221330497STony Lindgren clk_unregister_gate); 33321330497STony Lindgren } 33421330497STony Lindgren 33521330497STony Lindgren static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d, 33621330497STony Lindgren enum ti_adpll_clocks index, 33721330497STony Lindgren char *name, 33821330497STony Lindgren struct clk *parent_clock, 33921330497STony Lindgren unsigned int mult, 34021330497STony Lindgren unsigned int div) 34121330497STony Lindgren { 34221330497STony Lindgren const char *child_name; 34321330497STony Lindgren const char *parent_name; 34421330497STony Lindgren struct clk *clock; 34521330497STony Lindgren 34621330497STony Lindgren child_name = ti_adpll_clk_get_name(d, -ENODEV, name); 34721330497STony Lindgren if (!child_name) 34821330497STony Lindgren return -ENOMEM; 34921330497STony Lindgren 35021330497STony Lindgren parent_name = __clk_get_name(parent_clock); 35121330497STony Lindgren clock = clk_register_fixed_factor(d->dev, child_name, parent_name, 35221330497STony Lindgren 0, mult, div); 35321330497STony Lindgren if (IS_ERR(clock)) 35421330497STony Lindgren return PTR_ERR(clock); 35521330497STony Lindgren 35621330497STony Lindgren return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, 35721330497STony Lindgren clk_unregister); 35821330497STony Lindgren } 35921330497STony Lindgren 36021330497STony Lindgren static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d) 36121330497STony Lindgren { 36221330497STony Lindgren unsigned long flags; 36321330497STony Lindgren u32 v; 36421330497STony Lindgren 36521330497STony Lindgren spin_lock_irqsave(&d->lock, flags); 36621330497STony Lindgren v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); 36721330497STony Lindgren v |= BIT(ADPLL_CLKCTRL_IDLE); 36821330497STony Lindgren writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); 36921330497STony Lindgren spin_unlock_irqrestore(&d->lock, flags); 37021330497STony Lindgren } 37121330497STony Lindgren 37221330497STony Lindgren static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d) 37321330497STony Lindgren { 37421330497STony Lindgren unsigned long flags; 37521330497STony Lindgren u32 v; 37621330497STony Lindgren 37721330497STony Lindgren spin_lock_irqsave(&d->lock, flags); 37821330497STony Lindgren v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); 37921330497STony Lindgren v &= ~BIT(ADPLL_CLKCTRL_IDLE); 38021330497STony Lindgren writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); 38121330497STony Lindgren spin_unlock_irqrestore(&d->lock, flags); 38221330497STony Lindgren } 38321330497STony Lindgren 38421330497STony Lindgren static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d) 38521330497STony Lindgren { 38621330497STony Lindgren u32 v; 38721330497STony Lindgren 38821330497STony Lindgren v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); 38921330497STony Lindgren 39021330497STony Lindgren return v & BIT(ADPLL_STATUS_BYPASS); 39121330497STony Lindgren } 39221330497STony Lindgren 39321330497STony Lindgren /* 39421330497STony Lindgren * Locked and bypass are not actually mutually exclusive: if you only care 39521330497STony Lindgren * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling 39621330497STony Lindgren * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock. 39721330497STony Lindgren */ 39821330497STony Lindgren static bool ti_adpll_is_locked(struct ti_adpll_data *d) 39921330497STony Lindgren { 40021330497STony Lindgren u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); 40121330497STony Lindgren 40221330497STony Lindgren return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK; 40321330497STony Lindgren } 40421330497STony Lindgren 40521330497STony Lindgren static int ti_adpll_wait_lock(struct ti_adpll_data *d) 40621330497STony Lindgren { 40721330497STony Lindgren int retries = ADPLL_MAX_RETRIES; 40821330497STony Lindgren 40921330497STony Lindgren do { 41021330497STony Lindgren if (ti_adpll_is_locked(d)) 41121330497STony Lindgren return 0; 41221330497STony Lindgren usleep_range(200, 300); 41321330497STony Lindgren } while (retries--); 41421330497STony Lindgren 41521330497STony Lindgren dev_err(d->dev, "pll failed to lock\n"); 41621330497STony Lindgren return -ETIMEDOUT; 41721330497STony Lindgren } 41821330497STony Lindgren 41921330497STony Lindgren static int ti_adpll_prepare(struct clk_hw *hw) 42021330497STony Lindgren { 42121330497STony Lindgren struct ti_adpll_dco_data *dco = to_dco(hw); 42221330497STony Lindgren struct ti_adpll_data *d = to_adpll(dco); 42321330497STony Lindgren 42421330497STony Lindgren ti_adpll_clear_idle_bypass(d); 42521330497STony Lindgren ti_adpll_wait_lock(d); 42621330497STony Lindgren 42721330497STony Lindgren return 0; 42821330497STony Lindgren } 42921330497STony Lindgren 43021330497STony Lindgren static void ti_adpll_unprepare(struct clk_hw *hw) 43121330497STony Lindgren { 43221330497STony Lindgren struct ti_adpll_dco_data *dco = to_dco(hw); 43321330497STony Lindgren struct ti_adpll_data *d = to_adpll(dco); 43421330497STony Lindgren 43521330497STony Lindgren ti_adpll_set_idle_bypass(d); 43621330497STony Lindgren } 43721330497STony Lindgren 43821330497STony Lindgren static int ti_adpll_is_prepared(struct clk_hw *hw) 43921330497STony Lindgren { 44021330497STony Lindgren struct ti_adpll_dco_data *dco = to_dco(hw); 44121330497STony Lindgren struct ti_adpll_data *d = to_adpll(dco); 44221330497STony Lindgren 44321330497STony Lindgren return ti_adpll_is_locked(d); 44421330497STony Lindgren } 44521330497STony Lindgren 44621330497STony Lindgren /* 44721330497STony Lindgren * Note that the DCO clock is never subject to bypass: if the PLL is off, 44821330497STony Lindgren * dcoclk is low. 44921330497STony Lindgren */ 45021330497STony Lindgren static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw, 45121330497STony Lindgren unsigned long parent_rate) 45221330497STony Lindgren { 45321330497STony Lindgren struct ti_adpll_dco_data *dco = to_dco(hw); 45421330497STony Lindgren struct ti_adpll_data *d = to_adpll(dco); 45521330497STony Lindgren u32 frac_m, divider, v; 45621330497STony Lindgren u64 rate; 45721330497STony Lindgren unsigned long flags; 45821330497STony Lindgren 45921330497STony Lindgren if (ti_adpll_clock_is_bypass(d)) 46021330497STony Lindgren return 0; 46121330497STony Lindgren 46221330497STony Lindgren spin_lock_irqsave(&d->lock, flags); 46321330497STony Lindgren frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET); 46421330497STony Lindgren frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK; 4658a8b6eb7SStephen Boyd rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18; 46621330497STony Lindgren rate += frac_m; 46721330497STony Lindgren rate *= parent_rate; 46821330497STony Lindgren divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18; 46921330497STony Lindgren spin_unlock_irqrestore(&d->lock, flags); 47021330497STony Lindgren 47121330497STony Lindgren do_div(rate, divider); 47221330497STony Lindgren 47321330497STony Lindgren if (d->c->is_type_s) { 47421330497STony Lindgren v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); 47521330497STony Lindgren if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S)) 47621330497STony Lindgren rate *= 4; 47721330497STony Lindgren rate *= 2; 47821330497STony Lindgren } 47921330497STony Lindgren 48021330497STony Lindgren return rate; 48121330497STony Lindgren } 48221330497STony Lindgren 48321330497STony Lindgren /* PLL parent is always clkinp, bypass only affects the children */ 48421330497STony Lindgren static u8 ti_adpll_get_parent(struct clk_hw *hw) 48521330497STony Lindgren { 48621330497STony Lindgren return 0; 48721330497STony Lindgren } 48821330497STony Lindgren 4897cc566a8SBhumika Goyal static const struct clk_ops ti_adpll_ops = { 49021330497STony Lindgren .prepare = ti_adpll_prepare, 49121330497STony Lindgren .unprepare = ti_adpll_unprepare, 49221330497STony Lindgren .is_prepared = ti_adpll_is_prepared, 49321330497STony Lindgren .recalc_rate = ti_adpll_recalc_rate, 49421330497STony Lindgren .get_parent = ti_adpll_get_parent, 49521330497STony Lindgren }; 49621330497STony Lindgren 49721330497STony Lindgren static int ti_adpll_init_dco(struct ti_adpll_data *d) 49821330497STony Lindgren { 49921330497STony Lindgren struct clk_init_data init; 50021330497STony Lindgren struct clk *clock; 50121330497STony Lindgren const char *postfix; 50221330497STony Lindgren int width, err; 50321330497STony Lindgren 504a86854d0SKees Cook d->outputs.clks = devm_kcalloc(d->dev, 50521330497STony Lindgren MAX_ADPLL_OUTPUTS, 506a86854d0SKees Cook sizeof(struct clk *), 50721330497STony Lindgren GFP_KERNEL); 50821330497STony Lindgren if (!d->outputs.clks) 50921330497STony Lindgren return -ENOMEM; 51021330497STony Lindgren 51121330497STony Lindgren if (d->c->output_index < 0) 51221330497STony Lindgren postfix = "dco"; 51321330497STony Lindgren else 51421330497STony Lindgren postfix = NULL; 51521330497STony Lindgren 51621330497STony Lindgren init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix); 51721330497STony Lindgren if (!init.name) 51821330497STony Lindgren return -EINVAL; 51921330497STony Lindgren 52021330497STony Lindgren init.parent_names = d->parent_names; 52121330497STony Lindgren init.num_parents = d->c->nr_max_inputs; 52221330497STony Lindgren init.ops = &ti_adpll_ops; 52321330497STony Lindgren init.flags = CLK_GET_RATE_NOCACHE; 52421330497STony Lindgren d->dco.hw.init = &init; 52521330497STony Lindgren 52621330497STony Lindgren if (d->c->is_type_s) 52721330497STony Lindgren width = 5; 52821330497STony Lindgren else 52921330497STony Lindgren width = 4; 53021330497STony Lindgren 53121330497STony Lindgren /* Internal input clock divider N2 */ 53221330497STony Lindgren err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2", 53321330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINP], 53421330497STony Lindgren d->regs + ADPLL_MN2DIV_OFFSET, 53521330497STony Lindgren ADPLL_MN2DIV_N2, width, 0); 53621330497STony Lindgren if (err) 53721330497STony Lindgren return err; 53821330497STony Lindgren 53921330497STony Lindgren clock = devm_clk_register(d->dev, &d->dco.hw); 54021330497STony Lindgren if (IS_ERR(clock)) 54121330497STony Lindgren return PTR_ERR(clock); 54221330497STony Lindgren 54321330497STony Lindgren return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index, 54421330497STony Lindgren init.name, NULL); 54521330497STony Lindgren } 54621330497STony Lindgren 54721330497STony Lindgren static int ti_adpll_clkout_enable(struct clk_hw *hw) 54821330497STony Lindgren { 54921330497STony Lindgren struct ti_adpll_clkout_data *co = to_clkout(hw); 55021330497STony Lindgren struct clk_hw *gate_hw = &co->gate.hw; 55121330497STony Lindgren 55221330497STony Lindgren __clk_hw_set_clk(gate_hw, hw); 55321330497STony Lindgren 55421330497STony Lindgren return clk_gate_ops.enable(gate_hw); 55521330497STony Lindgren } 55621330497STony Lindgren 55721330497STony Lindgren static void ti_adpll_clkout_disable(struct clk_hw *hw) 55821330497STony Lindgren { 55921330497STony Lindgren struct ti_adpll_clkout_data *co = to_clkout(hw); 56021330497STony Lindgren struct clk_hw *gate_hw = &co->gate.hw; 56121330497STony Lindgren 56221330497STony Lindgren __clk_hw_set_clk(gate_hw, hw); 56321330497STony Lindgren clk_gate_ops.disable(gate_hw); 56421330497STony Lindgren } 56521330497STony Lindgren 56621330497STony Lindgren static int ti_adpll_clkout_is_enabled(struct clk_hw *hw) 56721330497STony Lindgren { 56821330497STony Lindgren struct ti_adpll_clkout_data *co = to_clkout(hw); 56921330497STony Lindgren struct clk_hw *gate_hw = &co->gate.hw; 57021330497STony Lindgren 57121330497STony Lindgren __clk_hw_set_clk(gate_hw, hw); 57221330497STony Lindgren 57321330497STony Lindgren return clk_gate_ops.is_enabled(gate_hw); 57421330497STony Lindgren } 57521330497STony Lindgren 57621330497STony Lindgren /* Setting PLL bypass puts clkout and clkoutx2 into bypass */ 57721330497STony Lindgren static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw) 57821330497STony Lindgren { 57921330497STony Lindgren struct ti_adpll_clkout_data *co = to_clkout(hw); 58021330497STony Lindgren struct ti_adpll_data *d = co->adpll; 58121330497STony Lindgren 58221330497STony Lindgren return ti_adpll_clock_is_bypass(d); 58321330497STony Lindgren } 58421330497STony Lindgren 58521330497STony Lindgren static int ti_adpll_init_clkout(struct ti_adpll_data *d, 58621330497STony Lindgren enum ti_adpll_clocks index, 58721330497STony Lindgren int output_index, int gate_bit, 58821330497STony Lindgren char *name, struct clk *clk0, 58921330497STony Lindgren struct clk *clk1) 59021330497STony Lindgren { 59121330497STony Lindgren struct ti_adpll_clkout_data *co; 59221330497STony Lindgren struct clk_init_data init; 59321330497STony Lindgren struct clk_ops *ops; 59421330497STony Lindgren const char *parent_names[2]; 59521330497STony Lindgren const char *child_name; 59621330497STony Lindgren struct clk *clock; 59721330497STony Lindgren int err; 59821330497STony Lindgren 59921330497STony Lindgren co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL); 60021330497STony Lindgren if (!co) 60121330497STony Lindgren return -ENOMEM; 60221330497STony Lindgren co->adpll = d; 60321330497STony Lindgren 60421330497STony Lindgren err = of_property_read_string_index(d->np, 60521330497STony Lindgren "clock-output-names", 60621330497STony Lindgren output_index, 60721330497STony Lindgren &child_name); 60821330497STony Lindgren if (err) 60921330497STony Lindgren return err; 61021330497STony Lindgren 61121330497STony Lindgren ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL); 61221330497STony Lindgren if (!ops) 61321330497STony Lindgren return -ENOMEM; 61421330497STony Lindgren 61521330497STony Lindgren init.name = child_name; 61621330497STony Lindgren init.ops = ops; 61721330497STony Lindgren init.flags = CLK_IS_BASIC; 61821330497STony Lindgren co->hw.init = &init; 61921330497STony Lindgren parent_names[0] = __clk_get_name(clk0); 62021330497STony Lindgren parent_names[1] = __clk_get_name(clk1); 62121330497STony Lindgren init.parent_names = parent_names; 62221330497STony Lindgren init.num_parents = 2; 62321330497STony Lindgren 62421330497STony Lindgren ops->get_parent = ti_adpll_clkout_get_parent; 62521330497STony Lindgren ops->determine_rate = __clk_mux_determine_rate; 62621330497STony Lindgren if (gate_bit) { 62721330497STony Lindgren co->gate.lock = &d->lock; 62821330497STony Lindgren co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET; 62921330497STony Lindgren co->gate.bit_idx = gate_bit; 63021330497STony Lindgren ops->enable = ti_adpll_clkout_enable; 63121330497STony Lindgren ops->disable = ti_adpll_clkout_disable; 63221330497STony Lindgren ops->is_enabled = ti_adpll_clkout_is_enabled; 63321330497STony Lindgren } 63421330497STony Lindgren 63521330497STony Lindgren clock = devm_clk_register(d->dev, &co->hw); 63621330497STony Lindgren if (IS_ERR(clock)) { 63721330497STony Lindgren dev_err(d->dev, "failed to register output %s: %li\n", 63821330497STony Lindgren name, PTR_ERR(clock)); 63921330497STony Lindgren return PTR_ERR(clock); 64021330497STony Lindgren } 64121330497STony Lindgren 64221330497STony Lindgren return ti_adpll_setup_clock(d, clock, index, output_index, child_name, 64321330497STony Lindgren NULL); 64421330497STony Lindgren } 64521330497STony Lindgren 64621330497STony Lindgren static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d) 64721330497STony Lindgren { 64821330497STony Lindgren int err; 64921330497STony Lindgren 65021330497STony Lindgren if (!d->c->is_type_s) 65121330497STony Lindgren return 0; 65221330497STony Lindgren 65321330497STony Lindgren /* Internal mux, sources from divider N2 or clkinpulow */ 65421330497STony Lindgren err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass", 65521330497STony Lindgren d->clocks[TI_ADPLL_N2].clk, 65621330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINPULOW], 65721330497STony Lindgren d->regs + ADPLL_CLKCTRL_OFFSET, 65821330497STony Lindgren ADPLL_CLKCTRL_ULOWCLKEN); 65921330497STony Lindgren if (err) 66021330497STony Lindgren return err; 66121330497STony Lindgren 66221330497STony Lindgren /* Internal divider M2, sources DCO */ 66321330497STony Lindgren err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2", 66421330497STony Lindgren d->clocks[TI_ADPLL_DCO].clk, 66521330497STony Lindgren d->regs + ADPLL_M2NDIV_OFFSET, 66621330497STony Lindgren ADPLL_M2NDIV_M2, 66721330497STony Lindgren ADPLL_M2NDIV_M2_ADPLL_S_WIDTH, 66821330497STony Lindgren CLK_DIVIDER_ONE_BASED); 66921330497STony Lindgren if (err) 67021330497STony Lindgren return err; 67121330497STony Lindgren 67221330497STony Lindgren /* Internal fixed divider, after M2 before clkout */ 67321330497STony Lindgren err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2", 67421330497STony Lindgren d->clocks[TI_ADPLL_M2].clk, 67521330497STony Lindgren 1, 2); 67621330497STony Lindgren if (err) 67721330497STony Lindgren return err; 67821330497STony Lindgren 67921330497STony Lindgren /* Output clkout with a mux and gate, sources from div2 or bypass */ 68021330497STony Lindgren err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT, 68121330497STony Lindgren ADPLL_CLKCTRL_CLKOUTEN, "clkout", 68221330497STony Lindgren d->clocks[TI_ADPLL_DIV2].clk, 68321330497STony Lindgren d->clocks[TI_ADPLL_BYPASS].clk); 68421330497STony Lindgren if (err) 68521330497STony Lindgren return err; 68621330497STony Lindgren 68721330497STony Lindgren /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */ 68821330497STony Lindgren err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0, 68921330497STony Lindgren "clkout2", d->clocks[TI_ADPLL_M2].clk, 69021330497STony Lindgren d->clocks[TI_ADPLL_BYPASS].clk); 69121330497STony Lindgren if (err) 69221330497STony Lindgren return err; 69321330497STony Lindgren 69421330497STony Lindgren /* Internal mux, sources from DCO and clkinphif */ 69521330497STony Lindgren if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) { 69621330497STony Lindgren err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif", 69721330497STony Lindgren d->clocks[TI_ADPLL_DCO].clk, 69821330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINPHIF], 69921330497STony Lindgren d->regs + ADPLL_CLKCTRL_OFFSET, 70021330497STony Lindgren ADPLL_CLKINPHIFSEL_ADPLL_S); 70121330497STony Lindgren if (err) 70221330497STony Lindgren return err; 70321330497STony Lindgren } 70421330497STony Lindgren 70521330497STony Lindgren /* Output clkouthif with a divider M3, sources from hif */ 70621330497STony Lindgren err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3", 70721330497STony Lindgren d->clocks[TI_ADPLL_HIF].clk, 70821330497STony Lindgren d->regs + ADPLL_M3DIV_OFFSET, 70921330497STony Lindgren ADPLL_M3DIV_M3, 71021330497STony Lindgren ADPLL_M3DIV_M3_WIDTH, 71121330497STony Lindgren CLK_DIVIDER_ONE_BASED); 71221330497STony Lindgren if (err) 71321330497STony Lindgren return err; 71421330497STony Lindgren 71521330497STony Lindgren /* Output clock dcoclkldo is the DCO */ 71621330497STony Lindgren 71721330497STony Lindgren return 0; 71821330497STony Lindgren } 71921330497STony Lindgren 72021330497STony Lindgren static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d) 72121330497STony Lindgren { 72221330497STony Lindgren int err; 72321330497STony Lindgren 72421330497STony Lindgren if (d->c->is_type_s) 72521330497STony Lindgren return 0; 72621330497STony Lindgren 72721330497STony Lindgren /* Output clkdcoldo, gated output of DCO */ 72821330497STony Lindgren err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO, 72921330497STony Lindgren "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk, 73021330497STony Lindgren d->regs + ADPLL_CLKCTRL_OFFSET, 73121330497STony Lindgren ADPLL_CLKCTRL_CLKDCOLDOEN, 0); 73221330497STony Lindgren if (err) 73321330497STony Lindgren return err; 73421330497STony Lindgren 73521330497STony Lindgren /* Internal divider M2, sources from DCO */ 73621330497STony Lindgren err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, 73721330497STony Lindgren "m2", d->clocks[TI_ADPLL_DCO].clk, 73821330497STony Lindgren d->regs + ADPLL_M2NDIV_OFFSET, 73921330497STony Lindgren ADPLL_M2NDIV_M2, 74021330497STony Lindgren ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH, 74121330497STony Lindgren CLK_DIVIDER_ONE_BASED); 74221330497STony Lindgren if (err) 74321330497STony Lindgren return err; 74421330497STony Lindgren 74521330497STony Lindgren /* Output clkoutldo, gated output of M2 */ 74621330497STony Lindgren err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO, 74721330497STony Lindgren "clkoutldo", d->clocks[TI_ADPLL_M2].clk, 74821330497STony Lindgren d->regs + ADPLL_CLKCTRL_OFFSET, 74921330497STony Lindgren ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ, 75021330497STony Lindgren 0); 75121330497STony Lindgren if (err) 75221330497STony Lindgren return err; 75321330497STony Lindgren 75421330497STony Lindgren /* Internal mux, sources from divider N2 or clkinpulow */ 75521330497STony Lindgren err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass", 75621330497STony Lindgren d->clocks[TI_ADPLL_N2].clk, 75721330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINPULOW], 75821330497STony Lindgren d->regs + ADPLL_CLKCTRL_OFFSET, 75921330497STony Lindgren ADPLL_CLKCTRL_ULOWCLKEN); 76021330497STony Lindgren if (err) 76121330497STony Lindgren return err; 76221330497STony Lindgren 76321330497STony Lindgren /* Output clkout, sources M2 or bypass */ 76421330497STony Lindgren err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT, 76521330497STony Lindgren ADPLL_CLKCTRL_CLKOUTEN, "clkout", 76621330497STony Lindgren d->clocks[TI_ADPLL_M2].clk, 76721330497STony Lindgren d->clocks[TI_ADPLL_BYPASS].clk); 76821330497STony Lindgren if (err) 76921330497STony Lindgren return err; 77021330497STony Lindgren 77121330497STony Lindgren return 0; 77221330497STony Lindgren } 77321330497STony Lindgren 77421330497STony Lindgren static void ti_adpll_free_resources(struct ti_adpll_data *d) 77521330497STony Lindgren { 77621330497STony Lindgren int i; 77721330497STony Lindgren 77821330497STony Lindgren for (i = TI_ADPLL_M3; i >= 0; i--) { 77921330497STony Lindgren struct ti_adpll_clock *ac = &d->clocks[i]; 78021330497STony Lindgren 78121330497STony Lindgren if (!ac || IS_ERR_OR_NULL(ac->clk)) 78221330497STony Lindgren continue; 78321330497STony Lindgren if (ac->cl) 78421330497STony Lindgren clkdev_drop(ac->cl); 78521330497STony Lindgren if (ac->unregister) 78621330497STony Lindgren ac->unregister(ac->clk); 78721330497STony Lindgren } 78821330497STony Lindgren } 78921330497STony Lindgren 79021330497STony Lindgren /* MPU PLL manages the lock register for all PLLs */ 79121330497STony Lindgren static void ti_adpll_unlock_all(void __iomem *reg) 79221330497STony Lindgren { 79321330497STony Lindgren u32 v; 79421330497STony Lindgren 79521330497STony Lindgren v = readl_relaxed(reg); 79621330497STony Lindgren if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED) 79721330497STony Lindgren writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg); 79821330497STony Lindgren } 79921330497STony Lindgren 80021330497STony Lindgren static int ti_adpll_init_registers(struct ti_adpll_data *d) 80121330497STony Lindgren { 80221330497STony Lindgren int register_offset = 0; 80321330497STony Lindgren 80421330497STony Lindgren if (d->c->is_type_s) { 80521330497STony Lindgren register_offset = 8; 80621330497STony Lindgren ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET); 80721330497STony Lindgren } 80821330497STony Lindgren 80921330497STony Lindgren d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET; 81021330497STony Lindgren 81121330497STony Lindgren return 0; 81221330497STony Lindgren } 81321330497STony Lindgren 81421330497STony Lindgren static int ti_adpll_init_inputs(struct ti_adpll_data *d) 81521330497STony Lindgren { 81621330497STony Lindgren const char *error = "need at least %i inputs"; 81721330497STony Lindgren struct clk *clock; 81821330497STony Lindgren int nr_inputs; 81921330497STony Lindgren 82021330497STony Lindgren nr_inputs = of_clk_get_parent_count(d->np); 82121330497STony Lindgren if (nr_inputs < d->c->nr_max_inputs) { 82221330497STony Lindgren dev_err(d->dev, error, nr_inputs); 82321330497STony Lindgren return -EINVAL; 82421330497STony Lindgren } 82521330497STony Lindgren of_clk_parent_fill(d->np, d->parent_names, nr_inputs); 82621330497STony Lindgren 82721330497STony Lindgren clock = devm_clk_get(d->dev, d->parent_names[0]); 82821330497STony Lindgren if (IS_ERR(clock)) { 82921330497STony Lindgren dev_err(d->dev, "could not get clkinp\n"); 83021330497STony Lindgren return PTR_ERR(clock); 83121330497STony Lindgren } 83221330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINP] = clock; 83321330497STony Lindgren 83421330497STony Lindgren clock = devm_clk_get(d->dev, d->parent_names[1]); 83521330497STony Lindgren if (IS_ERR(clock)) { 83621330497STony Lindgren dev_err(d->dev, "could not get clkinpulow clock\n"); 83721330497STony Lindgren return PTR_ERR(clock); 83821330497STony Lindgren } 83921330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock; 84021330497STony Lindgren 84121330497STony Lindgren if (d->c->is_type_s) { 84221330497STony Lindgren clock = devm_clk_get(d->dev, d->parent_names[2]); 84321330497STony Lindgren if (IS_ERR(clock)) { 84421330497STony Lindgren dev_err(d->dev, "could not get clkinphif clock\n"); 84521330497STony Lindgren return PTR_ERR(clock); 84621330497STony Lindgren } 84721330497STony Lindgren d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock; 84821330497STony Lindgren } 84921330497STony Lindgren 85021330497STony Lindgren return 0; 85121330497STony Lindgren } 85221330497STony Lindgren 85321330497STony Lindgren static const struct ti_adpll_platform_data ti_adpll_type_s = { 85421330497STony Lindgren .is_type_s = true, 85521330497STony Lindgren .nr_max_inputs = MAX_ADPLL_INPUTS, 85621330497STony Lindgren .nr_max_outputs = MAX_ADPLL_OUTPUTS, 85721330497STony Lindgren .output_index = TI_ADPLL_S_DCOCLKLDO, 85821330497STony Lindgren }; 85921330497STony Lindgren 86021330497STony Lindgren static const struct ti_adpll_platform_data ti_adpll_type_lj = { 86121330497STony Lindgren .is_type_s = false, 86221330497STony Lindgren .nr_max_inputs = MAX_ADPLL_INPUTS - 1, 86321330497STony Lindgren .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1, 86421330497STony Lindgren .output_index = -EINVAL, 86521330497STony Lindgren }; 86621330497STony Lindgren 86721330497STony Lindgren static const struct of_device_id ti_adpll_match[] = { 86821330497STony Lindgren { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s }, 86921330497STony Lindgren { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj }, 87021330497STony Lindgren {}, 87121330497STony Lindgren }; 87221330497STony Lindgren MODULE_DEVICE_TABLE(of, ti_adpll_match); 87321330497STony Lindgren 87421330497STony Lindgren static int ti_adpll_probe(struct platform_device *pdev) 87521330497STony Lindgren { 87621330497STony Lindgren struct device_node *node = pdev->dev.of_node; 87721330497STony Lindgren struct device *dev = &pdev->dev; 87821330497STony Lindgren const struct of_device_id *match; 87921330497STony Lindgren const struct ti_adpll_platform_data *pdata; 88021330497STony Lindgren struct ti_adpll_data *d; 88121330497STony Lindgren struct resource *res; 88221330497STony Lindgren int err; 88321330497STony Lindgren 88421330497STony Lindgren match = of_match_device(ti_adpll_match, dev); 88521330497STony Lindgren if (match) 88621330497STony Lindgren pdata = match->data; 88721330497STony Lindgren else 88821330497STony Lindgren return -ENODEV; 88921330497STony Lindgren 89021330497STony Lindgren d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 89121330497STony Lindgren if (!d) 89221330497STony Lindgren return -ENOMEM; 89321330497STony Lindgren d->dev = dev; 89421330497STony Lindgren d->np = node; 89521330497STony Lindgren d->c = pdata; 89621330497STony Lindgren dev_set_drvdata(d->dev, d); 89721330497STony Lindgren spin_lock_init(&d->lock); 89821330497STony Lindgren 89921330497STony Lindgren res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 90021330497STony Lindgren if (!res) 90121330497STony Lindgren return -ENODEV; 90221330497STony Lindgren d->pa = res->start; 90321330497STony Lindgren 90421330497STony Lindgren d->iobase = devm_ioremap_resource(dev, res); 90521330497STony Lindgren if (IS_ERR(d->iobase)) { 90621330497STony Lindgren dev_err(dev, "could not get IO base: %li\n", 90721330497STony Lindgren PTR_ERR(d->iobase)); 90821330497STony Lindgren return PTR_ERR(d->iobase); 90921330497STony Lindgren } 91021330497STony Lindgren 91121330497STony Lindgren err = ti_adpll_init_registers(d); 91221330497STony Lindgren if (err) 91321330497STony Lindgren return err; 91421330497STony Lindgren 91521330497STony Lindgren err = ti_adpll_init_inputs(d); 91621330497STony Lindgren if (err) 91721330497STony Lindgren return err; 91821330497STony Lindgren 919a86854d0SKees Cook d->clocks = devm_kcalloc(d->dev, 92021330497STony Lindgren TI_ADPLL_NR_CLOCKS, 921a86854d0SKees Cook sizeof(struct ti_adpll_clock), 92221330497STony Lindgren GFP_KERNEL); 92321330497STony Lindgren if (!d->clocks) 9248a8b6eb7SStephen Boyd return -ENOMEM; 92521330497STony Lindgren 92621330497STony Lindgren err = ti_adpll_init_dco(d); 92721330497STony Lindgren if (err) { 92821330497STony Lindgren dev_err(dev, "could not register dco: %i\n", err); 92921330497STony Lindgren goto free; 93021330497STony Lindgren } 93121330497STony Lindgren 93221330497STony Lindgren err = ti_adpll_init_children_adpll_s(d); 93321330497STony Lindgren if (err) 93421330497STony Lindgren goto free; 93521330497STony Lindgren err = ti_adpll_init_children_adpll_lj(d); 93621330497STony Lindgren if (err) 93721330497STony Lindgren goto free; 93821330497STony Lindgren 93921330497STony Lindgren err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs); 94021330497STony Lindgren if (err) 94121330497STony Lindgren goto free; 94221330497STony Lindgren 94321330497STony Lindgren return 0; 94421330497STony Lindgren 94521330497STony Lindgren free: 94621330497STony Lindgren WARN_ON(1); 94721330497STony Lindgren ti_adpll_free_resources(d); 94821330497STony Lindgren 94921330497STony Lindgren return err; 95021330497STony Lindgren } 95121330497STony Lindgren 95221330497STony Lindgren static int ti_adpll_remove(struct platform_device *pdev) 95321330497STony Lindgren { 95421330497STony Lindgren struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev); 95521330497STony Lindgren 95621330497STony Lindgren ti_adpll_free_resources(d); 95721330497STony Lindgren 95821330497STony Lindgren return 0; 95921330497STony Lindgren } 96021330497STony Lindgren 96121330497STony Lindgren static struct platform_driver ti_adpll_driver = { 96221330497STony Lindgren .driver = { 96321330497STony Lindgren .name = "ti-adpll", 96421330497STony Lindgren .of_match_table = ti_adpll_match, 96521330497STony Lindgren }, 96621330497STony Lindgren .probe = ti_adpll_probe, 96721330497STony Lindgren .remove = ti_adpll_remove, 96821330497STony Lindgren }; 96921330497STony Lindgren 97021330497STony Lindgren static int __init ti_adpll_init(void) 97121330497STony Lindgren { 97221330497STony Lindgren return platform_driver_register(&ti_adpll_driver); 97321330497STony Lindgren } 97421330497STony Lindgren core_initcall(ti_adpll_init); 97521330497STony Lindgren 97621330497STony Lindgren static void __exit ti_adpll_exit(void) 97721330497STony Lindgren { 97821330497STony Lindgren platform_driver_unregister(&ti_adpll_driver); 97921330497STony Lindgren } 98021330497STony Lindgren module_exit(ti_adpll_exit); 98121330497STony Lindgren 98221330497STony Lindgren MODULE_DESCRIPTION("Clock driver for dm814x ADPLL"); 98321330497STony Lindgren MODULE_ALIAS("platform:dm814-adpll-clock"); 98421330497STony Lindgren MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>"); 98521330497STony Lindgren MODULE_LICENSE("GPL v2"); 986