1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __TEGRA_CLK_H 18 #define __TEGRA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30 struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34 }; 35 36 #define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39 extern const struct clk_ops tegra_clk_sync_source_ops; 40 struct clk *tegra_clk_register_sync_source(const char *name, 41 unsigned long fixed_rate, unsigned long max_rate); 42 43 /** 44 * struct tegra_clk_frac_div - fractional divider clock 45 * 46 * @hw: handle between common and hardware-specific interfaces 47 * @reg: register containing divider 48 * @flags: hardware-specific flags 49 * @shift: shift to the divider bit field 50 * @width: width of the divider bit field 51 * @frac_width: width of the fractional bit field 52 * @lock: register lock 53 * 54 * Flags: 55 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 56 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 57 * flag indicates that this divider is for fixed rate PLL. 58 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 59 * fraction bit is set. This flags indicates to calculate divider for which 60 * fracton bit will be zero. 61 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 62 * set when divider value is not 0. This flags indicates that the divider 63 * is for UART module. 64 */ 65 struct tegra_clk_frac_div { 66 struct clk_hw hw; 67 void __iomem *reg; 68 u8 flags; 69 u8 shift; 70 u8 width; 71 u8 frac_width; 72 spinlock_t *lock; 73 }; 74 75 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 76 77 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 78 #define TEGRA_DIVIDER_FIXED BIT(1) 79 #define TEGRA_DIVIDER_INT BIT(2) 80 #define TEGRA_DIVIDER_UART BIT(3) 81 82 extern const struct clk_ops tegra_clk_frac_div_ops; 83 struct clk *tegra_clk_register_divider(const char *name, 84 const char *parent_name, void __iomem *reg, 85 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 86 u8 frac_width, spinlock_t *lock); 87 88 /* 89 * Tegra PLL: 90 * 91 * In general, there are 3 requirements for each PLL 92 * that SW needs to be comply with. 93 * (1) Input frequency range (REF). 94 * (2) Comparison frequency range (CF). CF = REF/DIVM. 95 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 96 * 97 * The final PLL output frequency (FO) = VCO >> DIVP. 98 */ 99 100 /** 101 * struct tegra_clk_pll_freq_table - PLL frequecy table 102 * 103 * @input_rate: input rate from source 104 * @output_rate: output rate from PLL for the input rate 105 * @n: feedback divider 106 * @m: input divider 107 * @p: post divider 108 * @cpcon: charge pump current 109 */ 110 struct tegra_clk_pll_freq_table { 111 unsigned long input_rate; 112 unsigned long output_rate; 113 u16 n; 114 u16 m; 115 u8 p; 116 u8 cpcon; 117 }; 118 119 /** 120 * struct pdiv_map - map post divider to hw value 121 * 122 * @pdiv: post divider 123 * @hw_val: value to be written to the PLL hw 124 */ 125 struct pdiv_map { 126 u8 pdiv; 127 u8 hw_val; 128 }; 129 130 /** 131 * struct clk_pll_params - PLL parameters 132 * 133 * @input_min: Minimum input frequency 134 * @input_max: Maximum input frequency 135 * @cf_min: Minimum comparison frequency 136 * @cf_max: Maximum comparison frequency 137 * @vco_min: Minimum VCO frequency 138 * @vco_max: Maximum VCO frequency 139 * @base_reg: PLL base reg offset 140 * @misc_reg: PLL misc reg offset 141 * @lock_reg: PLL lock reg offset 142 * @lock_bit_idx: Bit index for PLL lock status 143 * @lock_enable_bit_idx: Bit index to enable PLL lock 144 * @lock_delay: Delay in us if PLL lock is not used 145 */ 146 struct tegra_clk_pll_params { 147 unsigned long input_min; 148 unsigned long input_max; 149 unsigned long cf_min; 150 unsigned long cf_max; 151 unsigned long vco_min; 152 unsigned long vco_max; 153 154 u32 base_reg; 155 u32 misc_reg; 156 u32 lock_reg; 157 u32 lock_mask; 158 u32 lock_enable_bit_idx; 159 u32 iddq_reg; 160 u32 iddq_bit_idx; 161 u32 aux_reg; 162 u32 dyn_ramp_reg; 163 u32 ext_misc_reg[3]; 164 int stepa_shift; 165 int stepb_shift; 166 int lock_delay; 167 int max_p; 168 struct pdiv_map *pdiv_tohw; 169 }; 170 171 /** 172 * struct tegra_clk_pll - Tegra PLL clock 173 * 174 * @hw: handle between common and hardware-specifix interfaces 175 * @clk_base: address of CAR controller 176 * @pmc: address of PMC, required to read override bits 177 * @freq_table: array of frequencies supported by PLL 178 * @params: PLL parameters 179 * @flags: PLL flags 180 * @fixed_rate: PLL rate if it is fixed 181 * @lock: register lock 182 * @divn_shift: shift to the feedback divider bit field 183 * @divn_width: width of the feedback divider bit field 184 * @divm_shift: shift to the input divider bit field 185 * @divm_width: width of the input divider bit field 186 * @divp_shift: shift to the post divider bit field 187 * @divp_width: width of the post divider bit field 188 * 189 * Flags: 190 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 191 * PLL locking. If not set it will use lock_delay value to wait. 192 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 193 * to be programmed to change output frequency of the PLL. 194 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 195 * to be programmed to change output frequency of the PLL. 196 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 197 * to be programmed to change output frequency of the PLL. 198 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 199 * that it is PLLU and invert post divider value. 200 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 201 * flag indicates that it is PLLM and use override settings. 202 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 203 * of some plls. 204 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 205 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 206 * base register. 207 * TEGRA_PLL_BYPASS - PLL has bypass bit 208 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 209 */ 210 struct tegra_clk_pll { 211 struct clk_hw hw; 212 void __iomem *clk_base; 213 void __iomem *pmc; 214 u32 flags; 215 unsigned long fixed_rate; 216 spinlock_t *lock; 217 u8 divn_shift; 218 u8 divn_width; 219 u8 divm_shift; 220 u8 divm_width; 221 u8 divp_shift; 222 u8 divp_width; 223 struct tegra_clk_pll_freq_table *freq_table; 224 struct tegra_clk_pll_params *params; 225 }; 226 227 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 228 229 #define TEGRA_PLL_USE_LOCK BIT(0) 230 #define TEGRA_PLL_HAS_CPCON BIT(1) 231 #define TEGRA_PLL_SET_LFCON BIT(2) 232 #define TEGRA_PLL_SET_DCCON BIT(3) 233 #define TEGRA_PLLU BIT(4) 234 #define TEGRA_PLLM BIT(5) 235 #define TEGRA_PLL_FIXED BIT(6) 236 #define TEGRA_PLLE_CONFIGURE BIT(7) 237 #define TEGRA_PLL_LOCK_MISC BIT(8) 238 #define TEGRA_PLL_BYPASS BIT(9) 239 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 240 241 extern const struct clk_ops tegra_clk_pll_ops; 242 extern const struct clk_ops tegra_clk_plle_ops; 243 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 244 void __iomem *clk_base, void __iomem *pmc, 245 unsigned long flags, unsigned long fixed_rate, 246 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 247 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 248 249 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 250 void __iomem *clk_base, void __iomem *pmc, 251 unsigned long flags, unsigned long fixed_rate, 252 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 253 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 254 255 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 256 void __iomem *clk_base, void __iomem *pmc, 257 unsigned long flags, unsigned long fixed_rate, 258 struct tegra_clk_pll_params *pll_params, 259 u32 pll_flags, 260 struct tegra_clk_pll_freq_table *freq_table, 261 spinlock_t *lock); 262 263 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 264 void __iomem *clk_base, void __iomem *pmc, 265 unsigned long flags, unsigned long fixed_rate, 266 struct tegra_clk_pll_params *pll_params, 267 u32 pll_flags, 268 struct tegra_clk_pll_freq_table *freq_table, 269 spinlock_t *lock); 270 271 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 272 void __iomem *clk_base, void __iomem *pmc, 273 unsigned long flags, unsigned long fixed_rate, 274 struct tegra_clk_pll_params *pll_params, 275 u32 pll_flags, 276 struct tegra_clk_pll_freq_table *freq_table, 277 spinlock_t *lock); 278 279 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 280 void __iomem *clk_base, void __iomem *pmc, 281 unsigned long flags, unsigned long fixed_rate, 282 struct tegra_clk_pll_params *pll_params, 283 u32 pll_flags, 284 struct tegra_clk_pll_freq_table *freq_table, 285 spinlock_t *lock, unsigned long parent_rate); 286 287 struct clk *tegra_clk_register_plle_tegra114(const char *name, 288 const char *parent_name, 289 void __iomem *clk_base, unsigned long flags, 290 unsigned long fixed_rate, 291 struct tegra_clk_pll_params *pll_params, 292 struct tegra_clk_pll_freq_table *freq_table, 293 spinlock_t *lock); 294 295 /** 296 * struct tegra_clk_pll_out - PLL divider down clock 297 * 298 * @hw: handle between common and hardware-specific interfaces 299 * @reg: register containing the PLL divider 300 * @enb_bit_idx: bit to enable/disable PLL divider 301 * @rst_bit_idx: bit to reset PLL divider 302 * @lock: register lock 303 * @flags: hardware-specific flags 304 */ 305 struct tegra_clk_pll_out { 306 struct clk_hw hw; 307 void __iomem *reg; 308 u8 enb_bit_idx; 309 u8 rst_bit_idx; 310 spinlock_t *lock; 311 u8 flags; 312 }; 313 314 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 315 316 extern const struct clk_ops tegra_clk_pll_out_ops; 317 struct clk *tegra_clk_register_pll_out(const char *name, 318 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 319 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 320 spinlock_t *lock); 321 322 /** 323 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 324 * 325 * @enb_reg: read the enable status 326 * @enb_set_reg: write 1 to enable clock 327 * @enb_clr_reg: write 1 to disable clock 328 * @rst_reg: read the reset status 329 * @rst_set_reg: write 1 to assert the reset of peripheral 330 * @rst_clr_reg: write 1 to deassert the reset of peripheral 331 */ 332 struct tegra_clk_periph_regs { 333 u32 enb_reg; 334 u32 enb_set_reg; 335 u32 enb_clr_reg; 336 u32 rst_reg; 337 u32 rst_set_reg; 338 u32 rst_clr_reg; 339 }; 340 341 /** 342 * struct tegra_clk_periph_gate - peripheral gate clock 343 * 344 * @magic: magic number to validate type 345 * @hw: handle between common and hardware-specific interfaces 346 * @clk_base: address of CAR controller 347 * @regs: Registers to control the peripheral 348 * @flags: hardware-specific flags 349 * @clk_num: Clock number 350 * @enable_refcnt: array to maintain reference count of the clock 351 * 352 * Flags: 353 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 354 * for this module. 355 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 356 * after clock enable and driver for the module is responsible for 357 * doing reset. 358 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 359 * bus to flush the write operation in apb bus. This flag indicates 360 * that this peripheral is in apb bus. 361 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug 362 */ 363 struct tegra_clk_periph_gate { 364 u32 magic; 365 struct clk_hw hw; 366 void __iomem *clk_base; 367 u8 flags; 368 int clk_num; 369 int *enable_refcnt; 370 struct tegra_clk_periph_regs *regs; 371 }; 372 373 #define to_clk_periph_gate(_hw) \ 374 container_of(_hw, struct tegra_clk_periph_gate, hw) 375 376 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 377 378 #define TEGRA_PERIPH_NO_RESET BIT(0) 379 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 380 #define TEGRA_PERIPH_ON_APB BIT(2) 381 #define TEGRA_PERIPH_WAR_1005168 BIT(3) 382 383 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 384 extern const struct clk_ops tegra_clk_periph_gate_ops; 385 struct clk *tegra_clk_register_periph_gate(const char *name, 386 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 387 unsigned long flags, int clk_num, 388 struct tegra_clk_periph_regs *pregs, int *enable_refcnt); 389 390 /** 391 * struct clk-periph - peripheral clock 392 * 393 * @magic: magic number to validate type 394 * @hw: handle between common and hardware-specific interfaces 395 * @mux: mux clock 396 * @divider: divider clock 397 * @gate: gate clock 398 * @mux_ops: mux clock ops 399 * @div_ops: divider clock ops 400 * @gate_ops: gate clock ops 401 */ 402 struct tegra_clk_periph { 403 u32 magic; 404 struct clk_hw hw; 405 struct clk_mux mux; 406 struct tegra_clk_frac_div divider; 407 struct tegra_clk_periph_gate gate; 408 409 const struct clk_ops *mux_ops; 410 const struct clk_ops *div_ops; 411 const struct clk_ops *gate_ops; 412 }; 413 414 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 415 416 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 417 418 extern const struct clk_ops tegra_clk_periph_ops; 419 struct clk *tegra_clk_register_periph(const char *name, 420 const char **parent_names, int num_parents, 421 struct tegra_clk_periph *periph, void __iomem *clk_base, 422 u32 offset, unsigned long flags); 423 struct clk *tegra_clk_register_periph_nodiv(const char *name, 424 const char **parent_names, int num_parents, 425 struct tegra_clk_periph *periph, void __iomem *clk_base, 426 u32 offset); 427 428 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 429 _div_shift, _div_width, _div_frac_width, \ 430 _div_flags, _clk_num, _enb_refcnt, _regs, \ 431 _gate_flags, _table) \ 432 { \ 433 .mux = { \ 434 .flags = _mux_flags, \ 435 .shift = _mux_shift, \ 436 .mask = _mux_mask, \ 437 .table = _table, \ 438 }, \ 439 .divider = { \ 440 .flags = _div_flags, \ 441 .shift = _div_shift, \ 442 .width = _div_width, \ 443 .frac_width = _div_frac_width, \ 444 }, \ 445 .gate = { \ 446 .flags = _gate_flags, \ 447 .clk_num = _clk_num, \ 448 .enable_refcnt = _enb_refcnt, \ 449 .regs = _regs, \ 450 }, \ 451 .mux_ops = &clk_mux_ops, \ 452 .div_ops = &tegra_clk_frac_div_ops, \ 453 .gate_ops = &tegra_clk_periph_gate_ops, \ 454 } 455 456 struct tegra_periph_init_data { 457 const char *name; 458 int clk_id; 459 const char **parent_names; 460 int num_parents; 461 struct tegra_clk_periph periph; 462 u32 offset; 463 const char *con_id; 464 const char *dev_id; 465 unsigned long flags; 466 }; 467 468 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 469 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 470 _div_width, _div_frac_width, _div_flags, _regs, \ 471 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\ 472 _flags) \ 473 { \ 474 .name = _name, \ 475 .clk_id = _clk_id, \ 476 .parent_names = _parent_names, \ 477 .num_parents = ARRAY_SIZE(_parent_names), \ 478 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 479 _mux_flags, _div_shift, \ 480 _div_width, _div_frac_width, \ 481 _div_flags, _clk_num, \ 482 _enb_refcnt, _regs, \ 483 _gate_flags, _table), \ 484 .offset = _offset, \ 485 .con_id = _con_id, \ 486 .dev_id = _dev_id, \ 487 .flags = _flags \ 488 } 489 490 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 491 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 492 _div_width, _div_frac_width, _div_flags, _regs, \ 493 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 494 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 495 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 496 _div_shift, _div_width, _div_frac_width, _div_flags, \ 497 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 498 NULL, 0) 499 500 /** 501 * struct clk_super_mux - super clock 502 * 503 * @hw: handle between common and hardware-specific interfaces 504 * @reg: register controlling multiplexer 505 * @width: width of the multiplexer bit field 506 * @flags: hardware-specific flags 507 * @div2_index: bit controlling divide-by-2 508 * @pllx_index: PLLX index in the parent list 509 * @lock: register lock 510 * 511 * Flags: 512 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 513 * that this is LP cluster clock. 514 */ 515 struct tegra_clk_super_mux { 516 struct clk_hw hw; 517 void __iomem *reg; 518 u8 width; 519 u8 flags; 520 u8 div2_index; 521 u8 pllx_index; 522 spinlock_t *lock; 523 }; 524 525 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 526 527 #define TEGRA_DIVIDER_2 BIT(0) 528 529 extern const struct clk_ops tegra_clk_super_ops; 530 struct clk *tegra_clk_register_super_mux(const char *name, 531 const char **parent_names, u8 num_parents, 532 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 533 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 534 535 /** 536 * struct clk_init_tabel - clock initialization table 537 * @clk_id: clock id as mentioned in device tree bindings 538 * @parent_id: parent clock id as mentioned in device tree bindings 539 * @rate: rate to set 540 * @state: enable/disable 541 */ 542 struct tegra_clk_init_table { 543 unsigned int clk_id; 544 unsigned int parent_id; 545 unsigned long rate; 546 int state; 547 }; 548 549 /** 550 * struct clk_duplicate - duplicate clocks 551 * @clk_id: clock id as mentioned in device tree bindings 552 * @lookup: duplicate lookup entry for the clock 553 */ 554 struct tegra_clk_duplicate { 555 int clk_id; 556 struct clk_lookup lookup; 557 }; 558 559 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 560 { \ 561 .clk_id = _clk_id, \ 562 .lookup = { \ 563 .dev_id = _dev, \ 564 .con_id = _con, \ 565 }, \ 566 } 567 568 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 569 struct clk *clks[], int clk_max); 570 571 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 572 struct clk *clks[], int clk_max); 573 574 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 575 void tegra20_clock_init(struct device_node *np); 576 #else 577 static inline void tegra20_clock_init(struct device_node *np) {} 578 #endif /* CONFIG_ARCH_TEGRA_2x_SOC */ 579 580 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 581 void tegra30_clock_init(struct device_node *np); 582 #else 583 static inline void tegra30_clock_init(struct device_node *np) {} 584 #endif /* CONFIG_ARCH_TEGRA_3x_SOC */ 585 586 #ifdef CONFIG_ARCH_TEGRA_114_SOC 587 void tegra114_clock_init(struct device_node *np); 588 #else 589 static inline void tegra114_clock_init(struct device_node *np) {} 590 #endif /* CONFIG_ARCH_TEGRA114_SOC */ 591 592 typedef void (*tegra_clk_apply_init_table_func)(void); 593 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 594 595 #endif /* TEGRA_CLK_H */ 596