1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __TEGRA_CLK_H 7 #define __TEGRA_CLK_H 8 9 #include <linux/clk-provider.h> 10 #include <linux/clkdev.h> 11 #include <linux/delay.h> 12 13 #define CLK_OUT_ENB_L 0x010 14 #define CLK_OUT_ENB_H 0x014 15 #define CLK_OUT_ENB_U 0x018 16 #define CLK_OUT_ENB_V 0x360 17 #define CLK_OUT_ENB_W 0x364 18 #define CLK_OUT_ENB_X 0x280 19 #define CLK_OUT_ENB_Y 0x298 20 #define CLK_ENB_PLLP_OUT_CPU BIT(31) 21 #define CLK_OUT_ENB_SET_L 0x320 22 #define CLK_OUT_ENB_CLR_L 0x324 23 #define CLK_OUT_ENB_SET_H 0x328 24 #define CLK_OUT_ENB_CLR_H 0x32c 25 #define CLK_OUT_ENB_SET_U 0x330 26 #define CLK_OUT_ENB_CLR_U 0x334 27 #define CLK_OUT_ENB_SET_V 0x440 28 #define CLK_OUT_ENB_CLR_V 0x444 29 #define CLK_OUT_ENB_SET_W 0x448 30 #define CLK_OUT_ENB_CLR_W 0x44c 31 #define CLK_OUT_ENB_SET_X 0x284 32 #define CLK_OUT_ENB_CLR_X 0x288 33 #define CLK_OUT_ENB_SET_Y 0x29c 34 #define CLK_OUT_ENB_CLR_Y 0x2a0 35 36 #define RST_DEVICES_L 0x004 37 #define RST_DEVICES_H 0x008 38 #define RST_DEVICES_U 0x00C 39 #define RST_DEVICES_V 0x358 40 #define RST_DEVICES_W 0x35C 41 #define RST_DEVICES_X 0x28C 42 #define RST_DEVICES_Y 0x2a4 43 #define RST_DEVICES_SET_L 0x300 44 #define RST_DEVICES_CLR_L 0x304 45 #define RST_DEVICES_SET_H 0x308 46 #define RST_DEVICES_CLR_H 0x30c 47 #define RST_DEVICES_SET_U 0x310 48 #define RST_DEVICES_CLR_U 0x314 49 #define RST_DEVICES_SET_V 0x430 50 #define RST_DEVICES_CLR_V 0x434 51 #define RST_DEVICES_SET_W 0x438 52 #define RST_DEVICES_CLR_W 0x43c 53 #define RST_DEVICES_SET_X 0x290 54 #define RST_DEVICES_CLR_X 0x294 55 #define RST_DEVICES_SET_Y 0x2a8 56 #define RST_DEVICES_CLR_Y 0x2ac 57 58 /* 59 * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and 60 * any accidental write of 1 to these bits can cause PSLVERR. 61 * So below are the valid mask defines for each CLK_OUT_ENB register used to 62 * turn ON only the valid clocks. 63 */ 64 #define TEGRA210_CLK_ENB_VLD_MSK_L 0xdcd7dff9 65 #define TEGRA210_CLK_ENB_VLD_MSK_H 0x87d1f3e7 66 #define TEGRA210_CLK_ENB_VLD_MSK_U 0xf3fed3fa 67 #define TEGRA210_CLK_ENB_VLD_MSK_V 0xffc18cfb 68 #define TEGRA210_CLK_ENB_VLD_MSK_W 0x793fb7ff 69 #define TEGRA210_CLK_ENB_VLD_MSK_X 0x3fe66fff 70 #define TEGRA210_CLK_ENB_VLD_MSK_Y 0xfc1fc7ff 71 72 /** 73 * struct tegra_clk_sync_source - external clock source from codec 74 * 75 * @hw: handle between common and hardware-specific interfaces 76 * @rate: input frequency from source 77 * @max_rate: max rate allowed 78 */ 79 struct tegra_clk_sync_source { 80 struct clk_hw hw; 81 unsigned long rate; 82 unsigned long max_rate; 83 }; 84 85 #define to_clk_sync_source(_hw) \ 86 container_of(_hw, struct tegra_clk_sync_source, hw) 87 88 extern const struct clk_ops tegra_clk_sync_source_ops; 89 extern int *periph_clk_enb_refcnt; 90 91 struct clk *tegra_clk_register_sync_source(const char *name, 92 unsigned long max_rate); 93 94 /** 95 * struct tegra_clk_frac_div - fractional divider clock 96 * 97 * @hw: handle between common and hardware-specific interfaces 98 * @reg: register containing divider 99 * @flags: hardware-specific flags 100 * @shift: shift to the divider bit field 101 * @width: width of the divider bit field 102 * @frac_width: width of the fractional bit field 103 * @lock: register lock 104 * 105 * Flags: 106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 108 * flag indicates that this divider is for fixed rate PLL. 109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 110 * fraction bit is set. This flags indicates to calculate divider for which 111 * fracton bit will be zero. 112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 113 * set when divider value is not 0. This flags indicates that the divider 114 * is for UART module. 115 */ 116 struct tegra_clk_frac_div { 117 struct clk_hw hw; 118 void __iomem *reg; 119 u8 flags; 120 u8 shift; 121 u8 width; 122 u8 frac_width; 123 spinlock_t *lock; 124 }; 125 126 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 127 128 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 129 #define TEGRA_DIVIDER_FIXED BIT(1) 130 #define TEGRA_DIVIDER_INT BIT(2) 131 #define TEGRA_DIVIDER_UART BIT(3) 132 133 extern const struct clk_ops tegra_clk_frac_div_ops; 134 struct clk *tegra_clk_register_divider(const char *name, 135 const char *parent_name, void __iomem *reg, 136 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 137 u8 frac_width, spinlock_t *lock); 138 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, 139 void __iomem *reg, spinlock_t *lock); 140 141 /* 142 * Tegra PLL: 143 * 144 * In general, there are 3 requirements for each PLL 145 * that SW needs to be comply with. 146 * (1) Input frequency range (REF). 147 * (2) Comparison frequency range (CF). CF = REF/DIVM. 148 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 149 * 150 * The final PLL output frequency (FO) = VCO >> DIVP. 151 */ 152 153 /** 154 * struct tegra_clk_pll_freq_table - PLL frequecy table 155 * 156 * @input_rate: input rate from source 157 * @output_rate: output rate from PLL for the input rate 158 * @n: feedback divider 159 * @m: input divider 160 * @p: post divider 161 * @cpcon: charge pump current 162 * @sdm_data: fraction divider setting (0 = disabled) 163 */ 164 struct tegra_clk_pll_freq_table { 165 unsigned long input_rate; 166 unsigned long output_rate; 167 u32 n; 168 u32 m; 169 u8 p; 170 u8 cpcon; 171 u16 sdm_data; 172 }; 173 174 /** 175 * struct pdiv_map - map post divider to hw value 176 * 177 * @pdiv: post divider 178 * @hw_val: value to be written to the PLL hw 179 */ 180 struct pdiv_map { 181 u8 pdiv; 182 u8 hw_val; 183 }; 184 185 /** 186 * struct div_nmp - offset and width of m,n and p fields 187 * 188 * @divn_shift: shift to the feedback divider bit field 189 * @divn_width: width of the feedback divider bit field 190 * @divm_shift: shift to the input divider bit field 191 * @divm_width: width of the input divider bit field 192 * @divp_shift: shift to the post divider bit field 193 * @divp_width: width of the post divider bit field 194 * @override_divn_shift: shift to the feedback divider bitfield in override reg 195 * @override_divm_shift: shift to the input divider bitfield in override reg 196 * @override_divp_shift: shift to the post divider bitfield in override reg 197 */ 198 struct div_nmp { 199 u8 divn_shift; 200 u8 divn_width; 201 u8 divm_shift; 202 u8 divm_width; 203 u8 divp_shift; 204 u8 divp_width; 205 u8 override_divn_shift; 206 u8 override_divm_shift; 207 u8 override_divp_shift; 208 }; 209 210 #define MAX_PLL_MISC_REG_COUNT 6 211 212 struct tegra_clk_pll; 213 214 /** 215 * struct tegra_clk_pll_params - PLL parameters 216 * 217 * @input_min: Minimum input frequency 218 * @input_max: Maximum input frequency 219 * @cf_min: Minimum comparison frequency 220 * @cf_max: Maximum comparison frequency 221 * @vco_min: Minimum VCO frequency 222 * @vco_max: Maximum VCO frequency 223 * @base_reg: PLL base reg offset 224 * @misc_reg: PLL misc reg offset 225 * @lock_reg: PLL lock reg offset 226 * @lock_mask: Bitmask for PLL lock status 227 * @lock_enable_bit_idx: Bit index to enable PLL lock 228 * @iddq_reg: PLL IDDQ register offset 229 * @iddq_bit_idx: Bit index to enable PLL IDDQ 230 * @reset_reg: Register offset of where RESET bit is 231 * @reset_bit_idx: Shift of reset bit in reset_reg 232 * @sdm_din_reg: Register offset where SDM settings are 233 * @sdm_din_mask: Mask of SDM divider bits 234 * @sdm_ctrl_reg: Register offset where SDM enable is 235 * @sdm_ctrl_en_mask: Mask of SDM enable bit 236 * @ssc_ctrl_reg: Register offset where SSC settings are 237 * @ssc_ctrl_en_mask: Mask of SSC enable bit 238 * @aux_reg: AUX register offset 239 * @dyn_ramp_reg: Dynamic ramp control register offset 240 * @ext_misc_reg: Miscellaneous control register offsets 241 * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) 242 * @pmc_divp_reg: p divider PMC override register offset (PLLM) 243 * @flags: PLL flags 244 * @stepa_shift: Dynamic ramp step A field shift 245 * @stepb_shift: Dynamic ramp step B field shift 246 * @lock_delay: Delay in us if PLL lock is not used 247 * @max_p: maximum value for the p divider 248 * @defaults_set: Boolean signaling all reg defaults for PLL set. 249 * @pdiv_tohw: mapping of p divider to register values 250 * @div_nmp: offsets and widths on n, m and p fields 251 * @freq_table: array of frequencies supported by PLL 252 * @fixed_rate: PLL rate if it is fixed 253 * @mdiv_default: Default value for fixed mdiv for this PLL 254 * @round_p_to_pdiv: Callback used to round p to the closed pdiv 255 * @set_gain: Callback to adjust N div for SDM enabled 256 * PLL's based on fractional divider value. 257 * @calc_rate: Callback used to change how out of table 258 * rates (dividers and multipler) are calculated. 259 * @adjust_vco: Callback to adjust the programming range of the 260 * divider range (if SDM is present) 261 * @set_defaults: Callback which will try to initialize PLL 262 * registers to sane default values. This is first 263 * tried during PLL registration, but if the PLL 264 * is already enabled, it will be done the first 265 * time the rate is changed while the PLL is 266 * disabled. 267 * @dyn_ramp: Callback which can be used to define a custom 268 * dynamic ramp function for a given PLL. 269 * 270 * Flags: 271 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 272 * PLL locking. If not set it will use lock_delay value to wait. 273 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 274 * to be programmed to change output frequency of the PLL. 275 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 276 * to be programmed to change output frequency of the PLL. 277 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 278 * to be programmed to change output frequency of the PLL. 279 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 280 * that it is PLLU and invert post divider value. 281 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 282 * flag indicates that it is PLLM and use override settings. 283 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 284 * of some plls. 285 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 286 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 287 * base register. 288 * TEGRA_PLL_BYPASS - PLL has bypass bit 289 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 290 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv 291 * it may be more accurate (especially if SDM present) 292 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This 293 * flag indicated that it is PLLMB. 294 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output 295 */ 296 struct tegra_clk_pll_params { 297 unsigned long input_min; 298 unsigned long input_max; 299 unsigned long cf_min; 300 unsigned long cf_max; 301 unsigned long vco_min; 302 unsigned long vco_max; 303 304 u32 base_reg; 305 u32 misc_reg; 306 u32 lock_reg; 307 u32 lock_mask; 308 u32 lock_enable_bit_idx; 309 u32 iddq_reg; 310 u32 iddq_bit_idx; 311 u32 reset_reg; 312 u32 reset_bit_idx; 313 u32 sdm_din_reg; 314 u32 sdm_din_mask; 315 u32 sdm_ctrl_reg; 316 u32 sdm_ctrl_en_mask; 317 u32 ssc_ctrl_reg; 318 u32 ssc_ctrl_en_mask; 319 u32 aux_reg; 320 u32 dyn_ramp_reg; 321 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; 322 u32 pmc_divnm_reg; 323 u32 pmc_divp_reg; 324 u32 flags; 325 int stepa_shift; 326 int stepb_shift; 327 int lock_delay; 328 int max_p; 329 bool defaults_set; 330 const struct pdiv_map *pdiv_tohw; 331 struct div_nmp *div_nmp; 332 struct tegra_clk_pll_freq_table *freq_table; 333 unsigned long fixed_rate; 334 u16 mdiv_default; 335 u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); 336 void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); 337 int (*calc_rate)(struct clk_hw *hw, 338 struct tegra_clk_pll_freq_table *cfg, 339 unsigned long rate, unsigned long parent_rate); 340 unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, 341 unsigned long parent_rate); 342 void (*set_defaults)(struct tegra_clk_pll *pll); 343 int (*dyn_ramp)(struct tegra_clk_pll *pll, 344 struct tegra_clk_pll_freq_table *cfg); 345 }; 346 347 #define TEGRA_PLL_USE_LOCK BIT(0) 348 #define TEGRA_PLL_HAS_CPCON BIT(1) 349 #define TEGRA_PLL_SET_LFCON BIT(2) 350 #define TEGRA_PLL_SET_DCCON BIT(3) 351 #define TEGRA_PLLU BIT(4) 352 #define TEGRA_PLLM BIT(5) 353 #define TEGRA_PLL_FIXED BIT(6) 354 #define TEGRA_PLLE_CONFIGURE BIT(7) 355 #define TEGRA_PLL_LOCK_MISC BIT(8) 356 #define TEGRA_PLL_BYPASS BIT(9) 357 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 358 #define TEGRA_MDIV_NEW BIT(11) 359 #define TEGRA_PLLMB BIT(12) 360 #define TEGRA_PLL_VCO_OUT BIT(13) 361 362 /** 363 * struct tegra_clk_pll - Tegra PLL clock 364 * 365 * @hw: handle between common and hardware-specifix interfaces 366 * @clk_base: address of CAR controller 367 * @pmc: address of PMC, required to read override bits 368 * @lock: register lock 369 * @params: PLL parameters 370 */ 371 struct tegra_clk_pll { 372 struct clk_hw hw; 373 void __iomem *clk_base; 374 void __iomem *pmc; 375 spinlock_t *lock; 376 struct tegra_clk_pll_params *params; 377 }; 378 379 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 380 381 /** 382 * struct tegra_audio_clk_info - Tegra Audio Clk Information 383 * 384 * @name: name for the audio pll 385 * @pll_params: pll_params for audio pll 386 * @clk_id: clk_ids for the audio pll 387 * @parent: name of the parent of the audio pll 388 */ 389 struct tegra_audio_clk_info { 390 char *name; 391 struct tegra_clk_pll_params *pll_params; 392 int clk_id; 393 char *parent; 394 }; 395 396 extern const struct clk_ops tegra_clk_pll_ops; 397 extern const struct clk_ops tegra_clk_plle_ops; 398 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 399 void __iomem *clk_base, void __iomem *pmc, 400 unsigned long flags, struct tegra_clk_pll_params *pll_params, 401 spinlock_t *lock); 402 403 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 404 void __iomem *clk_base, void __iomem *pmc, 405 unsigned long flags, struct tegra_clk_pll_params *pll_params, 406 spinlock_t *lock); 407 408 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 409 void __iomem *clk_base, void __iomem *pmc, 410 unsigned long flags, 411 struct tegra_clk_pll_params *pll_params, 412 spinlock_t *lock); 413 414 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 415 void __iomem *clk_base, void __iomem *pmc, 416 unsigned long flags, 417 struct tegra_clk_pll_params *pll_params, 418 spinlock_t *lock); 419 420 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 421 void __iomem *clk_base, void __iomem *pmc, 422 unsigned long flags, 423 struct tegra_clk_pll_params *pll_params, 424 spinlock_t *lock); 425 426 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 427 void __iomem *clk_base, void __iomem *pmc, 428 unsigned long flags, 429 struct tegra_clk_pll_params *pll_params, 430 spinlock_t *lock, unsigned long parent_rate); 431 432 struct clk *tegra_clk_register_pllre_tegra210(const char *name, 433 const char *parent_name, void __iomem *clk_base, 434 void __iomem *pmc, unsigned long flags, 435 struct tegra_clk_pll_params *pll_params, 436 spinlock_t *lock, unsigned long parent_rate); 437 438 struct clk *tegra_clk_register_plle_tegra114(const char *name, 439 const char *parent_name, 440 void __iomem *clk_base, unsigned long flags, 441 struct tegra_clk_pll_params *pll_params, 442 spinlock_t *lock); 443 444 struct clk *tegra_clk_register_plle_tegra210(const char *name, 445 const char *parent_name, 446 void __iomem *clk_base, unsigned long flags, 447 struct tegra_clk_pll_params *pll_params, 448 spinlock_t *lock); 449 450 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 451 const char *parent_name, void __iomem *clk_base, 452 void __iomem *pmc, unsigned long flags, 453 struct tegra_clk_pll_params *pll_params, 454 spinlock_t *lock); 455 456 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 457 const char *parent_name, void __iomem *clk_base, 458 unsigned long flags, 459 struct tegra_clk_pll_params *pll_params, 460 spinlock_t *lock); 461 462 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 463 void __iomem *clk_base, unsigned long flags, 464 struct tegra_clk_pll_params *pll_params, 465 spinlock_t *lock); 466 467 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 468 void __iomem *clk_base, void __iomem *pmc, 469 unsigned long flags, 470 struct tegra_clk_pll_params *pll_params, 471 spinlock_t *lock); 472 473 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name, 474 void __iomem *clk_base, unsigned long flags, 475 struct tegra_clk_pll_params *pll_params, 476 spinlock_t *lock); 477 478 struct clk *tegra_clk_register_pllu_tegra114(const char *name, 479 const char *parent_name, 480 void __iomem *clk_base, unsigned long flags, 481 struct tegra_clk_pll_params *pll_params, 482 spinlock_t *lock); 483 484 struct clk *tegra_clk_register_pllu_tegra210(const char *name, 485 const char *parent_name, 486 void __iomem *clk_base, unsigned long flags, 487 struct tegra_clk_pll_params *pll_params, 488 spinlock_t *lock); 489 490 /** 491 * struct tegra_clk_pll_out - PLL divider down clock 492 * 493 * @hw: handle between common and hardware-specific interfaces 494 * @reg: register containing the PLL divider 495 * @enb_bit_idx: bit to enable/disable PLL divider 496 * @rst_bit_idx: bit to reset PLL divider 497 * @lock: register lock 498 * @flags: hardware-specific flags 499 */ 500 struct tegra_clk_pll_out { 501 struct clk_hw hw; 502 void __iomem *reg; 503 u8 enb_bit_idx; 504 u8 rst_bit_idx; 505 spinlock_t *lock; 506 u8 flags; 507 }; 508 509 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 510 511 extern const struct clk_ops tegra_clk_pll_out_ops; 512 struct clk *tegra_clk_register_pll_out(const char *name, 513 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 514 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 515 spinlock_t *lock); 516 517 /** 518 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 519 * 520 * @enb_reg: read the enable status 521 * @enb_set_reg: write 1 to enable clock 522 * @enb_clr_reg: write 1 to disable clock 523 * @rst_reg: read the reset status 524 * @rst_set_reg: write 1 to assert the reset of peripheral 525 * @rst_clr_reg: write 1 to deassert the reset of peripheral 526 */ 527 struct tegra_clk_periph_regs { 528 u32 enb_reg; 529 u32 enb_set_reg; 530 u32 enb_clr_reg; 531 u32 rst_reg; 532 u32 rst_set_reg; 533 u32 rst_clr_reg; 534 }; 535 536 /** 537 * struct tegra_clk_periph_gate - peripheral gate clock 538 * 539 * @magic: magic number to validate type 540 * @hw: handle between common and hardware-specific interfaces 541 * @clk_base: address of CAR controller 542 * @regs: Registers to control the peripheral 543 * @flags: hardware-specific flags 544 * @clk_num: Clock number 545 * @enable_refcnt: array to maintain reference count of the clock 546 * 547 * Flags: 548 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 549 * for this module. 550 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 551 * after clock enable and driver for the module is responsible for 552 * doing reset. 553 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 554 * bus to flush the write operation in apb bus. This flag indicates 555 * that this peripheral is in apb bus. 556 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug 557 */ 558 struct tegra_clk_periph_gate { 559 u32 magic; 560 struct clk_hw hw; 561 void __iomem *clk_base; 562 u8 flags; 563 int clk_num; 564 int *enable_refcnt; 565 const struct tegra_clk_periph_regs *regs; 566 }; 567 568 #define to_clk_periph_gate(_hw) \ 569 container_of(_hw, struct tegra_clk_periph_gate, hw) 570 571 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 572 573 #define TEGRA_PERIPH_NO_RESET BIT(0) 574 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 575 #define TEGRA_PERIPH_ON_APB BIT(2) 576 #define TEGRA_PERIPH_WAR_1005168 BIT(3) 577 #define TEGRA_PERIPH_NO_DIV BIT(4) 578 #define TEGRA_PERIPH_NO_GATE BIT(5) 579 580 extern const struct clk_ops tegra_clk_periph_gate_ops; 581 struct clk *tegra_clk_register_periph_gate(const char *name, 582 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 583 unsigned long flags, int clk_num, int *enable_refcnt); 584 585 struct tegra_clk_periph_fixed { 586 struct clk_hw hw; 587 void __iomem *base; 588 const struct tegra_clk_periph_regs *regs; 589 unsigned int mul; 590 unsigned int div; 591 unsigned int num; 592 }; 593 594 struct clk *tegra_clk_register_periph_fixed(const char *name, 595 const char *parent, 596 unsigned long flags, 597 void __iomem *base, 598 unsigned int mul, 599 unsigned int div, 600 unsigned int num); 601 602 /** 603 * struct clk-periph - peripheral clock 604 * 605 * @magic: magic number to validate type 606 * @hw: handle between common and hardware-specific interfaces 607 * @mux: mux clock 608 * @divider: divider clock 609 * @gate: gate clock 610 * @mux_ops: mux clock ops 611 * @div_ops: divider clock ops 612 * @gate_ops: gate clock ops 613 */ 614 struct tegra_clk_periph { 615 u32 magic; 616 struct clk_hw hw; 617 struct clk_mux mux; 618 struct tegra_clk_frac_div divider; 619 struct tegra_clk_periph_gate gate; 620 621 const struct clk_ops *mux_ops; 622 const struct clk_ops *div_ops; 623 const struct clk_ops *gate_ops; 624 }; 625 626 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 627 628 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 629 630 extern const struct clk_ops tegra_clk_periph_ops; 631 struct clk *tegra_clk_register_periph(const char *name, 632 const char * const *parent_names, int num_parents, 633 struct tegra_clk_periph *periph, void __iomem *clk_base, 634 u32 offset, unsigned long flags); 635 struct clk *tegra_clk_register_periph_nodiv(const char *name, 636 const char * const *parent_names, int num_parents, 637 struct tegra_clk_periph *periph, void __iomem *clk_base, 638 u32 offset); 639 640 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 641 _div_shift, _div_width, _div_frac_width, \ 642 _div_flags, _clk_num,\ 643 _gate_flags, _table, _lock) \ 644 { \ 645 .mux = { \ 646 .flags = _mux_flags, \ 647 .shift = _mux_shift, \ 648 .mask = _mux_mask, \ 649 .table = _table, \ 650 .lock = _lock, \ 651 }, \ 652 .divider = { \ 653 .flags = _div_flags, \ 654 .shift = _div_shift, \ 655 .width = _div_width, \ 656 .frac_width = _div_frac_width, \ 657 .lock = _lock, \ 658 }, \ 659 .gate = { \ 660 .flags = _gate_flags, \ 661 .clk_num = _clk_num, \ 662 }, \ 663 .mux_ops = &clk_mux_ops, \ 664 .div_ops = &tegra_clk_frac_div_ops, \ 665 .gate_ops = &tegra_clk_periph_gate_ops, \ 666 } 667 668 struct tegra_periph_init_data { 669 const char *name; 670 int clk_id; 671 union { 672 const char *const *parent_names; 673 const char *parent_name; 674 } p; 675 int num_parents; 676 struct tegra_clk_periph periph; 677 u32 offset; 678 const char *con_id; 679 const char *dev_id; 680 unsigned long flags; 681 }; 682 683 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 684 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 685 _div_width, _div_frac_width, _div_flags, \ 686 _clk_num, _gate_flags, _clk_id, _table, \ 687 _flags, _lock) \ 688 { \ 689 .name = _name, \ 690 .clk_id = _clk_id, \ 691 .p.parent_names = _parent_names, \ 692 .num_parents = ARRAY_SIZE(_parent_names), \ 693 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 694 _mux_flags, _div_shift, \ 695 _div_width, _div_frac_width, \ 696 _div_flags, _clk_num, \ 697 _gate_flags, _table, _lock), \ 698 .offset = _offset, \ 699 .con_id = _con_id, \ 700 .dev_id = _dev_id, \ 701 .flags = _flags \ 702 } 703 704 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 705 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 706 _div_width, _div_frac_width, _div_flags, \ 707 _clk_num, _gate_flags, _clk_id) \ 708 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 709 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 710 _div_shift, _div_width, _div_frac_width, _div_flags, \ 711 _clk_num, _gate_flags, _clk_id,\ 712 NULL, 0, NULL) 713 714 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, 715 struct tegra_periph_init_data *init); 716 717 /** 718 * struct clk_super_mux - super clock 719 * 720 * @hw: handle between common and hardware-specific interfaces 721 * @reg: register controlling multiplexer 722 * @width: width of the multiplexer bit field 723 * @flags: hardware-specific flags 724 * @div2_index: bit controlling divide-by-2 725 * @pllx_index: PLLX index in the parent list 726 * @lock: register lock 727 * 728 * Flags: 729 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 730 * that this is LP cluster clock. 731 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5 732 * super mux parent using PLLP branches. To use PLLP branches to CPU, need 733 * to configure additional bit PLLP_OUT_CPU in the clock registers. 734 */ 735 struct tegra_clk_super_mux { 736 struct clk_hw hw; 737 void __iomem *reg; 738 struct tegra_clk_frac_div frac_div; 739 const struct clk_ops *div_ops; 740 u8 width; 741 u8 flags; 742 u8 div2_index; 743 u8 pllx_index; 744 spinlock_t *lock; 745 }; 746 747 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 748 749 #define TEGRA_DIVIDER_2 BIT(0) 750 #define TEGRA210_CPU_CLK BIT(1) 751 752 extern const struct clk_ops tegra_clk_super_ops; 753 struct clk *tegra_clk_register_super_mux(const char *name, 754 const char **parent_names, u8 num_parents, 755 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 756 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 757 struct clk *tegra_clk_register_super_clk(const char *name, 758 const char * const *parent_names, u8 num_parents, 759 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 760 spinlock_t *lock); 761 762 /** 763 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC 764 * 765 * @hw: handle between common and hardware-specific interfaces 766 * @reg: register controlling mux and divider 767 * @flags: hardware-specific flags 768 * @lock: optional register lock 769 * @gate: gate clock 770 * @gate_ops: gate clock ops 771 */ 772 struct tegra_sdmmc_mux { 773 struct clk_hw hw; 774 void __iomem *reg; 775 spinlock_t *lock; 776 const struct clk_ops *gate_ops; 777 struct tegra_clk_periph_gate gate; 778 u8 div_flags; 779 }; 780 781 #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) 782 783 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, 784 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, 785 unsigned long flags, void *lock); 786 787 /** 788 * struct clk_init_table - clock initialization table 789 * @clk_id: clock id as mentioned in device tree bindings 790 * @parent_id: parent clock id as mentioned in device tree bindings 791 * @rate: rate to set 792 * @state: enable/disable 793 */ 794 struct tegra_clk_init_table { 795 unsigned int clk_id; 796 unsigned int parent_id; 797 unsigned long rate; 798 int state; 799 }; 800 801 /** 802 * struct clk_duplicate - duplicate clocks 803 * @clk_id: clock id as mentioned in device tree bindings 804 * @lookup: duplicate lookup entry for the clock 805 */ 806 struct tegra_clk_duplicate { 807 int clk_id; 808 struct clk_lookup lookup; 809 }; 810 811 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 812 { \ 813 .clk_id = _clk_id, \ 814 .lookup = { \ 815 .dev_id = _dev, \ 816 .con_id = _con, \ 817 }, \ 818 } 819 820 struct tegra_clk { 821 int dt_id; 822 bool present; 823 }; 824 825 struct tegra_devclk { 826 int dt_id; 827 char *dev_id; 828 char *con_id; 829 }; 830 831 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long), 832 int (*deassert)(unsigned long)); 833 834 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 835 struct clk *clks[], int clk_max); 836 837 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 838 struct clk *clks[], int clk_max); 839 840 const struct tegra_clk_periph_regs *get_reg_bank(int clkid); 841 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); 842 843 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); 844 845 void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get); 846 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 847 848 void tegra_audio_clk_init(void __iomem *clk_base, 849 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 850 struct tegra_audio_clk_info *audio_info, 851 unsigned int num_plls, unsigned long sync_max_rate); 852 853 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, 854 struct tegra_clk *tegra_clks, 855 struct tegra_clk_pll_params *pll_params); 856 857 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); 858 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 859 unsigned long *input_freqs, unsigned int num, 860 unsigned int clk_m_div, unsigned long *osc_freq, 861 unsigned long *pll_ref_freq); 862 void tegra_super_clk_gen4_init(void __iomem *clk_base, 863 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 864 struct tegra_clk_pll_params *pll_params); 865 void tegra_super_clk_gen5_init(void __iomem *clk_base, 866 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 867 struct tegra_clk_pll_params *pll_params); 868 869 #ifdef CONFIG_TEGRA_CLK_EMC 870 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 871 spinlock_t *lock); 872 #else 873 static inline struct clk *tegra_clk_register_emc(void __iomem *base, 874 struct device_node *np, 875 spinlock_t *lock) 876 { 877 return NULL; 878 } 879 #endif 880 881 void tegra114_clock_tune_cpu_trimmers_high(void); 882 void tegra114_clock_tune_cpu_trimmers_low(void); 883 void tegra114_clock_tune_cpu_trimmers_init(void); 884 void tegra114_clock_assert_dfll_dvco_reset(void); 885 void tegra114_clock_deassert_dfll_dvco_reset(void); 886 887 typedef void (*tegra_clk_apply_init_table_func)(void); 888 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 889 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); 890 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); 891 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); 892 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, 893 u8 frac_width, u8 flags); 894 void tegra_clk_osc_resume(void __iomem *clk_base); 895 void tegra_clk_set_pllp_out_cpu(bool enable); 896 void tegra_clk_periph_suspend(void); 897 void tegra_clk_periph_resume(void); 898 899 900 /* Combined read fence with delay */ 901 #define fence_udelay(delay, reg) \ 902 do { \ 903 readl(reg); \ 904 udelay(delay); \ 905 } while (0) 906 907 bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw); 908 struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter); 909 910 #endif /* TEGRA_CLK_H */ 911