1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __TEGRA_CLK_H 18 #define __TEGRA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30 struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34 }; 35 36 #define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39 extern const struct clk_ops tegra_clk_sync_source_ops; 40 struct clk *tegra_clk_register_sync_source(const char *name, 41 unsigned long fixed_rate, unsigned long max_rate); 42 43 /** 44 * struct tegra_clk_frac_div - fractional divider clock 45 * 46 * @hw: handle between common and hardware-specific interfaces 47 * @reg: register containing divider 48 * @flags: hardware-specific flags 49 * @shift: shift to the divider bit field 50 * @width: width of the divider bit field 51 * @frac_width: width of the fractional bit field 52 * @lock: register lock 53 * 54 * Flags: 55 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 56 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 57 * flag indicates that this divider is for fixed rate PLL. 58 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 59 * fraction bit is set. This flags indicates to calculate divider for which 60 * fracton bit will be zero. 61 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 62 * set when divider value is not 0. This flags indicates that the divider 63 * is for UART module. 64 */ 65 struct tegra_clk_frac_div { 66 struct clk_hw hw; 67 void __iomem *reg; 68 u8 flags; 69 u8 shift; 70 u8 width; 71 u8 frac_width; 72 spinlock_t *lock; 73 }; 74 75 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 76 77 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 78 #define TEGRA_DIVIDER_FIXED BIT(1) 79 #define TEGRA_DIVIDER_INT BIT(2) 80 #define TEGRA_DIVIDER_UART BIT(3) 81 82 extern const struct clk_ops tegra_clk_frac_div_ops; 83 struct clk *tegra_clk_register_divider(const char *name, 84 const char *parent_name, void __iomem *reg, 85 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 86 u8 frac_width, spinlock_t *lock); 87 88 /* 89 * Tegra PLL: 90 * 91 * In general, there are 3 requirements for each PLL 92 * that SW needs to be comply with. 93 * (1) Input frequency range (REF). 94 * (2) Comparison frequency range (CF). CF = REF/DIVM. 95 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 96 * 97 * The final PLL output frequency (FO) = VCO >> DIVP. 98 */ 99 100 /** 101 * struct tegra_clk_pll_freq_table - PLL frequecy table 102 * 103 * @input_rate: input rate from source 104 * @output_rate: output rate from PLL for the input rate 105 * @n: feedback divider 106 * @m: input divider 107 * @p: post divider 108 * @cpcon: charge pump current 109 */ 110 struct tegra_clk_pll_freq_table { 111 unsigned long input_rate; 112 unsigned long output_rate; 113 u16 n; 114 u16 m; 115 u8 p; 116 u8 cpcon; 117 }; 118 119 /** 120 * struct clk_pll_params - PLL parameters 121 * 122 * @input_min: Minimum input frequency 123 * @input_max: Maximum input frequency 124 * @cf_min: Minimum comparison frequency 125 * @cf_max: Maximum comparison frequency 126 * @vco_min: Minimum VCO frequency 127 * @vco_max: Maximum VCO frequency 128 * @base_reg: PLL base reg offset 129 * @misc_reg: PLL misc reg offset 130 * @lock_reg: PLL lock reg offset 131 * @lock_bit_idx: Bit index for PLL lock status 132 * @lock_enable_bit_idx: Bit index to enable PLL lock 133 * @lock_delay: Delay in us if PLL lock is not used 134 */ 135 struct tegra_clk_pll_params { 136 unsigned long input_min; 137 unsigned long input_max; 138 unsigned long cf_min; 139 unsigned long cf_max; 140 unsigned long vco_min; 141 unsigned long vco_max; 142 143 u32 base_reg; 144 u32 misc_reg; 145 u32 lock_reg; 146 u32 lock_bit_idx; 147 u32 lock_enable_bit_idx; 148 int lock_delay; 149 }; 150 151 /** 152 * struct tegra_clk_pll - Tegra PLL clock 153 * 154 * @hw: handle between common and hardware-specifix interfaces 155 * @clk_base: address of CAR controller 156 * @pmc: address of PMC, required to read override bits 157 * @freq_table: array of frequencies supported by PLL 158 * @params: PLL parameters 159 * @flags: PLL flags 160 * @fixed_rate: PLL rate if it is fixed 161 * @lock: register lock 162 * @divn_shift: shift to the feedback divider bit field 163 * @divn_width: width of the feedback divider bit field 164 * @divm_shift: shift to the input divider bit field 165 * @divm_width: width of the input divider bit field 166 * @divp_shift: shift to the post divider bit field 167 * @divp_width: width of the post divider bit field 168 * 169 * Flags: 170 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 171 * PLL locking. If not set it will use lock_delay value to wait. 172 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 173 * to be programmed to change output frequency of the PLL. 174 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 175 * to be programmed to change output frequency of the PLL. 176 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 177 * to be programmed to change output frequency of the PLL. 178 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 179 * that it is PLLU and invert post divider value. 180 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 181 * flag indicates that it is PLLM and use override settings. 182 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 183 * of some plls. 184 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 185 */ 186 struct tegra_clk_pll { 187 struct clk_hw hw; 188 void __iomem *clk_base; 189 void __iomem *pmc; 190 u8 flags; 191 unsigned long fixed_rate; 192 spinlock_t *lock; 193 u8 divn_shift; 194 u8 divn_width; 195 u8 divm_shift; 196 u8 divm_width; 197 u8 divp_shift; 198 u8 divp_width; 199 struct tegra_clk_pll_freq_table *freq_table; 200 struct tegra_clk_pll_params *params; 201 }; 202 203 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 204 205 #define TEGRA_PLL_USE_LOCK BIT(0) 206 #define TEGRA_PLL_HAS_CPCON BIT(1) 207 #define TEGRA_PLL_SET_LFCON BIT(2) 208 #define TEGRA_PLL_SET_DCCON BIT(3) 209 #define TEGRA_PLLU BIT(4) 210 #define TEGRA_PLLM BIT(5) 211 #define TEGRA_PLL_FIXED BIT(6) 212 #define TEGRA_PLLE_CONFIGURE BIT(7) 213 214 extern const struct clk_ops tegra_clk_pll_ops; 215 extern const struct clk_ops tegra_clk_plle_ops; 216 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 217 void __iomem *clk_base, void __iomem *pmc, 218 unsigned long flags, unsigned long fixed_rate, 219 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 220 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 221 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 222 void __iomem *clk_base, void __iomem *pmc, 223 unsigned long flags, unsigned long fixed_rate, 224 struct tegra_clk_pll_params *pll_params, u8 pll_flags, 225 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 226 227 /** 228 * struct tegra_clk_pll_out - PLL divider down clock 229 * 230 * @hw: handle between common and hardware-specific interfaces 231 * @reg: register containing the PLL divider 232 * @enb_bit_idx: bit to enable/disable PLL divider 233 * @rst_bit_idx: bit to reset PLL divider 234 * @lock: register lock 235 * @flags: hardware-specific flags 236 */ 237 struct tegra_clk_pll_out { 238 struct clk_hw hw; 239 void __iomem *reg; 240 u8 enb_bit_idx; 241 u8 rst_bit_idx; 242 spinlock_t *lock; 243 u8 flags; 244 }; 245 246 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 247 248 extern const struct clk_ops tegra_clk_pll_out_ops; 249 struct clk *tegra_clk_register_pll_out(const char *name, 250 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 251 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 252 spinlock_t *lock); 253 254 /** 255 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 256 * 257 * @enb_reg: read the enable status 258 * @enb_set_reg: write 1 to enable clock 259 * @enb_clr_reg: write 1 to disable clock 260 * @rst_reg: read the reset status 261 * @rst_set_reg: write 1 to assert the reset of peripheral 262 * @rst_clr_reg: write 1 to deassert the reset of peripheral 263 */ 264 struct tegra_clk_periph_regs { 265 u32 enb_reg; 266 u32 enb_set_reg; 267 u32 enb_clr_reg; 268 u32 rst_reg; 269 u32 rst_set_reg; 270 u32 rst_clr_reg; 271 }; 272 273 /** 274 * struct tegra_clk_periph_gate - peripheral gate clock 275 * 276 * @magic: magic number to validate type 277 * @hw: handle between common and hardware-specific interfaces 278 * @clk_base: address of CAR controller 279 * @regs: Registers to control the peripheral 280 * @flags: hardware-specific flags 281 * @clk_num: Clock number 282 * @enable_refcnt: array to maintain reference count of the clock 283 * 284 * Flags: 285 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 286 * for this module. 287 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 288 * after clock enable and driver for the module is responsible for 289 * doing reset. 290 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 291 * bus to flush the write operation in apb bus. This flag indicates 292 * that this peripheral is in apb bus. 293 */ 294 struct tegra_clk_periph_gate { 295 u32 magic; 296 struct clk_hw hw; 297 void __iomem *clk_base; 298 u8 flags; 299 int clk_num; 300 int *enable_refcnt; 301 struct tegra_clk_periph_regs *regs; 302 }; 303 304 #define to_clk_periph_gate(_hw) \ 305 container_of(_hw, struct tegra_clk_periph_gate, hw) 306 307 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 308 309 #define TEGRA_PERIPH_NO_RESET BIT(0) 310 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 311 #define TEGRA_PERIPH_ON_APB BIT(2) 312 313 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 314 extern const struct clk_ops tegra_clk_periph_gate_ops; 315 struct clk *tegra_clk_register_periph_gate(const char *name, 316 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 317 unsigned long flags, int clk_num, 318 struct tegra_clk_periph_regs *pregs, int *enable_refcnt); 319 320 /** 321 * struct clk-periph - peripheral clock 322 * 323 * @magic: magic number to validate type 324 * @hw: handle between common and hardware-specific interfaces 325 * @mux: mux clock 326 * @divider: divider clock 327 * @gate: gate clock 328 * @mux_ops: mux clock ops 329 * @div_ops: divider clock ops 330 * @gate_ops: gate clock ops 331 */ 332 struct tegra_clk_periph { 333 u32 magic; 334 struct clk_hw hw; 335 struct clk_mux mux; 336 struct tegra_clk_frac_div divider; 337 struct tegra_clk_periph_gate gate; 338 339 const struct clk_ops *mux_ops; 340 const struct clk_ops *div_ops; 341 const struct clk_ops *gate_ops; 342 }; 343 344 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 345 346 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 347 348 extern const struct clk_ops tegra_clk_periph_ops; 349 struct clk *tegra_clk_register_periph(const char *name, 350 const char **parent_names, int num_parents, 351 struct tegra_clk_periph *periph, void __iomem *clk_base, 352 u32 offset); 353 struct clk *tegra_clk_register_periph_nodiv(const char *name, 354 const char **parent_names, int num_parents, 355 struct tegra_clk_periph *periph, void __iomem *clk_base, 356 u32 offset); 357 358 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \ 359 _div_shift, _div_width, _div_frac_width, \ 360 _div_flags, _clk_num, _enb_refcnt, _regs, \ 361 _gate_flags) \ 362 { \ 363 .mux = { \ 364 .flags = _mux_flags, \ 365 .shift = _mux_shift, \ 366 .width = _mux_width, \ 367 }, \ 368 .divider = { \ 369 .flags = _div_flags, \ 370 .shift = _div_shift, \ 371 .width = _div_width, \ 372 .frac_width = _div_frac_width, \ 373 }, \ 374 .gate = { \ 375 .flags = _gate_flags, \ 376 .clk_num = _clk_num, \ 377 .enable_refcnt = _enb_refcnt, \ 378 .regs = _regs, \ 379 }, \ 380 .mux_ops = &clk_mux_ops, \ 381 .div_ops = &tegra_clk_frac_div_ops, \ 382 .gate_ops = &tegra_clk_periph_gate_ops, \ 383 } 384 385 struct tegra_periph_init_data { 386 const char *name; 387 int clk_id; 388 const char **parent_names; 389 int num_parents; 390 struct tegra_clk_periph periph; 391 u32 offset; 392 const char *con_id; 393 const char *dev_id; 394 }; 395 396 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \ 397 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 398 _div_width, _div_frac_width, _div_flags, _regs, \ 399 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 400 { \ 401 .name = _name, \ 402 .clk_id = _clk_id, \ 403 .parent_names = _parent_names, \ 404 .num_parents = ARRAY_SIZE(_parent_names), \ 405 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \ 406 _mux_flags, _div_shift, \ 407 _div_width, _div_frac_width, \ 408 _div_flags, _clk_num, \ 409 _enb_refcnt, _regs, \ 410 _gate_flags), \ 411 .offset = _offset, \ 412 .con_id = _con_id, \ 413 .dev_id = _dev_id, \ 414 } 415 416 /** 417 * struct clk_super_mux - super clock 418 * 419 * @hw: handle between common and hardware-specific interfaces 420 * @reg: register controlling multiplexer 421 * @width: width of the multiplexer bit field 422 * @flags: hardware-specific flags 423 * @div2_index: bit controlling divide-by-2 424 * @pllx_index: PLLX index in the parent list 425 * @lock: register lock 426 * 427 * Flags: 428 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 429 * that this is LP cluster clock. 430 */ 431 struct tegra_clk_super_mux { 432 struct clk_hw hw; 433 void __iomem *reg; 434 u8 width; 435 u8 flags; 436 u8 div2_index; 437 u8 pllx_index; 438 spinlock_t *lock; 439 }; 440 441 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 442 443 #define TEGRA_DIVIDER_2 BIT(0) 444 445 extern const struct clk_ops tegra_clk_super_ops; 446 struct clk *tegra_clk_register_super_mux(const char *name, 447 const char **parent_names, u8 num_parents, 448 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 449 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 450 451 /** 452 * struct clk_init_tabel - clock initialization table 453 * @clk_id: clock id as mentioned in device tree bindings 454 * @parent_id: parent clock id as mentioned in device tree bindings 455 * @rate: rate to set 456 * @state: enable/disable 457 */ 458 struct tegra_clk_init_table { 459 unsigned int clk_id; 460 unsigned int parent_id; 461 unsigned long rate; 462 int state; 463 }; 464 465 /** 466 * struct clk_duplicate - duplicate clocks 467 * @clk_id: clock id as mentioned in device tree bindings 468 * @lookup: duplicate lookup entry for the clock 469 */ 470 struct tegra_clk_duplicate { 471 int clk_id; 472 struct clk_lookup lookup; 473 }; 474 475 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 476 { \ 477 .clk_id = _clk_id, \ 478 .lookup = { \ 479 .dev_id = _dev, \ 480 .con_id = _con, \ 481 }, \ 482 } 483 484 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 485 struct clk *clks[], int clk_max); 486 487 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 488 struct clk *clks[], int clk_max); 489 490 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 491 void tegra20_clock_init(struct device_node *np); 492 #else 493 static inline void tegra20_clock_init(struct device_node *np) {} 494 #endif /* CONFIG_ARCH_TEGRA_2x_SOC */ 495 496 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 497 void tegra30_clock_init(struct device_node *np); 498 #else 499 static inline void tegra30_clock_init(struct device_node *np) {} 500 #endif /* CONFIG_ARCH_TEGRA_3x_SOC */ 501 502 #endif /* TEGRA_CLK_H */ 503