1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __TEGRA_CLK_H 7 #define __TEGRA_CLK_H 8 9 #include <linux/clk-provider.h> 10 #include <linux/clkdev.h> 11 #include <linux/delay.h> 12 13 /** 14 * struct tegra_clk_sync_source - external clock source from codec 15 * 16 * @hw: handle between common and hardware-specific interfaces 17 * @rate: input frequency from source 18 * @max_rate: max rate allowed 19 */ 20 struct tegra_clk_sync_source { 21 struct clk_hw hw; 22 unsigned long rate; 23 unsigned long max_rate; 24 }; 25 26 #define to_clk_sync_source(_hw) \ 27 container_of(_hw, struct tegra_clk_sync_source, hw) 28 29 extern const struct clk_ops tegra_clk_sync_source_ops; 30 extern int *periph_clk_enb_refcnt; 31 32 struct clk *tegra_clk_register_sync_source(const char *name, 33 unsigned long max_rate); 34 35 /** 36 * struct tegra_clk_frac_div - fractional divider clock 37 * 38 * @hw: handle between common and hardware-specific interfaces 39 * @reg: register containing divider 40 * @flags: hardware-specific flags 41 * @shift: shift to the divider bit field 42 * @width: width of the divider bit field 43 * @frac_width: width of the fractional bit field 44 * @lock: register lock 45 * 46 * Flags: 47 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 48 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 49 * flag indicates that this divider is for fixed rate PLL. 50 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 51 * fraction bit is set. This flags indicates to calculate divider for which 52 * fracton bit will be zero. 53 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 54 * set when divider value is not 0. This flags indicates that the divider 55 * is for UART module. 56 */ 57 struct tegra_clk_frac_div { 58 struct clk_hw hw; 59 void __iomem *reg; 60 u8 flags; 61 u8 shift; 62 u8 width; 63 u8 frac_width; 64 spinlock_t *lock; 65 }; 66 67 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 68 69 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 70 #define TEGRA_DIVIDER_FIXED BIT(1) 71 #define TEGRA_DIVIDER_INT BIT(2) 72 #define TEGRA_DIVIDER_UART BIT(3) 73 74 extern const struct clk_ops tegra_clk_frac_div_ops; 75 struct clk *tegra_clk_register_divider(const char *name, 76 const char *parent_name, void __iomem *reg, 77 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 78 u8 frac_width, spinlock_t *lock); 79 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, 80 void __iomem *reg, spinlock_t *lock); 81 82 /* 83 * Tegra PLL: 84 * 85 * In general, there are 3 requirements for each PLL 86 * that SW needs to be comply with. 87 * (1) Input frequency range (REF). 88 * (2) Comparison frequency range (CF). CF = REF/DIVM. 89 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 90 * 91 * The final PLL output frequency (FO) = VCO >> DIVP. 92 */ 93 94 /** 95 * struct tegra_clk_pll_freq_table - PLL frequecy table 96 * 97 * @input_rate: input rate from source 98 * @output_rate: output rate from PLL for the input rate 99 * @n: feedback divider 100 * @m: input divider 101 * @p: post divider 102 * @cpcon: charge pump current 103 * @sdm_data: fraction divider setting (0 = disabled) 104 */ 105 struct tegra_clk_pll_freq_table { 106 unsigned long input_rate; 107 unsigned long output_rate; 108 u32 n; 109 u32 m; 110 u8 p; 111 u8 cpcon; 112 u16 sdm_data; 113 }; 114 115 /** 116 * struct pdiv_map - map post divider to hw value 117 * 118 * @pdiv: post divider 119 * @hw_val: value to be written to the PLL hw 120 */ 121 struct pdiv_map { 122 u8 pdiv; 123 u8 hw_val; 124 }; 125 126 /** 127 * struct div_nmp - offset and width of m,n and p fields 128 * 129 * @divn_shift: shift to the feedback divider bit field 130 * @divn_width: width of the feedback divider bit field 131 * @divm_shift: shift to the input divider bit field 132 * @divm_width: width of the input divider bit field 133 * @divp_shift: shift to the post divider bit field 134 * @divp_width: width of the post divider bit field 135 * @override_divn_shift: shift to the feedback divider bitfield in override reg 136 * @override_divm_shift: shift to the input divider bitfield in override reg 137 * @override_divp_shift: shift to the post divider bitfield in override reg 138 */ 139 struct div_nmp { 140 u8 divn_shift; 141 u8 divn_width; 142 u8 divm_shift; 143 u8 divm_width; 144 u8 divp_shift; 145 u8 divp_width; 146 u8 override_divn_shift; 147 u8 override_divm_shift; 148 u8 override_divp_shift; 149 }; 150 151 #define MAX_PLL_MISC_REG_COUNT 6 152 153 struct tegra_clk_pll; 154 155 /** 156 * struct tegra_clk_pll_params - PLL parameters 157 * 158 * @input_min: Minimum input frequency 159 * @input_max: Maximum input frequency 160 * @cf_min: Minimum comparison frequency 161 * @cf_max: Maximum comparison frequency 162 * @vco_min: Minimum VCO frequency 163 * @vco_max: Maximum VCO frequency 164 * @base_reg: PLL base reg offset 165 * @misc_reg: PLL misc reg offset 166 * @lock_reg: PLL lock reg offset 167 * @lock_mask: Bitmask for PLL lock status 168 * @lock_enable_bit_idx: Bit index to enable PLL lock 169 * @iddq_reg: PLL IDDQ register offset 170 * @iddq_bit_idx: Bit index to enable PLL IDDQ 171 * @reset_reg: Register offset of where RESET bit is 172 * @reset_bit_idx: Shift of reset bit in reset_reg 173 * @sdm_din_reg: Register offset where SDM settings are 174 * @sdm_din_mask: Mask of SDM divider bits 175 * @sdm_ctrl_reg: Register offset where SDM enable is 176 * @sdm_ctrl_en_mask: Mask of SDM enable bit 177 * @ssc_ctrl_reg: Register offset where SSC settings are 178 * @ssc_ctrl_en_mask: Mask of SSC enable bit 179 * @aux_reg: AUX register offset 180 * @dyn_ramp_reg: Dynamic ramp control register offset 181 * @ext_misc_reg: Miscellaneous control register offsets 182 * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) 183 * @pmc_divp_reg: p divider PMC override register offset (PLLM) 184 * @flags: PLL flags 185 * @stepa_shift: Dynamic ramp step A field shift 186 * @stepb_shift: Dynamic ramp step B field shift 187 * @lock_delay: Delay in us if PLL lock is not used 188 * @max_p: maximum value for the p divider 189 * @defaults_set: Boolean signaling all reg defaults for PLL set. 190 * @pdiv_tohw: mapping of p divider to register values 191 * @div_nmp: offsets and widths on n, m and p fields 192 * @freq_table: array of frequencies supported by PLL 193 * @fixed_rate: PLL rate if it is fixed 194 * @mdiv_default: Default value for fixed mdiv for this PLL 195 * @round_p_to_pdiv: Callback used to round p to the closed pdiv 196 * @set_gain: Callback to adjust N div for SDM enabled 197 * PLL's based on fractional divider value. 198 * @calc_rate: Callback used to change how out of table 199 * rates (dividers and multipler) are calculated. 200 * @adjust_vco: Callback to adjust the programming range of the 201 * divider range (if SDM is present) 202 * @set_defaults: Callback which will try to initialize PLL 203 * registers to sane default values. This is first 204 * tried during PLL registration, but if the PLL 205 * is already enabled, it will be done the first 206 * time the rate is changed while the PLL is 207 * disabled. 208 * @dyn_ramp: Callback which can be used to define a custom 209 * dynamic ramp function for a given PLL. 210 * 211 * Flags: 212 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 213 * PLL locking. If not set it will use lock_delay value to wait. 214 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 215 * to be programmed to change output frequency of the PLL. 216 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 217 * to be programmed to change output frequency of the PLL. 218 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 219 * to be programmed to change output frequency of the PLL. 220 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 221 * that it is PLLU and invert post divider value. 222 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 223 * flag indicates that it is PLLM and use override settings. 224 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 225 * of some plls. 226 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 227 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 228 * base register. 229 * TEGRA_PLL_BYPASS - PLL has bypass bit 230 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 231 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv 232 * it may be more accurate (especially if SDM present) 233 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This 234 * flag indicated that it is PLLMB. 235 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output 236 */ 237 struct tegra_clk_pll_params { 238 unsigned long input_min; 239 unsigned long input_max; 240 unsigned long cf_min; 241 unsigned long cf_max; 242 unsigned long vco_min; 243 unsigned long vco_max; 244 245 u32 base_reg; 246 u32 misc_reg; 247 u32 lock_reg; 248 u32 lock_mask; 249 u32 lock_enable_bit_idx; 250 u32 iddq_reg; 251 u32 iddq_bit_idx; 252 u32 reset_reg; 253 u32 reset_bit_idx; 254 u32 sdm_din_reg; 255 u32 sdm_din_mask; 256 u32 sdm_ctrl_reg; 257 u32 sdm_ctrl_en_mask; 258 u32 ssc_ctrl_reg; 259 u32 ssc_ctrl_en_mask; 260 u32 aux_reg; 261 u32 dyn_ramp_reg; 262 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; 263 u32 pmc_divnm_reg; 264 u32 pmc_divp_reg; 265 u32 flags; 266 int stepa_shift; 267 int stepb_shift; 268 int lock_delay; 269 int max_p; 270 bool defaults_set; 271 const struct pdiv_map *pdiv_tohw; 272 struct div_nmp *div_nmp; 273 struct tegra_clk_pll_freq_table *freq_table; 274 unsigned long fixed_rate; 275 u16 mdiv_default; 276 u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); 277 void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); 278 int (*calc_rate)(struct clk_hw *hw, 279 struct tegra_clk_pll_freq_table *cfg, 280 unsigned long rate, unsigned long parent_rate); 281 unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, 282 unsigned long parent_rate); 283 void (*set_defaults)(struct tegra_clk_pll *pll); 284 int (*dyn_ramp)(struct tegra_clk_pll *pll, 285 struct tegra_clk_pll_freq_table *cfg); 286 }; 287 288 #define TEGRA_PLL_USE_LOCK BIT(0) 289 #define TEGRA_PLL_HAS_CPCON BIT(1) 290 #define TEGRA_PLL_SET_LFCON BIT(2) 291 #define TEGRA_PLL_SET_DCCON BIT(3) 292 #define TEGRA_PLLU BIT(4) 293 #define TEGRA_PLLM BIT(5) 294 #define TEGRA_PLL_FIXED BIT(6) 295 #define TEGRA_PLLE_CONFIGURE BIT(7) 296 #define TEGRA_PLL_LOCK_MISC BIT(8) 297 #define TEGRA_PLL_BYPASS BIT(9) 298 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 299 #define TEGRA_MDIV_NEW BIT(11) 300 #define TEGRA_PLLMB BIT(12) 301 #define TEGRA_PLL_VCO_OUT BIT(13) 302 303 /** 304 * struct tegra_clk_pll - Tegra PLL clock 305 * 306 * @hw: handle between common and hardware-specifix interfaces 307 * @clk_base: address of CAR controller 308 * @pmc: address of PMC, required to read override bits 309 * @lock: register lock 310 * @params: PLL parameters 311 */ 312 struct tegra_clk_pll { 313 struct clk_hw hw; 314 void __iomem *clk_base; 315 void __iomem *pmc; 316 spinlock_t *lock; 317 struct tegra_clk_pll_params *params; 318 }; 319 320 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 321 322 /** 323 * struct tegra_audio_clk_info - Tegra Audio Clk Information 324 * 325 * @name: name for the audio pll 326 * @pll_params: pll_params for audio pll 327 * @clk_id: clk_ids for the audio pll 328 * @parent: name of the parent of the audio pll 329 */ 330 struct tegra_audio_clk_info { 331 char *name; 332 struct tegra_clk_pll_params *pll_params; 333 int clk_id; 334 char *parent; 335 }; 336 337 extern const struct clk_ops tegra_clk_pll_ops; 338 extern const struct clk_ops tegra_clk_plle_ops; 339 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 340 void __iomem *clk_base, void __iomem *pmc, 341 unsigned long flags, struct tegra_clk_pll_params *pll_params, 342 spinlock_t *lock); 343 344 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 345 void __iomem *clk_base, void __iomem *pmc, 346 unsigned long flags, struct tegra_clk_pll_params *pll_params, 347 spinlock_t *lock); 348 349 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 350 void __iomem *clk_base, void __iomem *pmc, 351 unsigned long flags, 352 struct tegra_clk_pll_params *pll_params, 353 spinlock_t *lock); 354 355 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 356 void __iomem *clk_base, void __iomem *pmc, 357 unsigned long flags, 358 struct tegra_clk_pll_params *pll_params, 359 spinlock_t *lock); 360 361 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 362 void __iomem *clk_base, void __iomem *pmc, 363 unsigned long flags, 364 struct tegra_clk_pll_params *pll_params, 365 spinlock_t *lock); 366 367 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 368 void __iomem *clk_base, void __iomem *pmc, 369 unsigned long flags, 370 struct tegra_clk_pll_params *pll_params, 371 spinlock_t *lock, unsigned long parent_rate); 372 373 struct clk *tegra_clk_register_pllre_tegra210(const char *name, 374 const char *parent_name, void __iomem *clk_base, 375 void __iomem *pmc, unsigned long flags, 376 struct tegra_clk_pll_params *pll_params, 377 spinlock_t *lock, unsigned long parent_rate); 378 379 struct clk *tegra_clk_register_plle_tegra114(const char *name, 380 const char *parent_name, 381 void __iomem *clk_base, unsigned long flags, 382 struct tegra_clk_pll_params *pll_params, 383 spinlock_t *lock); 384 385 struct clk *tegra_clk_register_plle_tegra210(const char *name, 386 const char *parent_name, 387 void __iomem *clk_base, unsigned long flags, 388 struct tegra_clk_pll_params *pll_params, 389 spinlock_t *lock); 390 391 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 392 const char *parent_name, void __iomem *clk_base, 393 void __iomem *pmc, unsigned long flags, 394 struct tegra_clk_pll_params *pll_params, 395 spinlock_t *lock); 396 397 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 398 const char *parent_name, void __iomem *clk_base, 399 unsigned long flags, 400 struct tegra_clk_pll_params *pll_params, 401 spinlock_t *lock); 402 403 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 404 void __iomem *clk_base, unsigned long flags, 405 struct tegra_clk_pll_params *pll_params, 406 spinlock_t *lock); 407 408 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 409 void __iomem *clk_base, void __iomem *pmc, 410 unsigned long flags, 411 struct tegra_clk_pll_params *pll_params, 412 spinlock_t *lock); 413 414 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name, 415 void __iomem *clk_base, unsigned long flags, 416 struct tegra_clk_pll_params *pll_params, 417 spinlock_t *lock); 418 419 struct clk *tegra_clk_register_pllu_tegra114(const char *name, 420 const char *parent_name, 421 void __iomem *clk_base, unsigned long flags, 422 struct tegra_clk_pll_params *pll_params, 423 spinlock_t *lock); 424 425 struct clk *tegra_clk_register_pllu_tegra210(const char *name, 426 const char *parent_name, 427 void __iomem *clk_base, unsigned long flags, 428 struct tegra_clk_pll_params *pll_params, 429 spinlock_t *lock); 430 431 /** 432 * struct tegra_clk_pll_out - PLL divider down clock 433 * 434 * @hw: handle between common and hardware-specific interfaces 435 * @reg: register containing the PLL divider 436 * @enb_bit_idx: bit to enable/disable PLL divider 437 * @rst_bit_idx: bit to reset PLL divider 438 * @lock: register lock 439 * @flags: hardware-specific flags 440 */ 441 struct tegra_clk_pll_out { 442 struct clk_hw hw; 443 void __iomem *reg; 444 u8 enb_bit_idx; 445 u8 rst_bit_idx; 446 spinlock_t *lock; 447 u8 flags; 448 }; 449 450 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 451 452 extern const struct clk_ops tegra_clk_pll_out_ops; 453 struct clk *tegra_clk_register_pll_out(const char *name, 454 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 455 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 456 spinlock_t *lock); 457 458 /** 459 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 460 * 461 * @enb_reg: read the enable status 462 * @enb_set_reg: write 1 to enable clock 463 * @enb_clr_reg: write 1 to disable clock 464 * @rst_reg: read the reset status 465 * @rst_set_reg: write 1 to assert the reset of peripheral 466 * @rst_clr_reg: write 1 to deassert the reset of peripheral 467 */ 468 struct tegra_clk_periph_regs { 469 u32 enb_reg; 470 u32 enb_set_reg; 471 u32 enb_clr_reg; 472 u32 rst_reg; 473 u32 rst_set_reg; 474 u32 rst_clr_reg; 475 }; 476 477 /** 478 * struct tegra_clk_periph_gate - peripheral gate clock 479 * 480 * @magic: magic number to validate type 481 * @hw: handle between common and hardware-specific interfaces 482 * @clk_base: address of CAR controller 483 * @regs: Registers to control the peripheral 484 * @flags: hardware-specific flags 485 * @clk_num: Clock number 486 * @enable_refcnt: array to maintain reference count of the clock 487 * 488 * Flags: 489 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 490 * for this module. 491 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 492 * after clock enable and driver for the module is responsible for 493 * doing reset. 494 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 495 * bus to flush the write operation in apb bus. This flag indicates 496 * that this peripheral is in apb bus. 497 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug 498 */ 499 struct tegra_clk_periph_gate { 500 u32 magic; 501 struct clk_hw hw; 502 void __iomem *clk_base; 503 u8 flags; 504 int clk_num; 505 int *enable_refcnt; 506 const struct tegra_clk_periph_regs *regs; 507 }; 508 509 #define to_clk_periph_gate(_hw) \ 510 container_of(_hw, struct tegra_clk_periph_gate, hw) 511 512 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 513 514 #define TEGRA_PERIPH_NO_RESET BIT(0) 515 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 516 #define TEGRA_PERIPH_ON_APB BIT(2) 517 #define TEGRA_PERIPH_WAR_1005168 BIT(3) 518 #define TEGRA_PERIPH_NO_DIV BIT(4) 519 #define TEGRA_PERIPH_NO_GATE BIT(5) 520 521 extern const struct clk_ops tegra_clk_periph_gate_ops; 522 struct clk *tegra_clk_register_periph_gate(const char *name, 523 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 524 unsigned long flags, int clk_num, int *enable_refcnt); 525 526 struct tegra_clk_periph_fixed { 527 struct clk_hw hw; 528 void __iomem *base; 529 const struct tegra_clk_periph_regs *regs; 530 unsigned int mul; 531 unsigned int div; 532 unsigned int num; 533 }; 534 535 struct clk *tegra_clk_register_periph_fixed(const char *name, 536 const char *parent, 537 unsigned long flags, 538 void __iomem *base, 539 unsigned int mul, 540 unsigned int div, 541 unsigned int num); 542 543 /** 544 * struct clk-periph - peripheral clock 545 * 546 * @magic: magic number to validate type 547 * @hw: handle between common and hardware-specific interfaces 548 * @mux: mux clock 549 * @divider: divider clock 550 * @gate: gate clock 551 * @mux_ops: mux clock ops 552 * @div_ops: divider clock ops 553 * @gate_ops: gate clock ops 554 */ 555 struct tegra_clk_periph { 556 u32 magic; 557 struct clk_hw hw; 558 struct clk_mux mux; 559 struct tegra_clk_frac_div divider; 560 struct tegra_clk_periph_gate gate; 561 562 const struct clk_ops *mux_ops; 563 const struct clk_ops *div_ops; 564 const struct clk_ops *gate_ops; 565 }; 566 567 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 568 569 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 570 571 extern const struct clk_ops tegra_clk_periph_ops; 572 struct clk *tegra_clk_register_periph(const char *name, 573 const char * const *parent_names, int num_parents, 574 struct tegra_clk_periph *periph, void __iomem *clk_base, 575 u32 offset, unsigned long flags); 576 struct clk *tegra_clk_register_periph_nodiv(const char *name, 577 const char * const *parent_names, int num_parents, 578 struct tegra_clk_periph *periph, void __iomem *clk_base, 579 u32 offset); 580 581 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 582 _div_shift, _div_width, _div_frac_width, \ 583 _div_flags, _clk_num,\ 584 _gate_flags, _table, _lock) \ 585 { \ 586 .mux = { \ 587 .flags = _mux_flags, \ 588 .shift = _mux_shift, \ 589 .mask = _mux_mask, \ 590 .table = _table, \ 591 .lock = _lock, \ 592 }, \ 593 .divider = { \ 594 .flags = _div_flags, \ 595 .shift = _div_shift, \ 596 .width = _div_width, \ 597 .frac_width = _div_frac_width, \ 598 .lock = _lock, \ 599 }, \ 600 .gate = { \ 601 .flags = _gate_flags, \ 602 .clk_num = _clk_num, \ 603 }, \ 604 .mux_ops = &clk_mux_ops, \ 605 .div_ops = &tegra_clk_frac_div_ops, \ 606 .gate_ops = &tegra_clk_periph_gate_ops, \ 607 } 608 609 struct tegra_periph_init_data { 610 const char *name; 611 int clk_id; 612 union { 613 const char *const *parent_names; 614 const char *parent_name; 615 } p; 616 int num_parents; 617 struct tegra_clk_periph periph; 618 u32 offset; 619 const char *con_id; 620 const char *dev_id; 621 unsigned long flags; 622 }; 623 624 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 625 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 626 _div_width, _div_frac_width, _div_flags, \ 627 _clk_num, _gate_flags, _clk_id, _table, \ 628 _flags, _lock) \ 629 { \ 630 .name = _name, \ 631 .clk_id = _clk_id, \ 632 .p.parent_names = _parent_names, \ 633 .num_parents = ARRAY_SIZE(_parent_names), \ 634 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 635 _mux_flags, _div_shift, \ 636 _div_width, _div_frac_width, \ 637 _div_flags, _clk_num, \ 638 _gate_flags, _table, _lock), \ 639 .offset = _offset, \ 640 .con_id = _con_id, \ 641 .dev_id = _dev_id, \ 642 .flags = _flags \ 643 } 644 645 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 646 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 647 _div_width, _div_frac_width, _div_flags, \ 648 _clk_num, _gate_flags, _clk_id) \ 649 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 650 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 651 _div_shift, _div_width, _div_frac_width, _div_flags, \ 652 _clk_num, _gate_flags, _clk_id,\ 653 NULL, 0, NULL) 654 655 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, 656 struct tegra_periph_init_data *init); 657 658 /** 659 * struct clk_super_mux - super clock 660 * 661 * @hw: handle between common and hardware-specific interfaces 662 * @reg: register controlling multiplexer 663 * @width: width of the multiplexer bit field 664 * @flags: hardware-specific flags 665 * @div2_index: bit controlling divide-by-2 666 * @pllx_index: PLLX index in the parent list 667 * @lock: register lock 668 * 669 * Flags: 670 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 671 * that this is LP cluster clock. 672 */ 673 struct tegra_clk_super_mux { 674 struct clk_hw hw; 675 void __iomem *reg; 676 struct tegra_clk_frac_div frac_div; 677 const struct clk_ops *div_ops; 678 u8 width; 679 u8 flags; 680 u8 div2_index; 681 u8 pllx_index; 682 spinlock_t *lock; 683 }; 684 685 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 686 687 #define TEGRA_DIVIDER_2 BIT(0) 688 689 extern const struct clk_ops tegra_clk_super_ops; 690 struct clk *tegra_clk_register_super_mux(const char *name, 691 const char **parent_names, u8 num_parents, 692 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 693 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 694 struct clk *tegra_clk_register_super_clk(const char *name, 695 const char * const *parent_names, u8 num_parents, 696 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 697 spinlock_t *lock); 698 699 /** 700 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC 701 * 702 * @hw: handle between common and hardware-specific interfaces 703 * @reg: register controlling mux and divider 704 * @flags: hardware-specific flags 705 * @lock: optional register lock 706 * @gate: gate clock 707 * @gate_ops: gate clock ops 708 */ 709 struct tegra_sdmmc_mux { 710 struct clk_hw hw; 711 void __iomem *reg; 712 spinlock_t *lock; 713 const struct clk_ops *gate_ops; 714 struct tegra_clk_periph_gate gate; 715 u8 div_flags; 716 }; 717 718 #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) 719 720 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, 721 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, 722 unsigned long flags, void *lock); 723 724 /** 725 * struct clk_init_table - clock initialization table 726 * @clk_id: clock id as mentioned in device tree bindings 727 * @parent_id: parent clock id as mentioned in device tree bindings 728 * @rate: rate to set 729 * @state: enable/disable 730 */ 731 struct tegra_clk_init_table { 732 unsigned int clk_id; 733 unsigned int parent_id; 734 unsigned long rate; 735 int state; 736 }; 737 738 /** 739 * struct clk_duplicate - duplicate clocks 740 * @clk_id: clock id as mentioned in device tree bindings 741 * @lookup: duplicate lookup entry for the clock 742 */ 743 struct tegra_clk_duplicate { 744 int clk_id; 745 struct clk_lookup lookup; 746 }; 747 748 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 749 { \ 750 .clk_id = _clk_id, \ 751 .lookup = { \ 752 .dev_id = _dev, \ 753 .con_id = _con, \ 754 }, \ 755 } 756 757 struct tegra_clk { 758 int dt_id; 759 bool present; 760 }; 761 762 struct tegra_devclk { 763 int dt_id; 764 char *dev_id; 765 char *con_id; 766 }; 767 768 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long), 769 int (*deassert)(unsigned long)); 770 771 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 772 struct clk *clks[], int clk_max); 773 774 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 775 struct clk *clks[], int clk_max); 776 777 const struct tegra_clk_periph_regs *get_reg_bank(int clkid); 778 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); 779 780 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); 781 782 void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get); 783 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 784 785 void tegra_audio_clk_init(void __iomem *clk_base, 786 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 787 struct tegra_audio_clk_info *audio_info, 788 unsigned int num_plls, unsigned long sync_max_rate); 789 790 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, 791 struct tegra_clk *tegra_clks, 792 struct tegra_clk_pll_params *pll_params); 793 794 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); 795 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); 796 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 797 unsigned long *input_freqs, unsigned int num, 798 unsigned int clk_m_div, unsigned long *osc_freq, 799 unsigned long *pll_ref_freq); 800 void tegra_super_clk_gen4_init(void __iomem *clk_base, 801 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 802 struct tegra_clk_pll_params *pll_params); 803 void tegra_super_clk_gen5_init(void __iomem *clk_base, 804 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 805 struct tegra_clk_pll_params *pll_params); 806 807 #ifdef CONFIG_TEGRA_CLK_EMC 808 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 809 spinlock_t *lock); 810 #else 811 static inline struct clk *tegra_clk_register_emc(void __iomem *base, 812 struct device_node *np, 813 spinlock_t *lock) 814 { 815 return NULL; 816 } 817 #endif 818 819 void tegra114_clock_tune_cpu_trimmers_high(void); 820 void tegra114_clock_tune_cpu_trimmers_low(void); 821 void tegra114_clock_tune_cpu_trimmers_init(void); 822 void tegra114_clock_assert_dfll_dvco_reset(void); 823 void tegra114_clock_deassert_dfll_dvco_reset(void); 824 825 typedef void (*tegra_clk_apply_init_table_func)(void); 826 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 827 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); 828 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); 829 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); 830 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, 831 u8 frac_width, u8 flags); 832 833 834 /* Combined read fence with delay */ 835 #define fence_udelay(delay, reg) \ 836 do { \ 837 readl(reg); \ 838 udelay(delay); \ 839 } while (0) 840 841 #endif /* TEGRA_CLK_H */ 842