1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __TEGRA_CLK_H 18 #define __TEGRA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30 struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34 }; 35 36 #define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39 extern const struct clk_ops tegra_clk_sync_source_ops; 40 extern int *periph_clk_enb_refcnt; 41 42 struct clk *tegra_clk_register_sync_source(const char *name, 43 unsigned long fixed_rate, unsigned long max_rate); 44 45 /** 46 * struct tegra_clk_frac_div - fractional divider clock 47 * 48 * @hw: handle between common and hardware-specific interfaces 49 * @reg: register containing divider 50 * @flags: hardware-specific flags 51 * @shift: shift to the divider bit field 52 * @width: width of the divider bit field 53 * @frac_width: width of the fractional bit field 54 * @lock: register lock 55 * 56 * Flags: 57 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 58 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 59 * flag indicates that this divider is for fixed rate PLL. 60 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 61 * fraction bit is set. This flags indicates to calculate divider for which 62 * fracton bit will be zero. 63 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 64 * set when divider value is not 0. This flags indicates that the divider 65 * is for UART module. 66 */ 67 struct tegra_clk_frac_div { 68 struct clk_hw hw; 69 void __iomem *reg; 70 u8 flags; 71 u8 shift; 72 u8 width; 73 u8 frac_width; 74 spinlock_t *lock; 75 }; 76 77 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 78 79 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 80 #define TEGRA_DIVIDER_FIXED BIT(1) 81 #define TEGRA_DIVIDER_INT BIT(2) 82 #define TEGRA_DIVIDER_UART BIT(3) 83 84 extern const struct clk_ops tegra_clk_frac_div_ops; 85 struct clk *tegra_clk_register_divider(const char *name, 86 const char *parent_name, void __iomem *reg, 87 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 88 u8 frac_width, spinlock_t *lock); 89 90 /* 91 * Tegra PLL: 92 * 93 * In general, there are 3 requirements for each PLL 94 * that SW needs to be comply with. 95 * (1) Input frequency range (REF). 96 * (2) Comparison frequency range (CF). CF = REF/DIVM. 97 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 98 * 99 * The final PLL output frequency (FO) = VCO >> DIVP. 100 */ 101 102 /** 103 * struct tegra_clk_pll_freq_table - PLL frequecy table 104 * 105 * @input_rate: input rate from source 106 * @output_rate: output rate from PLL for the input rate 107 * @n: feedback divider 108 * @m: input divider 109 * @p: post divider 110 * @cpcon: charge pump current 111 */ 112 struct tegra_clk_pll_freq_table { 113 unsigned long input_rate; 114 unsigned long output_rate; 115 u16 n; 116 u16 m; 117 u8 p; 118 u8 cpcon; 119 }; 120 121 /** 122 * struct pdiv_map - map post divider to hw value 123 * 124 * @pdiv: post divider 125 * @hw_val: value to be written to the PLL hw 126 */ 127 struct pdiv_map { 128 u8 pdiv; 129 u8 hw_val; 130 }; 131 132 /** 133 * struct div_nmp - offset and width of m,n and p fields 134 * 135 * @divn_shift: shift to the feedback divider bit field 136 * @divn_width: width of the feedback divider bit field 137 * @divm_shift: shift to the input divider bit field 138 * @divm_width: width of the input divider bit field 139 * @divp_shift: shift to the post divider bit field 140 * @divp_width: width of the post divider bit field 141 * @override_divn_shift: shift to the feedback divider bitfield in override reg 142 * @override_divm_shift: shift to the input divider bitfield in override reg 143 * @override_divp_shift: shift to the post divider bitfield in override reg 144 */ 145 struct div_nmp { 146 u8 divn_shift; 147 u8 divn_width; 148 u8 divm_shift; 149 u8 divm_width; 150 u8 divp_shift; 151 u8 divp_width; 152 u8 override_divn_shift; 153 u8 override_divm_shift; 154 u8 override_divp_shift; 155 }; 156 157 /** 158 * struct clk_pll_params - PLL parameters 159 * 160 * @input_min: Minimum input frequency 161 * @input_max: Maximum input frequency 162 * @cf_min: Minimum comparison frequency 163 * @cf_max: Maximum comparison frequency 164 * @vco_min: Minimum VCO frequency 165 * @vco_max: Maximum VCO frequency 166 * @base_reg: PLL base reg offset 167 * @misc_reg: PLL misc reg offset 168 * @lock_reg: PLL lock reg offset 169 * @lock_bit_idx: Bit index for PLL lock status 170 * @lock_enable_bit_idx: Bit index to enable PLL lock 171 * @lock_delay: Delay in us if PLL lock is not used 172 */ 173 struct tegra_clk_pll_params { 174 unsigned long input_min; 175 unsigned long input_max; 176 unsigned long cf_min; 177 unsigned long cf_max; 178 unsigned long vco_min; 179 unsigned long vco_max; 180 181 u32 base_reg; 182 u32 misc_reg; 183 u32 lock_reg; 184 u32 lock_mask; 185 u32 lock_enable_bit_idx; 186 u32 iddq_reg; 187 u32 iddq_bit_idx; 188 u32 aux_reg; 189 u32 dyn_ramp_reg; 190 u32 ext_misc_reg[3]; 191 u32 pmc_divnm_reg; 192 u32 pmc_divp_reg; 193 u32 flags; 194 int stepa_shift; 195 int stepb_shift; 196 int lock_delay; 197 int max_p; 198 struct pdiv_map *pdiv_tohw; 199 struct div_nmp *div_nmp; 200 struct tegra_clk_pll_freq_table *freq_table; 201 unsigned long fixed_rate; 202 }; 203 204 /** 205 * struct tegra_clk_pll - Tegra PLL clock 206 * 207 * @hw: handle between common and hardware-specifix interfaces 208 * @clk_base: address of CAR controller 209 * @pmc: address of PMC, required to read override bits 210 * @freq_table: array of frequencies supported by PLL 211 * @params: PLL parameters 212 * @flags: PLL flags 213 * @fixed_rate: PLL rate if it is fixed 214 * @lock: register lock 215 * 216 * Flags: 217 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 218 * PLL locking. If not set it will use lock_delay value to wait. 219 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 220 * to be programmed to change output frequency of the PLL. 221 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 222 * to be programmed to change output frequency of the PLL. 223 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 224 * to be programmed to change output frequency of the PLL. 225 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 226 * that it is PLLU and invert post divider value. 227 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 228 * flag indicates that it is PLLM and use override settings. 229 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 230 * of some plls. 231 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 232 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 233 * base register. 234 * TEGRA_PLL_BYPASS - PLL has bypass bit 235 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 236 */ 237 struct tegra_clk_pll { 238 struct clk_hw hw; 239 void __iomem *clk_base; 240 void __iomem *pmc; 241 spinlock_t *lock; 242 struct tegra_clk_pll_params *params; 243 }; 244 245 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 246 247 #define TEGRA_PLL_USE_LOCK BIT(0) 248 #define TEGRA_PLL_HAS_CPCON BIT(1) 249 #define TEGRA_PLL_SET_LFCON BIT(2) 250 #define TEGRA_PLL_SET_DCCON BIT(3) 251 #define TEGRA_PLLU BIT(4) 252 #define TEGRA_PLLM BIT(5) 253 #define TEGRA_PLL_FIXED BIT(6) 254 #define TEGRA_PLLE_CONFIGURE BIT(7) 255 #define TEGRA_PLL_LOCK_MISC BIT(8) 256 #define TEGRA_PLL_BYPASS BIT(9) 257 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 258 259 extern const struct clk_ops tegra_clk_pll_ops; 260 extern const struct clk_ops tegra_clk_plle_ops; 261 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 262 void __iomem *clk_base, void __iomem *pmc, 263 unsigned long flags, struct tegra_clk_pll_params *pll_params, 264 spinlock_t *lock); 265 266 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 267 void __iomem *clk_base, void __iomem *pmc, 268 unsigned long flags, struct tegra_clk_pll_params *pll_params, 269 spinlock_t *lock); 270 271 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 272 void __iomem *clk_base, void __iomem *pmc, 273 unsigned long flags, 274 struct tegra_clk_pll_params *pll_params, 275 spinlock_t *lock); 276 277 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 278 void __iomem *clk_base, void __iomem *pmc, 279 unsigned long flags, 280 struct tegra_clk_pll_params *pll_params, 281 spinlock_t *lock); 282 283 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 284 void __iomem *clk_base, void __iomem *pmc, 285 unsigned long flags, 286 struct tegra_clk_pll_params *pll_params, 287 spinlock_t *lock); 288 289 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 290 void __iomem *clk_base, void __iomem *pmc, 291 unsigned long flags, 292 struct tegra_clk_pll_params *pll_params, 293 spinlock_t *lock, unsigned long parent_rate); 294 295 struct clk *tegra_clk_register_plle_tegra114(const char *name, 296 const char *parent_name, 297 void __iomem *clk_base, unsigned long flags, 298 struct tegra_clk_pll_params *pll_params, 299 spinlock_t *lock); 300 301 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 302 void __iomem *clk_base, unsigned long flags, 303 struct tegra_clk_pll_params *pll_params, 304 spinlock_t *lock); 305 306 /** 307 * struct tegra_clk_pll_out - PLL divider down clock 308 * 309 * @hw: handle between common and hardware-specific interfaces 310 * @reg: register containing the PLL divider 311 * @enb_bit_idx: bit to enable/disable PLL divider 312 * @rst_bit_idx: bit to reset PLL divider 313 * @lock: register lock 314 * @flags: hardware-specific flags 315 */ 316 struct tegra_clk_pll_out { 317 struct clk_hw hw; 318 void __iomem *reg; 319 u8 enb_bit_idx; 320 u8 rst_bit_idx; 321 spinlock_t *lock; 322 u8 flags; 323 }; 324 325 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 326 327 extern const struct clk_ops tegra_clk_pll_out_ops; 328 struct clk *tegra_clk_register_pll_out(const char *name, 329 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 330 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 331 spinlock_t *lock); 332 333 /** 334 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 335 * 336 * @enb_reg: read the enable status 337 * @enb_set_reg: write 1 to enable clock 338 * @enb_clr_reg: write 1 to disable clock 339 * @rst_reg: read the reset status 340 * @rst_set_reg: write 1 to assert the reset of peripheral 341 * @rst_clr_reg: write 1 to deassert the reset of peripheral 342 */ 343 struct tegra_clk_periph_regs { 344 u32 enb_reg; 345 u32 enb_set_reg; 346 u32 enb_clr_reg; 347 u32 rst_reg; 348 u32 rst_set_reg; 349 u32 rst_clr_reg; 350 }; 351 352 /** 353 * struct tegra_clk_periph_gate - peripheral gate clock 354 * 355 * @magic: magic number to validate type 356 * @hw: handle between common and hardware-specific interfaces 357 * @clk_base: address of CAR controller 358 * @regs: Registers to control the peripheral 359 * @flags: hardware-specific flags 360 * @clk_num: Clock number 361 * @enable_refcnt: array to maintain reference count of the clock 362 * 363 * Flags: 364 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 365 * for this module. 366 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 367 * after clock enable and driver for the module is responsible for 368 * doing reset. 369 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 370 * bus to flush the write operation in apb bus. This flag indicates 371 * that this peripheral is in apb bus. 372 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug 373 */ 374 struct tegra_clk_periph_gate { 375 u32 magic; 376 struct clk_hw hw; 377 void __iomem *clk_base; 378 u8 flags; 379 int clk_num; 380 int *enable_refcnt; 381 struct tegra_clk_periph_regs *regs; 382 }; 383 384 #define to_clk_periph_gate(_hw) \ 385 container_of(_hw, struct tegra_clk_periph_gate, hw) 386 387 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 388 389 #define TEGRA_PERIPH_NO_RESET BIT(0) 390 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 391 #define TEGRA_PERIPH_ON_APB BIT(2) 392 #define TEGRA_PERIPH_WAR_1005168 BIT(3) 393 #define TEGRA_PERIPH_NO_DIV BIT(4) 394 #define TEGRA_PERIPH_NO_GATE BIT(5) 395 396 extern const struct clk_ops tegra_clk_periph_gate_ops; 397 struct clk *tegra_clk_register_periph_gate(const char *name, 398 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 399 unsigned long flags, int clk_num, int *enable_refcnt); 400 401 /** 402 * struct clk-periph - peripheral clock 403 * 404 * @magic: magic number to validate type 405 * @hw: handle between common and hardware-specific interfaces 406 * @mux: mux clock 407 * @divider: divider clock 408 * @gate: gate clock 409 * @mux_ops: mux clock ops 410 * @div_ops: divider clock ops 411 * @gate_ops: gate clock ops 412 */ 413 struct tegra_clk_periph { 414 u32 magic; 415 struct clk_hw hw; 416 struct clk_mux mux; 417 struct tegra_clk_frac_div divider; 418 struct tegra_clk_periph_gate gate; 419 420 const struct clk_ops *mux_ops; 421 const struct clk_ops *div_ops; 422 const struct clk_ops *gate_ops; 423 }; 424 425 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 426 427 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 428 429 extern const struct clk_ops tegra_clk_periph_ops; 430 struct clk *tegra_clk_register_periph(const char *name, 431 const char **parent_names, int num_parents, 432 struct tegra_clk_periph *periph, void __iomem *clk_base, 433 u32 offset, unsigned long flags); 434 struct clk *tegra_clk_register_periph_nodiv(const char *name, 435 const char **parent_names, int num_parents, 436 struct tegra_clk_periph *periph, void __iomem *clk_base, 437 u32 offset); 438 439 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 440 _div_shift, _div_width, _div_frac_width, \ 441 _div_flags, _clk_num,\ 442 _gate_flags, _table, _lock) \ 443 { \ 444 .mux = { \ 445 .flags = _mux_flags, \ 446 .shift = _mux_shift, \ 447 .mask = _mux_mask, \ 448 .table = _table, \ 449 .lock = _lock, \ 450 }, \ 451 .divider = { \ 452 .flags = _div_flags, \ 453 .shift = _div_shift, \ 454 .width = _div_width, \ 455 .frac_width = _div_frac_width, \ 456 .lock = _lock, \ 457 }, \ 458 .gate = { \ 459 .flags = _gate_flags, \ 460 .clk_num = _clk_num, \ 461 }, \ 462 .mux_ops = &clk_mux_ops, \ 463 .div_ops = &tegra_clk_frac_div_ops, \ 464 .gate_ops = &tegra_clk_periph_gate_ops, \ 465 } 466 467 struct tegra_periph_init_data { 468 const char *name; 469 int clk_id; 470 union { 471 const char **parent_names; 472 const char *parent_name; 473 } p; 474 int num_parents; 475 struct tegra_clk_periph periph; 476 u32 offset; 477 const char *con_id; 478 const char *dev_id; 479 unsigned long flags; 480 }; 481 482 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 483 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 484 _div_width, _div_frac_width, _div_flags, \ 485 _clk_num, _gate_flags, _clk_id, _table, \ 486 _flags, _lock) \ 487 { \ 488 .name = _name, \ 489 .clk_id = _clk_id, \ 490 .p.parent_names = _parent_names, \ 491 .num_parents = ARRAY_SIZE(_parent_names), \ 492 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 493 _mux_flags, _div_shift, \ 494 _div_width, _div_frac_width, \ 495 _div_flags, _clk_num, \ 496 _gate_flags, _table, _lock), \ 497 .offset = _offset, \ 498 .con_id = _con_id, \ 499 .dev_id = _dev_id, \ 500 .flags = _flags \ 501 } 502 503 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 504 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 505 _div_width, _div_frac_width, _div_flags, \ 506 _clk_num, _gate_flags, _clk_id) \ 507 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 508 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 509 _div_shift, _div_width, _div_frac_width, _div_flags, \ 510 _clk_num, _gate_flags, _clk_id,\ 511 NULL, 0, NULL) 512 513 /** 514 * struct clk_super_mux - super clock 515 * 516 * @hw: handle between common and hardware-specific interfaces 517 * @reg: register controlling multiplexer 518 * @width: width of the multiplexer bit field 519 * @flags: hardware-specific flags 520 * @div2_index: bit controlling divide-by-2 521 * @pllx_index: PLLX index in the parent list 522 * @lock: register lock 523 * 524 * Flags: 525 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 526 * that this is LP cluster clock. 527 */ 528 struct tegra_clk_super_mux { 529 struct clk_hw hw; 530 void __iomem *reg; 531 u8 width; 532 u8 flags; 533 u8 div2_index; 534 u8 pllx_index; 535 spinlock_t *lock; 536 }; 537 538 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 539 540 #define TEGRA_DIVIDER_2 BIT(0) 541 542 extern const struct clk_ops tegra_clk_super_ops; 543 struct clk *tegra_clk_register_super_mux(const char *name, 544 const char **parent_names, u8 num_parents, 545 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 546 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 547 548 /** 549 * struct clk_init_tabel - clock initialization table 550 * @clk_id: clock id as mentioned in device tree bindings 551 * @parent_id: parent clock id as mentioned in device tree bindings 552 * @rate: rate to set 553 * @state: enable/disable 554 */ 555 struct tegra_clk_init_table { 556 unsigned int clk_id; 557 unsigned int parent_id; 558 unsigned long rate; 559 int state; 560 }; 561 562 /** 563 * struct clk_duplicate - duplicate clocks 564 * @clk_id: clock id as mentioned in device tree bindings 565 * @lookup: duplicate lookup entry for the clock 566 */ 567 struct tegra_clk_duplicate { 568 int clk_id; 569 struct clk_lookup lookup; 570 }; 571 572 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 573 { \ 574 .clk_id = _clk_id, \ 575 .lookup = { \ 576 .dev_id = _dev, \ 577 .con_id = _con, \ 578 }, \ 579 } 580 581 struct tegra_clk { 582 int dt_id; 583 bool present; 584 }; 585 586 struct tegra_devclk { 587 int dt_id; 588 char *dev_id; 589 char *con_id; 590 }; 591 592 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 593 struct clk *clks[], int clk_max); 594 595 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 596 struct clk *clks[], int clk_max); 597 598 struct tegra_clk_periph_regs *get_reg_bank(int clkid); 599 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); 600 601 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); 602 603 void tegra_add_of_provider(struct device_node *np); 604 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 605 606 void tegra_audio_clk_init(void __iomem *clk_base, 607 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 608 struct tegra_clk_pll_params *pll_params); 609 610 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, 611 struct tegra_clk *tegra_clks, 612 struct tegra_clk_pll_params *pll_params); 613 614 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); 615 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); 616 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, 617 unsigned long *input_freqs, int num, 618 unsigned long *osc_freq, 619 unsigned long *pll_ref_freq); 620 void tegra_super_clk_gen4_init(void __iomem *clk_base, 621 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 622 struct tegra_clk_pll_params *pll_params); 623 624 void tegra114_clock_tune_cpu_trimmers_high(void); 625 void tegra114_clock_tune_cpu_trimmers_low(void); 626 void tegra114_clock_tune_cpu_trimmers_init(void); 627 void tegra114_clock_assert_dfll_dvco_reset(void); 628 void tegra114_clock_deassert_dfll_dvco_reset(void); 629 630 typedef void (*tegra_clk_apply_init_table_func)(void); 631 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 632 633 #endif /* TEGRA_CLK_H */ 634