1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/clkdev.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/delay.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/clk/tegra.h> 24 #include <linux/reset-controller.h> 25 26 #include <soc/tegra/fuse.h> 27 28 #include "clk.h" 29 30 #define CLK_OUT_ENB_L 0x010 31 #define CLK_OUT_ENB_H 0x014 32 #define CLK_OUT_ENB_U 0x018 33 #define CLK_OUT_ENB_V 0x360 34 #define CLK_OUT_ENB_W 0x364 35 #define CLK_OUT_ENB_X 0x280 36 #define CLK_OUT_ENB_Y 0x298 37 #define CLK_OUT_ENB_SET_L 0x320 38 #define CLK_OUT_ENB_CLR_L 0x324 39 #define CLK_OUT_ENB_SET_H 0x328 40 #define CLK_OUT_ENB_CLR_H 0x32c 41 #define CLK_OUT_ENB_SET_U 0x330 42 #define CLK_OUT_ENB_CLR_U 0x334 43 #define CLK_OUT_ENB_SET_V 0x440 44 #define CLK_OUT_ENB_CLR_V 0x444 45 #define CLK_OUT_ENB_SET_W 0x448 46 #define CLK_OUT_ENB_CLR_W 0x44c 47 #define CLK_OUT_ENB_SET_X 0x284 48 #define CLK_OUT_ENB_CLR_X 0x288 49 #define CLK_OUT_ENB_SET_Y 0x29c 50 #define CLK_OUT_ENB_CLR_Y 0x2a0 51 52 #define RST_DEVICES_L 0x004 53 #define RST_DEVICES_H 0x008 54 #define RST_DEVICES_U 0x00C 55 #define RST_DEVICES_V 0x358 56 #define RST_DEVICES_W 0x35C 57 #define RST_DEVICES_X 0x28C 58 #define RST_DEVICES_Y 0x2a4 59 #define RST_DEVICES_SET_L 0x300 60 #define RST_DEVICES_CLR_L 0x304 61 #define RST_DEVICES_SET_H 0x308 62 #define RST_DEVICES_CLR_H 0x30c 63 #define RST_DEVICES_SET_U 0x310 64 #define RST_DEVICES_CLR_U 0x314 65 #define RST_DEVICES_SET_V 0x430 66 #define RST_DEVICES_CLR_V 0x434 67 #define RST_DEVICES_SET_W 0x438 68 #define RST_DEVICES_CLR_W 0x43c 69 #define RST_DEVICES_SET_X 0x290 70 #define RST_DEVICES_CLR_X 0x294 71 #define RST_DEVICES_SET_Y 0x2a8 72 #define RST_DEVICES_CLR_Y 0x2ac 73 74 /* Global data of Tegra CPU CAR ops */ 75 static struct tegra_cpu_car_ops dummy_car_ops; 76 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; 77 78 int *periph_clk_enb_refcnt; 79 static int periph_banks; 80 static struct clk **clks; 81 static int clk_num; 82 static struct clk_onecell_data clk_data; 83 84 /* Handlers for SoC-specific reset lines */ 85 static int (*special_reset_assert)(unsigned long); 86 static int (*special_reset_deassert)(unsigned long); 87 static unsigned int num_special_reset; 88 89 static const struct tegra_clk_periph_regs periph_regs[] = { 90 [0] = { 91 .enb_reg = CLK_OUT_ENB_L, 92 .enb_set_reg = CLK_OUT_ENB_SET_L, 93 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 94 .rst_reg = RST_DEVICES_L, 95 .rst_set_reg = RST_DEVICES_SET_L, 96 .rst_clr_reg = RST_DEVICES_CLR_L, 97 }, 98 [1] = { 99 .enb_reg = CLK_OUT_ENB_H, 100 .enb_set_reg = CLK_OUT_ENB_SET_H, 101 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 102 .rst_reg = RST_DEVICES_H, 103 .rst_set_reg = RST_DEVICES_SET_H, 104 .rst_clr_reg = RST_DEVICES_CLR_H, 105 }, 106 [2] = { 107 .enb_reg = CLK_OUT_ENB_U, 108 .enb_set_reg = CLK_OUT_ENB_SET_U, 109 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 110 .rst_reg = RST_DEVICES_U, 111 .rst_set_reg = RST_DEVICES_SET_U, 112 .rst_clr_reg = RST_DEVICES_CLR_U, 113 }, 114 [3] = { 115 .enb_reg = CLK_OUT_ENB_V, 116 .enb_set_reg = CLK_OUT_ENB_SET_V, 117 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 118 .rst_reg = RST_DEVICES_V, 119 .rst_set_reg = RST_DEVICES_SET_V, 120 .rst_clr_reg = RST_DEVICES_CLR_V, 121 }, 122 [4] = { 123 .enb_reg = CLK_OUT_ENB_W, 124 .enb_set_reg = CLK_OUT_ENB_SET_W, 125 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 126 .rst_reg = RST_DEVICES_W, 127 .rst_set_reg = RST_DEVICES_SET_W, 128 .rst_clr_reg = RST_DEVICES_CLR_W, 129 }, 130 [5] = { 131 .enb_reg = CLK_OUT_ENB_X, 132 .enb_set_reg = CLK_OUT_ENB_SET_X, 133 .enb_clr_reg = CLK_OUT_ENB_CLR_X, 134 .rst_reg = RST_DEVICES_X, 135 .rst_set_reg = RST_DEVICES_SET_X, 136 .rst_clr_reg = RST_DEVICES_CLR_X, 137 }, 138 [6] = { 139 .enb_reg = CLK_OUT_ENB_Y, 140 .enb_set_reg = CLK_OUT_ENB_SET_Y, 141 .enb_clr_reg = CLK_OUT_ENB_CLR_Y, 142 .rst_reg = RST_DEVICES_Y, 143 .rst_set_reg = RST_DEVICES_SET_Y, 144 .rst_clr_reg = RST_DEVICES_CLR_Y, 145 }, 146 }; 147 148 static void __iomem *clk_base; 149 150 static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev, 151 unsigned long id) 152 { 153 /* 154 * If peripheral is on the APB bus then we must read the APB bus to 155 * flush the write operation in apb bus. This will avoid peripheral 156 * access after disabling clock. Since the reset driver has no 157 * knowledge of which reset IDs represent which devices, simply do 158 * this all the time. 159 */ 160 tegra_read_chipid(); 161 162 if (id < periph_banks * 32) { 163 writel_relaxed(BIT(id % 32), 164 clk_base + periph_regs[id / 32].rst_set_reg); 165 return 0; 166 } else if (id < periph_banks * 32 + num_special_reset) { 167 return special_reset_assert(id); 168 } 169 170 return -EINVAL; 171 } 172 173 static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev, 174 unsigned long id) 175 { 176 if (id < periph_banks * 32) { 177 writel_relaxed(BIT(id % 32), 178 clk_base + periph_regs[id / 32].rst_clr_reg); 179 return 0; 180 } else if (id < periph_banks * 32 + num_special_reset) { 181 return special_reset_deassert(id); 182 } 183 184 return -EINVAL; 185 } 186 187 static int tegra_clk_rst_reset(struct reset_controller_dev *rcdev, 188 unsigned long id) 189 { 190 int err; 191 192 err = tegra_clk_rst_assert(rcdev, id); 193 if (err) 194 return err; 195 196 udelay(1); 197 198 return tegra_clk_rst_deassert(rcdev, id); 199 } 200 201 const struct tegra_clk_periph_regs *get_reg_bank(int clkid) 202 { 203 int reg_bank = clkid / 32; 204 205 if (reg_bank < periph_banks) 206 return &periph_regs[reg_bank]; 207 else { 208 WARN_ON(1); 209 return NULL; 210 } 211 } 212 213 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) 214 { 215 clk_base = regs; 216 217 if (WARN_ON(banks > ARRAY_SIZE(periph_regs))) 218 return NULL; 219 220 periph_clk_enb_refcnt = kcalloc(32 * banks, 221 sizeof(*periph_clk_enb_refcnt), 222 GFP_KERNEL); 223 if (!periph_clk_enb_refcnt) 224 return NULL; 225 226 periph_banks = banks; 227 228 clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL); 229 if (!clks) 230 kfree(periph_clk_enb_refcnt); 231 232 clk_num = num; 233 234 return clks; 235 } 236 237 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 238 struct clk *clks[], int clk_max) 239 { 240 struct clk *clk; 241 242 for (; dup_list->clk_id < clk_max; dup_list++) { 243 clk = clks[dup_list->clk_id]; 244 dup_list->lookup.clk = clk; 245 clkdev_add(&dup_list->lookup); 246 } 247 } 248 249 void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, 250 struct clk *clks[], int clk_max) 251 { 252 struct clk *clk; 253 254 for (; tbl->clk_id < clk_max; tbl++) { 255 clk = clks[tbl->clk_id]; 256 if (IS_ERR_OR_NULL(clk)) { 257 pr_err("%s: invalid entry %ld in clks array for id %d\n", 258 __func__, PTR_ERR(clk), tbl->clk_id); 259 WARN_ON(1); 260 261 continue; 262 } 263 264 if (tbl->parent_id < clk_max) { 265 struct clk *parent = clks[tbl->parent_id]; 266 if (clk_set_parent(clk, parent)) { 267 pr_err("%s: Failed to set parent %s of %s\n", 268 __func__, __clk_get_name(parent), 269 __clk_get_name(clk)); 270 WARN_ON(1); 271 } 272 } 273 274 if (tbl->rate) 275 if (clk_set_rate(clk, tbl->rate)) { 276 pr_err("%s: Failed to set rate %lu of %s\n", 277 __func__, tbl->rate, 278 __clk_get_name(clk)); 279 WARN_ON(1); 280 } 281 282 if (tbl->state) 283 if (clk_prepare_enable(clk)) { 284 pr_err("%s: Failed to enable %s\n", __func__, 285 __clk_get_name(clk)); 286 WARN_ON(1); 287 } 288 } 289 } 290 291 static const struct reset_control_ops rst_ops = { 292 .assert = tegra_clk_rst_assert, 293 .deassert = tegra_clk_rst_deassert, 294 .reset = tegra_clk_rst_reset, 295 }; 296 297 static struct reset_controller_dev rst_ctlr = { 298 .ops = &rst_ops, 299 .owner = THIS_MODULE, 300 .of_reset_n_cells = 1, 301 }; 302 303 void __init tegra_add_of_provider(struct device_node *np, 304 void *clk_src_onecell_get) 305 { 306 int i; 307 308 for (i = 0; i < clk_num; i++) { 309 if (IS_ERR(clks[i])) { 310 pr_err 311 ("Tegra clk %d: register failed with %ld\n", 312 i, PTR_ERR(clks[i])); 313 } 314 if (!clks[i]) 315 clks[i] = ERR_PTR(-EINVAL); 316 } 317 318 clk_data.clks = clks; 319 clk_data.clk_num = clk_num; 320 of_clk_add_provider(np, clk_src_onecell_get, &clk_data); 321 322 rst_ctlr.of_node = np; 323 rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset; 324 reset_controller_register(&rst_ctlr); 325 } 326 327 void __init tegra_init_special_resets(unsigned int num, 328 int (*assert)(unsigned long), 329 int (*deassert)(unsigned long)) 330 { 331 num_special_reset = num; 332 special_reset_assert = assert; 333 special_reset_deassert = deassert; 334 } 335 336 void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num) 337 { 338 int i; 339 340 for (i = 0; i < num; i++, dev_clks++) 341 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id, 342 dev_clks->dev_id); 343 344 for (i = 0; i < clk_num; i++) { 345 if (!IS_ERR_OR_NULL(clks[i])) 346 clk_register_clkdev(clks[i], __clk_get_name(clks[i]), 347 "tegra-clk-debug"); 348 } 349 } 350 351 struct clk ** __init tegra_lookup_dt_id(int clk_id, 352 struct tegra_clk *tegra_clk) 353 { 354 if (tegra_clk[clk_id].present) 355 return &clks[tegra_clk[clk_id].dt_id]; 356 else 357 return NULL; 358 } 359 360 tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 361 362 static int __init tegra_clocks_apply_init_table(void) 363 { 364 if (!tegra_clk_apply_init_table) 365 return 0; 366 367 tegra_clk_apply_init_table(); 368 369 return 0; 370 } 371 arch_initcall(tegra_clocks_apply_init_table); 372