1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/delay.h> 19 #include <linux/clk-provider.h> 20 #include <linux/clkdev.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/clk/tegra.h> 24 25 #include <soc/tegra/pmc.h> 26 27 #include <dt-bindings/clock/tegra30-car.h> 28 29 #include "clk.h" 30 #include "clk-id.h" 31 32 #define OSC_CTRL 0x50 33 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 34 #define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 35 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 36 #define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 37 #define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 38 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 39 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 40 #define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 41 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 42 43 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 44 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 45 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 46 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 47 48 #define OSC_FREQ_DET 0x58 49 #define OSC_FREQ_DET_TRIG BIT(31) 50 51 #define OSC_FREQ_DET_STATUS 0x5c 52 #define OSC_FREQ_DET_BUSY BIT(31) 53 #define OSC_FREQ_DET_CNT_MASK 0xffff 54 55 #define CCLKG_BURST_POLICY 0x368 56 #define SUPER_CCLKG_DIVIDER 0x36c 57 #define CCLKLP_BURST_POLICY 0x370 58 #define SUPER_CCLKLP_DIVIDER 0x374 59 #define SCLK_BURST_POLICY 0x028 60 #define SUPER_SCLK_DIVIDER 0x02c 61 62 #define SYSTEM_CLK_RATE 0x030 63 64 #define TEGRA30_CLK_PERIPH_BANKS 5 65 66 #define PLLC_BASE 0x80 67 #define PLLC_MISC 0x8c 68 #define PLLM_BASE 0x90 69 #define PLLM_MISC 0x9c 70 #define PLLP_BASE 0xa0 71 #define PLLP_MISC 0xac 72 #define PLLX_BASE 0xe0 73 #define PLLX_MISC 0xe4 74 #define PLLD_BASE 0xd0 75 #define PLLD_MISC 0xdc 76 #define PLLD2_BASE 0x4b8 77 #define PLLD2_MISC 0x4bc 78 #define PLLE_BASE 0xe8 79 #define PLLE_MISC 0xec 80 #define PLLA_BASE 0xb0 81 #define PLLA_MISC 0xbc 82 #define PLLU_BASE 0xc0 83 #define PLLU_MISC 0xcc 84 85 #define PLL_MISC_LOCK_ENABLE 18 86 #define PLLDU_MISC_LOCK_ENABLE 22 87 #define PLLE_MISC_LOCK_ENABLE 9 88 89 #define PLL_BASE_LOCK BIT(27) 90 #define PLLE_MISC_LOCK BIT(11) 91 92 #define PLLE_AUX 0x48c 93 #define PLLC_OUT 0x84 94 #define PLLM_OUT 0x94 95 #define PLLP_OUTA 0xa4 96 #define PLLP_OUTB 0xa8 97 #define PLLA_OUT 0xb4 98 99 #define AUDIO_SYNC_CLK_I2S0 0x4a0 100 #define AUDIO_SYNC_CLK_I2S1 0x4a4 101 #define AUDIO_SYNC_CLK_I2S2 0x4a8 102 #define AUDIO_SYNC_CLK_I2S3 0x4ac 103 #define AUDIO_SYNC_CLK_I2S4 0x4b0 104 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 105 106 #define CLK_SOURCE_SPDIF_OUT 0x108 107 #define CLK_SOURCE_PWM 0x110 108 #define CLK_SOURCE_D_AUDIO 0x3d0 109 #define CLK_SOURCE_DAM0 0x3d8 110 #define CLK_SOURCE_DAM1 0x3dc 111 #define CLK_SOURCE_DAM2 0x3e0 112 #define CLK_SOURCE_3D2 0x3b0 113 #define CLK_SOURCE_2D 0x15c 114 #define CLK_SOURCE_HDMI 0x18c 115 #define CLK_SOURCE_DSIB 0xd0 116 #define CLK_SOURCE_SE 0x42c 117 #define CLK_SOURCE_EMC 0x19c 118 119 #define AUDIO_SYNC_DOUBLER 0x49c 120 121 /* Tegra CPU clock and reset control regs */ 122 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 123 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 124 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 125 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 126 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 127 128 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 129 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 130 131 #define CLK_RESET_CCLK_BURST 0x20 132 #define CLK_RESET_CCLK_DIVIDER 0x24 133 #define CLK_RESET_PLLX_BASE 0xe0 134 #define CLK_RESET_PLLX_MISC 0xe4 135 136 #define CLK_RESET_SOURCE_CSITE 0x1d4 137 138 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 139 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 140 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 141 #define CLK_RESET_CCLK_IDLE_POLICY 1 142 #define CLK_RESET_CCLK_RUN_POLICY 2 143 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 144 145 /* PLLM override registers */ 146 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 147 148 #ifdef CONFIG_PM_SLEEP 149 static struct cpu_clk_suspend_context { 150 u32 pllx_misc; 151 u32 pllx_base; 152 153 u32 cpu_burst; 154 u32 clk_csite_src; 155 u32 cclk_divider; 156 } tegra30_cpu_clk_sctx; 157 #endif 158 159 static void __iomem *clk_base; 160 static void __iomem *pmc_base; 161 static unsigned long input_freq; 162 163 static DEFINE_SPINLOCK(cml_lock); 164 static DEFINE_SPINLOCK(pll_d_lock); 165 static DEFINE_SPINLOCK(emc_lock); 166 167 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 168 _clk_num, _gate_flags, _clk_id) \ 169 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 170 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 171 _clk_num, _gate_flags, _clk_id) 172 173 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ 174 _clk_num, _gate_flags, _clk_id) \ 175 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 176 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 177 _clk_num, _gate_flags, _clk_id) 178 179 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ 180 _clk_num, _gate_flags, _clk_id) \ 181 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 182 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 183 TEGRA_DIVIDER_ROUND_UP, _clk_num, \ 184 _gate_flags, _clk_id) 185 186 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 187 _mux_shift, _mux_width, _clk_num, \ 188 _gate_flags, _clk_id) \ 189 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 190 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\ 191 _clk_num, _gate_flags, \ 192 _clk_id) 193 194 static struct clk **clks; 195 196 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 197 { 12000000, 1040000000, 520, 6, 1, 8 }, 198 { 13000000, 1040000000, 480, 6, 1, 8 }, 199 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */ 200 { 19200000, 1040000000, 325, 6, 1, 6 }, 201 { 26000000, 1040000000, 520, 13, 1, 8 }, 202 { 12000000, 832000000, 416, 6, 1, 8 }, 203 { 13000000, 832000000, 832, 13, 1, 8 }, 204 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */ 205 { 19200000, 832000000, 260, 6, 1, 8 }, 206 { 26000000, 832000000, 416, 13, 1, 8 }, 207 { 12000000, 624000000, 624, 12, 1, 8 }, 208 { 13000000, 624000000, 624, 13, 1, 8 }, 209 { 16800000, 600000000, 520, 14, 1, 8 }, 210 { 19200000, 624000000, 520, 16, 1, 8 }, 211 { 26000000, 624000000, 624, 26, 1, 8 }, 212 { 12000000, 600000000, 600, 12, 1, 8 }, 213 { 13000000, 600000000, 600, 13, 1, 8 }, 214 { 16800000, 600000000, 500, 14, 1, 8 }, 215 { 19200000, 600000000, 375, 12, 1, 6 }, 216 { 26000000, 600000000, 600, 26, 1, 8 }, 217 { 12000000, 520000000, 520, 12, 1, 8 }, 218 { 13000000, 520000000, 520, 13, 1, 8 }, 219 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */ 220 { 19200000, 520000000, 325, 12, 1, 6 }, 221 { 26000000, 520000000, 520, 26, 1, 8 }, 222 { 12000000, 416000000, 416, 12, 1, 8 }, 223 { 13000000, 416000000, 416, 13, 1, 8 }, 224 { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */ 225 { 19200000, 416000000, 260, 12, 1, 6 }, 226 { 26000000, 416000000, 416, 26, 1, 8 }, 227 { 0, 0, 0, 0, 0, 0 }, 228 }; 229 230 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 231 { 12000000, 666000000, 666, 12, 1, 8 }, 232 { 13000000, 666000000, 666, 13, 1, 8 }, 233 { 16800000, 666000000, 555, 14, 1, 8 }, 234 { 19200000, 666000000, 555, 16, 1, 8 }, 235 { 26000000, 666000000, 666, 26, 1, 8 }, 236 { 12000000, 600000000, 600, 12, 1, 8 }, 237 { 13000000, 600000000, 600, 13, 1, 8 }, 238 { 16800000, 600000000, 500, 14, 1, 8 }, 239 { 19200000, 600000000, 375, 12, 1, 6 }, 240 { 26000000, 600000000, 600, 26, 1, 8 }, 241 { 0, 0, 0, 0, 0, 0 }, 242 }; 243 244 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 245 { 12000000, 216000000, 432, 12, 2, 8 }, 246 { 13000000, 216000000, 432, 13, 2, 8 }, 247 { 16800000, 216000000, 360, 14, 2, 8 }, 248 { 19200000, 216000000, 360, 16, 2, 8 }, 249 { 26000000, 216000000, 432, 26, 2, 8 }, 250 { 0, 0, 0, 0, 0, 0 }, 251 }; 252 253 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 254 { 9600000, 564480000, 294, 5, 1, 4 }, 255 { 9600000, 552960000, 288, 5, 1, 4 }, 256 { 9600000, 24000000, 5, 2, 1, 1 }, 257 { 28800000, 56448000, 49, 25, 1, 1 }, 258 { 28800000, 73728000, 64, 25, 1, 1 }, 259 { 28800000, 24000000, 5, 6, 1, 1 }, 260 { 0, 0, 0, 0, 0, 0 }, 261 }; 262 263 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 264 { 12000000, 216000000, 216, 12, 1, 4 }, 265 { 13000000, 216000000, 216, 13, 1, 4 }, 266 { 16800000, 216000000, 180, 14, 1, 4 }, 267 { 19200000, 216000000, 180, 16, 1, 4 }, 268 { 26000000, 216000000, 216, 26, 1, 4 }, 269 { 12000000, 594000000, 594, 12, 1, 8 }, 270 { 13000000, 594000000, 594, 13, 1, 8 }, 271 { 16800000, 594000000, 495, 14, 1, 8 }, 272 { 19200000, 594000000, 495, 16, 1, 8 }, 273 { 26000000, 594000000, 594, 26, 1, 8 }, 274 { 12000000, 1000000000, 1000, 12, 1, 12 }, 275 { 13000000, 1000000000, 1000, 13, 1, 12 }, 276 { 19200000, 1000000000, 625, 12, 1, 8 }, 277 { 26000000, 1000000000, 1000, 26, 1, 12 }, 278 { 0, 0, 0, 0, 0, 0 }, 279 }; 280 281 static const struct pdiv_map pllu_p[] = { 282 { .pdiv = 1, .hw_val = 1 }, 283 { .pdiv = 2, .hw_val = 0 }, 284 { .pdiv = 0, .hw_val = 0 }, 285 }; 286 287 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 288 { 12000000, 480000000, 960, 12, 2, 12 }, 289 { 13000000, 480000000, 960, 13, 2, 12 }, 290 { 16800000, 480000000, 400, 7, 2, 5 }, 291 { 19200000, 480000000, 200, 4, 2, 3 }, 292 { 26000000, 480000000, 960, 26, 2, 12 }, 293 { 0, 0, 0, 0, 0, 0 }, 294 }; 295 296 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 297 /* 1.7 GHz */ 298 { 12000000, 1700000000, 850, 6, 1, 8 }, 299 { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */ 300 { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */ 301 { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */ 302 { 26000000, 1700000000, 850, 13, 1, 8 }, 303 /* 1.6 GHz */ 304 { 12000000, 1600000000, 800, 6, 1, 8 }, 305 { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */ 306 { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */ 307 { 19200000, 1600000000, 500, 6, 1, 8 }, 308 { 26000000, 1600000000, 800, 13, 1, 8 }, 309 /* 1.5 GHz */ 310 { 12000000, 1500000000, 750, 6, 1, 8 }, 311 { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */ 312 { 16800000, 1500000000, 625, 7, 1, 8 }, 313 { 19200000, 1500000000, 625, 8, 1, 8 }, 314 { 26000000, 1500000000, 750, 13, 1, 8 }, 315 /* 1.4 GHz */ 316 { 12000000, 1400000000, 700, 6, 1, 8 }, 317 { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */ 318 { 16800000, 1400000000, 1000, 12, 1, 8 }, 319 { 19200000, 1400000000, 875, 12, 1, 8 }, 320 { 26000000, 1400000000, 700, 13, 1, 8 }, 321 /* 1.3 GHz */ 322 { 12000000, 1300000000, 975, 9, 1, 8 }, 323 { 13000000, 1300000000, 1000, 10, 1, 8 }, 324 { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */ 325 { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */ 326 { 26000000, 1300000000, 650, 13, 1, 8 }, 327 /* 1.2 GHz */ 328 { 12000000, 1200000000, 1000, 10, 1, 8 }, 329 { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */ 330 { 16800000, 1200000000, 1000, 14, 1, 8 }, 331 { 19200000, 1200000000, 1000, 16, 1, 8 }, 332 { 26000000, 1200000000, 600, 13, 1, 8 }, 333 /* 1.1 GHz */ 334 { 12000000, 1100000000, 825, 9, 1, 8 }, 335 { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */ 336 { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */ 337 { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */ 338 { 26000000, 1100000000, 550, 13, 1, 8 }, 339 /* 1 GHz */ 340 { 12000000, 1000000000, 1000, 12, 1, 8 }, 341 { 13000000, 1000000000, 1000, 13, 1, 8 }, 342 { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */ 343 { 19200000, 1000000000, 625, 12, 1, 8 }, 344 { 26000000, 1000000000, 1000, 26, 1, 8 }, 345 { 0, 0, 0, 0, 0, 0 }, 346 }; 347 348 static const struct pdiv_map plle_p[] = { 349 { .pdiv = 18, .hw_val = 18 }, 350 { .pdiv = 24, .hw_val = 24 }, 351 { .pdiv = 0, .hw_val = 0 }, 352 }; 353 354 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 355 /* PLLE special case: use cpcon field to store cml divider value */ 356 { 12000000, 100000000, 150, 1, 18, 11 }, 357 { 216000000, 100000000, 200, 18, 24, 13 }, 358 { 0, 0, 0, 0, 0, 0 }, 359 }; 360 361 /* PLL parameters */ 362 static struct tegra_clk_pll_params pll_c_params __ro_after_init = { 363 .input_min = 2000000, 364 .input_max = 31000000, 365 .cf_min = 1000000, 366 .cf_max = 6000000, 367 .vco_min = 20000000, 368 .vco_max = 1400000000, 369 .base_reg = PLLC_BASE, 370 .misc_reg = PLLC_MISC, 371 .lock_mask = PLL_BASE_LOCK, 372 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 373 .lock_delay = 300, 374 .freq_table = pll_c_freq_table, 375 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 376 TEGRA_PLL_HAS_LOCK_ENABLE, 377 }; 378 379 static struct div_nmp pllm_nmp = { 380 .divn_shift = 8, 381 .divn_width = 10, 382 .override_divn_shift = 5, 383 .divm_shift = 0, 384 .divm_width = 5, 385 .override_divm_shift = 0, 386 .divp_shift = 20, 387 .divp_width = 3, 388 .override_divp_shift = 15, 389 }; 390 391 static struct tegra_clk_pll_params pll_m_params __ro_after_init = { 392 .input_min = 2000000, 393 .input_max = 31000000, 394 .cf_min = 1000000, 395 .cf_max = 6000000, 396 .vco_min = 20000000, 397 .vco_max = 1200000000, 398 .base_reg = PLLM_BASE, 399 .misc_reg = PLLM_MISC, 400 .lock_mask = PLL_BASE_LOCK, 401 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 402 .lock_delay = 300, 403 .div_nmp = &pllm_nmp, 404 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 405 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 406 .freq_table = pll_m_freq_table, 407 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 408 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | 409 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED, 410 }; 411 412 static struct tegra_clk_pll_params pll_p_params __ro_after_init = { 413 .input_min = 2000000, 414 .input_max = 31000000, 415 .cf_min = 1000000, 416 .cf_max = 6000000, 417 .vco_min = 20000000, 418 .vco_max = 1400000000, 419 .base_reg = PLLP_BASE, 420 .misc_reg = PLLP_MISC, 421 .lock_mask = PLL_BASE_LOCK, 422 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 423 .lock_delay = 300, 424 .freq_table = pll_p_freq_table, 425 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 426 TEGRA_PLL_HAS_LOCK_ENABLE, 427 .fixed_rate = 408000000, 428 }; 429 430 static struct tegra_clk_pll_params pll_a_params = { 431 .input_min = 2000000, 432 .input_max = 31000000, 433 .cf_min = 1000000, 434 .cf_max = 6000000, 435 .vco_min = 20000000, 436 .vco_max = 1400000000, 437 .base_reg = PLLA_BASE, 438 .misc_reg = PLLA_MISC, 439 .lock_mask = PLL_BASE_LOCK, 440 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 441 .lock_delay = 300, 442 .freq_table = pll_a_freq_table, 443 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 444 TEGRA_PLL_HAS_LOCK_ENABLE, 445 }; 446 447 static struct tegra_clk_pll_params pll_d_params __ro_after_init = { 448 .input_min = 2000000, 449 .input_max = 40000000, 450 .cf_min = 1000000, 451 .cf_max = 6000000, 452 .vco_min = 40000000, 453 .vco_max = 1000000000, 454 .base_reg = PLLD_BASE, 455 .misc_reg = PLLD_MISC, 456 .lock_mask = PLL_BASE_LOCK, 457 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 458 .lock_delay = 1000, 459 .freq_table = pll_d_freq_table, 460 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 461 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 462 }; 463 464 static struct tegra_clk_pll_params pll_d2_params __ro_after_init = { 465 .input_min = 2000000, 466 .input_max = 40000000, 467 .cf_min = 1000000, 468 .cf_max = 6000000, 469 .vco_min = 40000000, 470 .vco_max = 1000000000, 471 .base_reg = PLLD2_BASE, 472 .misc_reg = PLLD2_MISC, 473 .lock_mask = PLL_BASE_LOCK, 474 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 475 .lock_delay = 1000, 476 .freq_table = pll_d_freq_table, 477 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 478 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 479 }; 480 481 static struct tegra_clk_pll_params pll_u_params __ro_after_init = { 482 .input_min = 2000000, 483 .input_max = 40000000, 484 .cf_min = 1000000, 485 .cf_max = 6000000, 486 .vco_min = 48000000, 487 .vco_max = 960000000, 488 .base_reg = PLLU_BASE, 489 .misc_reg = PLLU_MISC, 490 .lock_mask = PLL_BASE_LOCK, 491 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 492 .lock_delay = 1000, 493 .pdiv_tohw = pllu_p, 494 .freq_table = pll_u_freq_table, 495 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 496 TEGRA_PLL_HAS_LOCK_ENABLE, 497 }; 498 499 static struct tegra_clk_pll_params pll_x_params __ro_after_init = { 500 .input_min = 2000000, 501 .input_max = 31000000, 502 .cf_min = 1000000, 503 .cf_max = 6000000, 504 .vco_min = 20000000, 505 .vco_max = 1700000000, 506 .base_reg = PLLX_BASE, 507 .misc_reg = PLLX_MISC, 508 .lock_mask = PLL_BASE_LOCK, 509 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 510 .lock_delay = 300, 511 .freq_table = pll_x_freq_table, 512 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | 513 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 514 }; 515 516 static struct tegra_clk_pll_params pll_e_params __ro_after_init = { 517 .input_min = 12000000, 518 .input_max = 216000000, 519 .cf_min = 12000000, 520 .cf_max = 12000000, 521 .vco_min = 1200000000, 522 .vco_max = 2400000000U, 523 .base_reg = PLLE_BASE, 524 .misc_reg = PLLE_MISC, 525 .lock_mask = PLLE_MISC_LOCK, 526 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 527 .lock_delay = 300, 528 .pdiv_tohw = plle_p, 529 .freq_table = pll_e_freq_table, 530 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED | 531 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC, 532 .fixed_rate = 100000000, 533 }; 534 535 static unsigned long tegra30_input_freq[] = { 536 [ 0] = 13000000, 537 [ 1] = 16800000, 538 [ 4] = 19200000, 539 [ 5] = 38400000, 540 [ 8] = 12000000, 541 [ 9] = 48000000, 542 [12] = 26000000, 543 }; 544 545 static struct tegra_devclk devclks[] __initdata = { 546 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C }, 547 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 }, 548 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P }, 549 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 }, 550 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 }, 551 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 }, 552 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 }, 553 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M }, 554 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 }, 555 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X }, 556 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 }, 557 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U }, 558 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D }, 559 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 }, 560 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 }, 561 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 }, 562 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A }, 563 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 }, 564 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E }, 565 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC }, 566 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC }, 567 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC }, 568 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC }, 569 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC }, 570 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC }, 571 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC }, 572 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 }, 573 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 }, 574 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 }, 575 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 }, 576 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 }, 577 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF }, 578 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X }, 579 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X }, 580 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X }, 581 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X }, 582 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X }, 583 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X }, 584 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 }, 585 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 }, 586 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 }, 587 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK }, 588 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G }, 589 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP }, 590 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK }, 591 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK }, 592 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK }, 593 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD }, 594 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC }, 595 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K }, 596 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 }, 597 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 }, 598 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 }, 599 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 }, 600 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M }, 601 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF }, 602 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS }, 603 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP }, 604 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA }, 605 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV }, 606 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA }, 607 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI }, 608 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP }, 609 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE }, 610 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI }, 611 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE }, 612 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN }, 613 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF }, 614 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI }, 615 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA }, 616 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC }, 617 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER }, 618 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC }, 619 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD }, 620 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 }, 621 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 }, 622 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE }, 623 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD }, 624 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV }, 625 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 }, 626 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 }, 627 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 }, 628 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 }, 629 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 }, 630 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT }, 631 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN }, 632 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO }, 633 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 }, 634 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 }, 635 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 }, 636 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA }, 637 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X }, 638 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 }, 639 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 }, 640 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 }, 641 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 }, 642 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 }, 643 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 }, 644 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB }, 645 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA }, 646 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH }, 647 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED }, 648 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR }, 649 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE }, 650 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA }, 651 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR }, 652 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI }, 653 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR }, 654 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW }, 655 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE }, 656 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI }, 657 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP }, 658 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE }, 659 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X }, 660 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D }, 661 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 }, 662 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D }, 663 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE }, 664 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT }, 665 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR }, 666 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 }, 667 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 }, 668 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 }, 669 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 }, 670 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE }, 671 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO }, 672 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC }, 673 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON }, 674 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR }, 675 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 }, 676 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 }, 677 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 }, 678 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 }, 679 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 }, 680 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA }, 681 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB }, 682 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC }, 683 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD }, 684 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE }, 685 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI }, 686 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 }, 687 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 }, 688 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 }, 689 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM }, 690 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 }, 691 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 }, 692 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB }, 693 }; 694 695 static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { 696 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true }, 697 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true }, 698 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true }, 699 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true }, 700 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true }, 701 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true }, 702 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true }, 703 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true }, 704 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true }, 705 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true }, 706 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true }, 707 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true }, 708 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true }, 709 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true }, 710 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true }, 711 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true }, 712 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true }, 713 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true }, 714 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true }, 715 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true }, 716 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true }, 717 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true }, 718 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true }, 719 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true }, 720 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true }, 721 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true }, 722 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true }, 723 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true }, 724 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true }, 725 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true }, 726 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true }, 727 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true }, 728 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true }, 729 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true }, 730 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true }, 731 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true }, 732 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true }, 733 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true }, 734 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true }, 735 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true }, 736 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true }, 737 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true }, 738 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true }, 739 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true }, 740 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true }, 741 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true }, 742 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true }, 743 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true }, 744 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true }, 745 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true }, 746 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true }, 747 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true }, 748 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true }, 749 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true }, 750 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true }, 751 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true }, 752 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true }, 753 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true }, 754 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true }, 755 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true }, 756 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true }, 757 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true }, 758 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true }, 759 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true }, 760 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true }, 761 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true }, 762 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true }, 763 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true }, 764 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true }, 765 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true }, 766 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true }, 767 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true }, 768 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true }, 769 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true }, 770 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true }, 771 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true }, 772 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true }, 773 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true }, 774 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true }, 775 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true }, 776 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true }, 777 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true }, 778 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true }, 779 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true }, 780 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true }, 781 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true }, 782 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true }, 783 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true }, 784 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true }, 785 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true }, 786 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true }, 787 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true }, 788 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true }, 789 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true }, 790 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true }, 791 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true }, 792 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true }, 793 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, 794 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true }, 795 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true }, 796 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true }, 797 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true }, 798 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true }, 799 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true }, 800 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true }, 801 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true }, 802 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true }, 803 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true }, 804 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true }, 805 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true }, 806 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true }, 807 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true }, 808 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true }, 809 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true }, 810 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true }, 811 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true }, 812 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true }, 813 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true }, 814 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true }, 815 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true }, 816 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true }, 817 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true }, 818 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true }, 819 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true }, 820 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, 821 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true }, 822 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = true }, 823 }; 824 825 static const char *pll_e_parents[] = { "pll_ref", "pll_p" }; 826 827 static void __init tegra30_pll_init(void) 828 { 829 struct clk *clk; 830 831 /* PLLC */ 832 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 833 &pll_c_params, NULL); 834 clks[TEGRA30_CLK_PLL_C] = clk; 835 836 /* PLLC_OUT1 */ 837 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 838 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 839 8, 8, 1, NULL); 840 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 841 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 842 0, NULL); 843 clks[TEGRA30_CLK_PLL_C_OUT1] = clk; 844 845 /* PLLM */ 846 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 847 CLK_SET_RATE_GATE, &pll_m_params, NULL); 848 clks[TEGRA30_CLK_PLL_M] = clk; 849 850 /* PLLM_OUT1 */ 851 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 852 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 853 8, 8, 1, NULL); 854 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 855 clk_base + PLLM_OUT, 1, 0, 856 CLK_SET_RATE_PARENT, 0, NULL); 857 clks[TEGRA30_CLK_PLL_M_OUT1] = clk; 858 859 /* PLLX */ 860 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 861 &pll_x_params, NULL); 862 clks[TEGRA30_CLK_PLL_X] = clk; 863 864 /* PLLX_OUT0 */ 865 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 866 CLK_SET_RATE_PARENT, 1, 2); 867 clks[TEGRA30_CLK_PLL_X_OUT0] = clk; 868 869 /* PLLU */ 870 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, 871 &pll_u_params, NULL); 872 clks[TEGRA30_CLK_PLL_U] = clk; 873 874 /* PLLD */ 875 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 876 &pll_d_params, &pll_d_lock); 877 clks[TEGRA30_CLK_PLL_D] = clk; 878 879 /* PLLD_OUT0 */ 880 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 881 CLK_SET_RATE_PARENT, 1, 2); 882 clks[TEGRA30_CLK_PLL_D_OUT0] = clk; 883 884 /* PLLD2 */ 885 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 886 &pll_d2_params, NULL); 887 clks[TEGRA30_CLK_PLL_D2] = clk; 888 889 /* PLLD2_OUT0 */ 890 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 891 CLK_SET_RATE_PARENT, 1, 2); 892 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk; 893 894 /* PLLE */ 895 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 896 ARRAY_SIZE(pll_e_parents), 897 CLK_SET_RATE_NO_REPARENT, 898 clk_base + PLLE_AUX, 2, 1, 0, NULL); 899 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 900 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); 901 clks[TEGRA30_CLK_PLL_E] = clk; 902 } 903 904 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 905 "pll_p_cclkg", "pll_p_out4_cclkg", 906 "pll_p_out3_cclkg", "unused", "pll_x" }; 907 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 908 "pll_p_cclklp", "pll_p_out4_cclklp", 909 "pll_p_out3_cclklp", "unused", "pll_x", 910 "pll_x_out0" }; 911 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 912 "pll_p_out3", "pll_p_out2", "unused", 913 "clk_32k", "pll_m_out1" }; 914 915 static void __init tegra30_super_clk_init(void) 916 { 917 struct clk *clk; 918 919 /* 920 * Clock input to cclk_g divided from pll_p using 921 * U71 divider of cclk_g. 922 */ 923 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 924 clk_base + SUPER_CCLKG_DIVIDER, 0, 925 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 926 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 927 928 /* 929 * Clock input to cclk_g divided from pll_p_out3 using 930 * U71 divider of cclk_g. 931 */ 932 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 933 clk_base + SUPER_CCLKG_DIVIDER, 0, 934 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 935 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 936 937 /* 938 * Clock input to cclk_g divided from pll_p_out4 using 939 * U71 divider of cclk_g. 940 */ 941 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 942 clk_base + SUPER_CCLKG_DIVIDER, 0, 943 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 944 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 945 946 /* CCLKG */ 947 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 948 ARRAY_SIZE(cclk_g_parents), 949 CLK_SET_RATE_PARENT, 950 clk_base + CCLKG_BURST_POLICY, 951 0, 4, 0, 0, NULL); 952 clks[TEGRA30_CLK_CCLK_G] = clk; 953 954 /* 955 * Clock input to cclk_lp divided from pll_p using 956 * U71 divider of cclk_lp. 957 */ 958 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 959 clk_base + SUPER_CCLKLP_DIVIDER, 0, 960 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 961 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 962 963 /* 964 * Clock input to cclk_lp divided from pll_p_out3 using 965 * U71 divider of cclk_lp. 966 */ 967 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 968 clk_base + SUPER_CCLKLP_DIVIDER, 0, 969 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 970 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 971 972 /* 973 * Clock input to cclk_lp divided from pll_p_out4 using 974 * U71 divider of cclk_lp. 975 */ 976 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 977 clk_base + SUPER_CCLKLP_DIVIDER, 0, 978 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 979 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 980 981 /* CCLKLP */ 982 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 983 ARRAY_SIZE(cclk_lp_parents), 984 CLK_SET_RATE_PARENT, 985 clk_base + CCLKLP_BURST_POLICY, 986 TEGRA_DIVIDER_2, 4, 8, 9, 987 NULL); 988 clks[TEGRA30_CLK_CCLK_LP] = clk; 989 990 /* SCLK */ 991 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 992 ARRAY_SIZE(sclk_parents), 993 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 994 clk_base + SCLK_BURST_POLICY, 995 0, 4, 0, 0, NULL); 996 clks[TEGRA30_CLK_SCLK] = clk; 997 998 /* twd */ 999 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1000 CLK_SET_RATE_PARENT, 1, 2); 1001 clks[TEGRA30_CLK_TWD] = clk; 1002 1003 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL); 1004 } 1005 1006 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1007 "clk_m" }; 1008 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1009 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1010 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1011 "clk_m" }; 1012 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1013 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1014 "pll_a_out0", "pll_c", 1015 "pll_d2_out0", "clk_m" }; 1016 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1017 "pll_d2_out0" }; 1018 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" }; 1019 1020 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1021 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT), 1022 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO), 1023 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0), 1024 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1), 1025 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2), 1026 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2), 1027 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE), 1028 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI), 1029 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM), 1030 }; 1031 1032 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1033 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB), 1034 }; 1035 1036 static void __init tegra30_periph_clk_init(void) 1037 { 1038 struct tegra_periph_init_data *data; 1039 struct clk *clk; 1040 unsigned int i; 1041 1042 /* dsia */ 1043 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1044 0, 48, periph_clk_enb_refcnt); 1045 clks[TEGRA30_CLK_DSIA] = clk; 1046 1047 /* pcie */ 1048 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1049 70, periph_clk_enb_refcnt); 1050 clks[TEGRA30_CLK_PCIE] = clk; 1051 1052 /* afi */ 1053 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1054 periph_clk_enb_refcnt); 1055 clks[TEGRA30_CLK_AFI] = clk; 1056 1057 /* emc */ 1058 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1059 ARRAY_SIZE(mux_pllmcp_clkm), 1060 CLK_SET_RATE_NO_REPARENT, 1061 clk_base + CLK_SOURCE_EMC, 1062 30, 2, 0, &emc_lock); 1063 1064 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 1065 &emc_lock); 1066 clks[TEGRA30_CLK_MC] = clk; 1067 1068 /* cml0 */ 1069 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1070 0, 0, &cml_lock); 1071 clks[TEGRA30_CLK_CML0] = clk; 1072 1073 /* cml1 */ 1074 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1075 1, 0, &cml_lock); 1076 clks[TEGRA30_CLK_CML1] = clk; 1077 1078 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1079 data = &tegra_periph_clk_list[i]; 1080 clk = tegra_clk_register_periph_data(clk_base, data); 1081 clks[data->clk_id] = clk; 1082 } 1083 1084 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1085 data = &tegra_periph_nodiv_clk_list[i]; 1086 clk = tegra_clk_register_periph_nodiv(data->name, 1087 data->p.parent_names, 1088 data->num_parents, &data->periph, 1089 clk_base, data->offset); 1090 clks[data->clk_id] = clk; 1091 } 1092 1093 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params); 1094 } 1095 1096 /* Tegra30 CPU clock and reset control functions */ 1097 static void tegra30_wait_cpu_in_reset(u32 cpu) 1098 { 1099 unsigned int reg; 1100 1101 do { 1102 reg = readl(clk_base + 1103 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1104 cpu_relax(); 1105 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1106 1107 return; 1108 } 1109 1110 static void tegra30_put_cpu_in_reset(u32 cpu) 1111 { 1112 writel(CPU_RESET(cpu), 1113 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1114 dmb(); 1115 } 1116 1117 static void tegra30_cpu_out_of_reset(u32 cpu) 1118 { 1119 writel(CPU_RESET(cpu), 1120 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1121 wmb(); 1122 } 1123 1124 static void tegra30_enable_cpu_clock(u32 cpu) 1125 { 1126 unsigned int reg; 1127 1128 writel(CPU_CLOCK(cpu), 1129 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1130 reg = readl(clk_base + 1131 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1132 } 1133 1134 static void tegra30_disable_cpu_clock(u32 cpu) 1135 { 1136 unsigned int reg; 1137 1138 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1139 writel(reg | CPU_CLOCK(cpu), 1140 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1141 } 1142 1143 #ifdef CONFIG_PM_SLEEP 1144 static bool tegra30_cpu_rail_off_ready(void) 1145 { 1146 unsigned int cpu_rst_status; 1147 int cpu_pwr_status; 1148 1149 cpu_rst_status = readl(clk_base + 1150 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1151 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || 1152 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || 1153 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); 1154 1155 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1156 return false; 1157 1158 return true; 1159 } 1160 1161 static void tegra30_cpu_clock_suspend(void) 1162 { 1163 /* switch coresite to clk_m, save off original source */ 1164 tegra30_cpu_clk_sctx.clk_csite_src = 1165 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1166 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE); 1167 1168 tegra30_cpu_clk_sctx.cpu_burst = 1169 readl(clk_base + CLK_RESET_CCLK_BURST); 1170 tegra30_cpu_clk_sctx.pllx_base = 1171 readl(clk_base + CLK_RESET_PLLX_BASE); 1172 tegra30_cpu_clk_sctx.pllx_misc = 1173 readl(clk_base + CLK_RESET_PLLX_MISC); 1174 tegra30_cpu_clk_sctx.cclk_divider = 1175 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1176 } 1177 1178 static void tegra30_cpu_clock_resume(void) 1179 { 1180 unsigned int reg, policy; 1181 1182 /* Is CPU complex already running on PLLX? */ 1183 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1184 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1185 1186 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1187 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1188 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1189 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1190 else 1191 BUG(); 1192 1193 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1194 /* restore PLLX settings if CPU is on different PLL */ 1195 writel(tegra30_cpu_clk_sctx.pllx_misc, 1196 clk_base + CLK_RESET_PLLX_MISC); 1197 writel(tegra30_cpu_clk_sctx.pllx_base, 1198 clk_base + CLK_RESET_PLLX_BASE); 1199 1200 /* wait for PLL stabilization if PLLX was enabled */ 1201 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1202 udelay(300); 1203 } 1204 1205 /* 1206 * Restore original burst policy setting for calls resulting from CPU 1207 * LP2 in idle or system suspend. 1208 */ 1209 writel(tegra30_cpu_clk_sctx.cclk_divider, 1210 clk_base + CLK_RESET_CCLK_DIVIDER); 1211 writel(tegra30_cpu_clk_sctx.cpu_burst, 1212 clk_base + CLK_RESET_CCLK_BURST); 1213 1214 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1215 clk_base + CLK_RESET_SOURCE_CSITE); 1216 } 1217 #endif 1218 1219 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1220 .wait_for_reset = tegra30_wait_cpu_in_reset, 1221 .put_in_reset = tegra30_put_cpu_in_reset, 1222 .out_of_reset = tegra30_cpu_out_of_reset, 1223 .enable_clock = tegra30_enable_cpu_clock, 1224 .disable_clock = tegra30_disable_cpu_clock, 1225 #ifdef CONFIG_PM_SLEEP 1226 .rail_off_ready = tegra30_cpu_rail_off_ready, 1227 .suspend = tegra30_cpu_clock_suspend, 1228 .resume = tegra30_cpu_clock_resume, 1229 #endif 1230 }; 1231 1232 static struct tegra_clk_init_table init_table[] __initdata = { 1233 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1234 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1235 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1236 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1237 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1238 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 }, 1239 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 }, 1240 { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 }, 1241 { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 }, 1242 { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1243 { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1244 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1245 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1246 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1247 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1248 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1249 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1250 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1251 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1252 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1253 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1254 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1255 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1256 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1257 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1258 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1259 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1260 { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, 1261 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, 1262 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, 1263 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, 1264 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1265 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1266 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1267 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1268 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, 1269 { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, 1270 /* must be the last entry */ 1271 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, 1272 }; 1273 1274 static void __init tegra30_clock_apply_init_table(void) 1275 { 1276 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX); 1277 } 1278 1279 /* 1280 * Some clocks may be used by different drivers depending on the board 1281 * configuration. List those here to register them twice in the clock lookup 1282 * table under two names. 1283 */ 1284 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1285 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL), 1286 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL), 1287 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL), 1288 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"), 1289 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"), 1290 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"), 1291 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"), 1292 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"), 1293 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL), 1294 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"), 1295 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"), 1296 /* must be the last entry */ 1297 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), 1298 }; 1299 1300 static const struct of_device_id pmc_match[] __initconst = { 1301 { .compatible = "nvidia,tegra30-pmc" }, 1302 { }, 1303 }; 1304 1305 static struct tegra_audio_clk_info tegra30_audio_plls[] = { 1306 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, 1307 }; 1308 1309 static void __init tegra30_clock_init(struct device_node *np) 1310 { 1311 struct device_node *node; 1312 1313 clk_base = of_iomap(np, 0); 1314 if (!clk_base) { 1315 pr_err("ioremap tegra30 CAR failed\n"); 1316 return; 1317 } 1318 1319 node = of_find_matching_node(NULL, pmc_match); 1320 if (!node) { 1321 pr_err("Failed to find pmc node\n"); 1322 BUG(); 1323 } 1324 1325 pmc_base = of_iomap(node, 0); 1326 if (!pmc_base) { 1327 pr_err("Can't map pmc registers\n"); 1328 BUG(); 1329 } 1330 1331 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX, 1332 TEGRA30_CLK_PERIPH_BANKS); 1333 if (!clks) 1334 return; 1335 1336 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq, 1337 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq, 1338 NULL) < 0) 1339 return; 1340 1341 tegra_fixed_clk_init(tegra30_clks); 1342 tegra30_pll_init(); 1343 tegra30_super_clk_init(); 1344 tegra30_periph_clk_init(); 1345 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, 1346 tegra30_audio_plls, 1347 ARRAY_SIZE(tegra30_audio_plls)); 1348 tegra_pmc_clk_init(pmc_base, tegra30_clks); 1349 1350 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); 1351 1352 tegra_add_of_provider(np, of_clk_src_onecell_get); 1353 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1354 1355 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1356 1357 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 1358 } 1359 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init); 1360